lib/Target/Hexagon/HexagonTargetMachine.cpp

   1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implements the info about Hexagon target spec.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "HexagonTargetMachine.h"
  14 #include "Hexagon.h"
  15 #include "HexagonISelLowering.h"
  16 #include "HexagonMachineScheduler.h"
  17 #include "HexagonTargetObjectFile.h"
  18 #include "HexagonTargetTransformInfo.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/TargetPassConfig.h"
  21 #include "llvm/IR/LegacyPassManager.h"
  22 #include "llvm/IR/Module.h"
  23 #include "llvm/Support/CommandLine.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
  26 #include "llvm/Transforms/Scalar.h"
  27
  28 using namespace llvm;
  29
  30 static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore,
  31   cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"));
  32
  33 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
  34   cl::init(true), cl::desc("Enable RDF-based optimizations"));
  35
  36 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
  37   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
  38
  39 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
  40   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  41   cl::desc("Disable Hexagon Addressing Mode Optimization"));
  42
  43 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
  44   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  45   cl::desc("Disable Hexagon CFG Optimization"));
  46
  47 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
  48   cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
  49
  50 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
  51   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
  52
  53 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
  54   cl::init(true), cl::Hidden, cl::ZeroOrMore,
  55   cl::desc("Early expansion of MUX"));
  56
  57 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
  58   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
  59
  60 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
  61   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
  62
  63 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
  64   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
  65
  66 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
  67   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
  68
  69 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
  70   cl::desc("Enable converting conditional transfers into MUX instructions"));
  71
  72 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
  73   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
  74   "predicate instructions"));
  75
  76 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
  77   cl::init(false), cl::Hidden, cl::ZeroOrMore,
  78   cl::desc("Enable loop data prefetch on Hexagon"));
  79
  80 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
  81   cl::desc("Disable splitting double registers"));
  82
  83 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
  84   cl::Hidden, cl::desc("Bit simplification"));
  85
  86 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
  87   cl::Hidden, cl::desc("Loop rescheduling"));
  88
  89 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
  90   cl::Hidden, cl::desc("Disable backend optimizations"));
  91
  92 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
  93   cl::Hidden, cl::ZeroOrMore, cl::init(false),
  94   cl::desc("Enable Hexagon Vector print instr pass"));
  95
  96 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
  97   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
  98
  99 static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup",
 100   cl::Hidden, cl::ZeroOrMore, cl::init(true),
 101   cl::desc("Simplify the CFG after atomic expansion pass"));
 102
 103 /// HexagonTargetMachineModule - Note that this is used on hosts that
 104 /// cannot link in a library unless there are references into the
 105 /// library.  In particular, it seems that it is not possible to get
 106 /// things to work on Win32 without this.  Though it is unused, do not
 107 /// remove it.
 108 extern "C" int HexagonTargetMachineModule;
 109 int HexagonTargetMachineModule = 0;
 110
 111 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
 112   ScheduleDAGMILive *DAG =
 113     new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
 114   DAG->addMutation(make_unique<HexagonSubtarget::UsrOverflowMutation>());
 115   DAG->addMutation(make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
 116   DAG->addMutation(make_unique<HexagonSubtarget::CallMutation>());
 117   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
 118   return DAG;
 119 }
 120
 121 static MachineSchedRegistry
 122 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
 123                     createVLIWMachineSched);
 124
 125 namespace llvm {
 126   extern char &HexagonExpandCondsetsID;
 127   void initializeHexagonBitSimplifyPass(PassRegistry&);
 128   void initializeHexagonConstExtendersPass(PassRegistry&);
 129   void initializeHexagonConstPropagationPass(PassRegistry&);
 130   void initializeHexagonEarlyIfConversionPass(PassRegistry&);
 131   void initializeHexagonExpandCondsetsPass(PassRegistry&);
 132   void initializeHexagonGenMuxPass(PassRegistry&);
 133   void initializeHexagonHardwareLoopsPass(PassRegistry&);
 134   void initializeHexagonLoopIdiomRecognizePass(PassRegistry&);
 135   void initializeHexagonVectorLoopCarriedReusePass(PassRegistry&);
 136   void initializeHexagonNewValueJumpPass(PassRegistry&);
 137   void initializeHexagonOptAddrModePass(PassRegistry&);
 138   void initializeHexagonPacketizerPass(PassRegistry&);
 139   void initializeHexagonRDFOptPass(PassRegistry&);
 140   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
 141   void initializeHexagonVExtractPass(PassRegistry&);
 142   Pass *createHexagonLoopIdiomPass();
 143   Pass *createHexagonVectorLoopCarriedReusePass();
 144
 145   FunctionPass *createHexagonBitSimplify();
 146   FunctionPass *createHexagonBranchRelaxation();
 147   FunctionPass *createHexagonCallFrameInformation();
 148   FunctionPass *createHexagonCFGOptimizer();
 149   FunctionPass *createHexagonCommonGEP();
 150   FunctionPass *createHexagonConstExtenders();
 151   FunctionPass *createHexagonConstPropagationPass();
 152   FunctionPass *createHexagonCopyToCombine();
 153   FunctionPass *createHexagonEarlyIfConversion();
 154   FunctionPass *createHexagonFixupHwLoops();
 155   FunctionPass *createHexagonGenExtract();
 156   FunctionPass *createHexagonGenInsert();
 157   FunctionPass *createHexagonGenMux();
 158   FunctionPass *createHexagonGenPredicate();
 159   FunctionPass *createHexagonHardwareLoops();
 160   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
 161                                      CodeGenOpt::Level OptLevel);
 162   FunctionPass *createHexagonLoopRescheduling();
 163   FunctionPass *createHexagonNewValueJump();
 164   FunctionPass *createHexagonOptimizeSZextends();
 165   FunctionPass *createHexagonOptAddrMode();
 166   FunctionPass *createHexagonPacketizer(bool Minimal);
 167   FunctionPass *createHexagonPeephole();
 168   FunctionPass *createHexagonRDFOpt();
 169   FunctionPass *createHexagonSplitConst32AndConst64();
 170   FunctionPass *createHexagonSplitDoubleRegs();
 171   FunctionPass *createHexagonStoreWidening();
 172   FunctionPass *createHexagonVectorPrint();
 173   FunctionPass *createHexagonVExtract();
 174 } // end namespace llvm;
 175
 176 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
 177   if (!RM.hasValue())
 178     return Reloc::Static;
 179   return *RM;
 180 }
 181
 182 extern "C" void LLVMInitializeHexagonTarget() {
 183   // Register the target.
 184   RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget());
 185
 186   PassRegistry &PR = *PassRegistry::getPassRegistry();
 187   initializeHexagonBitSimplifyPass(PR);
 188   initializeHexagonConstExtendersPass(PR);
 189   initializeHexagonConstPropagationPass(PR);
 190   initializeHexagonEarlyIfConversionPass(PR);
 191   initializeHexagonGenMuxPass(PR);
 192   initializeHexagonHardwareLoopsPass(PR);
 193   initializeHexagonLoopIdiomRecognizePass(PR);
 194   initializeHexagonVectorLoopCarriedReusePass(PR);
 195   initializeHexagonNewValueJumpPass(PR);
 196   initializeHexagonOptAddrModePass(PR);
 197   initializeHexagonPacketizerPass(PR);
 198   initializeHexagonRDFOptPass(PR);
 199   initializeHexagonSplitDoubleRegsPass(PR);
 200   initializeHexagonVExtractPass(PR);
 201 }
 202
 203 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
 204                                            StringRef CPU, StringRef FS,
 205                                            const TargetOptions &Options,
 206                                            Optional<Reloc::Model> RM,
 207                                            Optional<CodeModel::Model> CM,
 208                                            CodeGenOpt::Level OL, bool JIT)
 209     // Specify the vector alignment explicitly. For v512x1, the calculated
 210     // alignment would be 512*alignment(i1), which is 512 bytes, instead of
 211     // the required minimum of 64 bytes.
 212     : LLVMTargetMachine(
 213           T,
 214           "e-m:e-p:32:32:32-a:0-n16:32-"
 215           "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
 216           "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
 217           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
 218           getEffectiveCodeModel(CM, CodeModel::Small),
 219           (HexagonNoOpt ? CodeGenOpt::None : OL)),
 220       TLOF(make_unique<HexagonTargetObjectFile>()) {
 221   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
 222   initAsmInfo();
 223 }
 224
 225 const HexagonSubtarget *
 226 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
 227   AttributeList FnAttrs = F.getAttributes();
 228   Attribute CPUAttr =
 229       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu");
 230   Attribute FSAttr =
 231       FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features");
 232
 233   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
 234                         ? CPUAttr.getValueAsString().str()
 235                         : TargetCPU;
 236   std::string FS = !FSAttr.hasAttribute(Attribute::None)
 237                        ? FSAttr.getValueAsString().str()
 238                        : TargetFS;
 239
 240   auto &I = SubtargetMap[CPU + FS];
 241   if (!I) {
 242     // This needs to be done before we create a new subtarget since any
 243     // creation will depend on the TM and the code generation flags on the
 244     // function that reside in TargetOptions.
 245     resetTargetOptions(F);
 246     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
 247   }
 248   return I.get();
 249 }
 250
 251 void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) {
 252   PMB.addExtension(
 253     PassManagerBuilder::EP_LateLoopOptimizations,
 254     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
 255       PM.add(createHexagonLoopIdiomPass());
 256     });
 257   PMB.addExtension(
 258     PassManagerBuilder::EP_LoopOptimizerEnd,
 259     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
 260       PM.add(createHexagonVectorLoopCarriedReusePass());
 261     });
 262 }
 263
 264 TargetTransformInfo
 265 HexagonTargetMachine::getTargetTransformInfo(const Function &F) {
 266   return TargetTransformInfo(HexagonTTIImpl(this, F));
 267 }
 268
 269
 270 HexagonTargetMachine::~HexagonTargetMachine() {}
 271
 272 namespace {
 273 /// Hexagon Code Generator Pass Configuration Options.
 274 class HexagonPassConfig : public TargetPassConfig {
 275 public:
 276   HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
 277     : TargetPassConfig(TM, PM) {}
 278
 279   HexagonTargetMachine &getHexagonTargetMachine() const {
 280     return getTM<HexagonTargetMachine>();
 281   }
 282
 283   ScheduleDAGInstrs *
 284   createMachineScheduler(MachineSchedContext *C) const override {
 285     return createVLIWMachineSched(C);
 286   }
 287
 288   void addIRPasses() override;
 289   bool addInstSelector() override;
 290   void addPreRegAlloc() override;
 291   void addPostRegAlloc() override;
 292   void addPreSched2() override;
 293   void addPreEmitPass() override;
 294 };
 295 } // namespace
 296
 297 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
 298   return new HexagonPassConfig(*this, PM);
 299 }
 300
 301 void HexagonPassConfig::addIRPasses() {
 302   TargetPassConfig::addIRPasses();
 303   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
 304
 305   if (!NoOpt) {
 306     addPass(createConstantPropagationPass());
 307     addPass(createDeadCodeEliminationPass());
 308   }
 309
 310   addPass(createAtomicExpandPass());
 311
 312   if (!NoOpt) {
 313     if (EnableInitialCFGCleanup)
 314       addPass(createCFGSimplificationPass(1, true, true, false, true));
 315     if (EnableLoopPrefetch)
 316       addPass(createLoopDataPrefetchPass());
 317     if (EnableCommGEP)
 318       addPass(createHexagonCommonGEP());
 319     // Replace certain combinations of shifts and ands with extracts.
 320     if (EnableGenExtract)
 321       addPass(createHexagonGenExtract());
 322   }
 323 }
 324
 325 bool HexagonPassConfig::addInstSelector() {
 326   HexagonTargetMachine &TM = getHexagonTargetMachine();
 327   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
 328
 329   if (!NoOpt)
 330     addPass(createHexagonOptimizeSZextends());
 331
 332   addPass(createHexagonISelDag(TM, getOptLevel()));
 333
 334   if (!NoOpt) {
 335     if (EnableVExtractOpt)
 336       addPass(createHexagonVExtract());
 337     // Create logical operations on predicate registers.
 338     if (EnableGenPred)
 339       addPass(createHexagonGenPredicate());
 340     // Rotate loops to expose bit-simplification opportunities.
 341     if (EnableLoopResched)
 342       addPass(createHexagonLoopRescheduling());
 343     // Split double registers.
 344     if (!DisableHSDR)
 345       addPass(createHexagonSplitDoubleRegs());
 346     // Bit simplification.
 347     if (EnableBitSimplify)
 348       addPass(createHexagonBitSimplify());
 349     addPass(createHexagonPeephole());
 350     // Constant propagation.
 351     if (!DisableHCP) {
 352       addPass(createHexagonConstPropagationPass());
 353       addPass(&UnreachableMachineBlockElimID);
 354     }
 355     if (EnableGenInsert)
 356       addPass(createHexagonGenInsert());
 357     if (EnableEarlyIf)
 358       addPass(createHexagonEarlyIfConversion());
 359   }
 360
 361   return false;
 362 }
 363
 364 void HexagonPassConfig::addPreRegAlloc() {
 365   if (getOptLevel() != CodeGenOpt::None) {
 366     if (EnableCExtOpt)
 367       addPass(createHexagonConstExtenders());
 368     if (EnableExpandCondsets)
 369       insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID);
 370     if (!DisableStoreWidening)
 371       addPass(createHexagonStoreWidening());
 372     if (!DisableHardwareLoops)
 373       addPass(createHexagonHardwareLoops());
 374   }
 375   if (TM->getOptLevel() >= CodeGenOpt::Default)
 376     addPass(&MachinePipelinerID);
 377 }
 378
 379 void HexagonPassConfig::addPostRegAlloc() {
 380   if (getOptLevel() != CodeGenOpt::None) {
 381     if (EnableRDFOpt)
 382       addPass(createHexagonRDFOpt());
 383     if (!DisableHexagonCFGOpt)
 384       addPass(createHexagonCFGOptimizer());
 385     if (!DisableAModeOpt)
 386       addPass(createHexagonOptAddrMode());
 387   }
 388 }
 389
 390 void HexagonPassConfig::addPreSched2() {
 391   addPass(createHexagonCopyToCombine());
 392   if (getOptLevel() != CodeGenOpt::None)
 393     addPass(&IfConverterID);
 394   addPass(createHexagonSplitConst32AndConst64());
 395 }
 396
 397 void HexagonPassConfig::addPreEmitPass() {
 398   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
 399
 400   if (!NoOpt)
 401     addPass(createHexagonNewValueJump());
 402
 403   addPass(createHexagonBranchRelaxation());
 404
 405   if (!NoOpt) {
 406     if (!DisableHardwareLoops)
 407       addPass(createHexagonFixupHwLoops());
 408     // Generate MUX from pairs of conditional transfers.
 409     if (EnableGenMux)
 410       addPass(createHexagonGenMux());
 411   }
 412
 413   // Packetization is mandatory: it handles gather/scatter at all opt levels.
 414   addPass(createHexagonPacketizer(NoOpt), false);
 415
 416   if (EnableVectorPrint)
 417     addPass(createHexagonVectorPrint(), false);
 418
 419   // Add CFI instructions if necessary.
 420   addPass(createHexagonCallFrameInformation(), false);
 421 }