lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h

   1 //===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file provides Mips specific target descriptions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  14 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H
  15
  16 #include "llvm/Support/DataTypes.h"
  17
  18 #include <memory>
  19
  20 namespace llvm {
  21 class MCAsmBackend;
  22 class MCCodeEmitter;
  23 class MCContext;
  24 class MCInstrInfo;
  25 class MCObjectTargetWriter;
  26 class MCRegisterInfo;
  27 class MCSubtargetInfo;
  28 class MCTargetOptions;
  29 class StringRef;
  30 class Target;
  31 class Triple;
  32 class raw_ostream;
  33 class raw_pwrite_stream;
  34
  35 Target &getTheMipsTarget();
  36 Target &getTheMipselTarget();
  37 Target &getTheMips64Target();
  38 Target &getTheMips64elTarget();
  39
  40 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
  41                                          const MCRegisterInfo &MRI,
  42                                          MCContext &Ctx);
  43 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
  44                                          const MCRegisterInfo &MRI,
  45                                          MCContext &Ctx);
  46
  47 MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
  48                                    const MCRegisterInfo &MRI,
  49                                    const MCTargetOptions &Options);
  50
  51 std::unique_ptr<MCObjectTargetWriter>
  52 createMipsELFObjectWriter(const Triple &TT, bool IsN32);
  53
  54 namespace MIPS_MC {
  55 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
  56 }
  57
  58 } // End llvm namespace
  59
  60 // Defines symbolic names for Mips registers.  This defines a mapping from
  61 // register name to register number.
  62 #define GET_REGINFO_ENUM
  63 #include "MipsGenRegisterInfo.inc"
  64
  65 // Defines symbolic names for the Mips instructions.
  66 #define GET_INSTRINFO_ENUM
  67 #include "MipsGenInstrInfo.inc"
  68
  69 #define GET_SUBTARGETINFO_ENUM
  70 #include "MipsGenSubtargetInfo.inc"
  71
  72 #endif