lib/Target/Mips/MicroMips32r6InstrInfo.td

   1 //=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes microMIPSr6 instructions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 def brtarget21_mm : Operand<OtherVT> {
  14   let EncoderMethod = "getBranchTarget21OpValueMM";
  15   let OperandType = "OPERAND_PCREL";
  16   let DecoderMethod = "DecodeBranchTarget21MM";
  17   let ParserMatchClass = MipsJumpTargetAsmOperand;
  18 }
  19
  20 def brtarget26_mm : Operand<OtherVT> {
  21   let EncoderMethod = "getBranchTarget26OpValueMM";
  22   let OperandType = "OPERAND_PCREL";
  23   let DecoderMethod = "DecodeBranchTarget26MM";
  24   let ParserMatchClass = MipsJumpTargetAsmOperand;
  25 }
  26
  27 def brtargetr6 : Operand<OtherVT> {
  28   let EncoderMethod = "getBranchTargetOpValueMMR6";
  29   let OperandType = "OPERAND_PCREL";
  30   let DecoderMethod = "DecodeBranchTargetMM";
  31   let ParserMatchClass = MipsJumpTargetAsmOperand;
  32 }
  33
  34 def brtarget_lsl2_mm : Operand<OtherVT> {
  35   let EncoderMethod = "getBranchTargetOpValueLsl2MMR6";
  36   let OperandType = "OPERAND_PCREL";
  37   // Instructions that use this operand have their decoder method
  38   // set with DecodeDisambiguates
  39   let DecoderMethod = "";
  40   let ParserMatchClass = MipsJumpTargetAsmOperand;
  41 }
  42
  43 //===----------------------------------------------------------------------===//
  44 //
  45 // Instruction Encodings
  46 //
  47 //===----------------------------------------------------------------------===//
  48 class ADD_MMR6_ENC : ARITH_FM_MMR6<"add", 0x110>;
  49 class ADDIU_MMR6_ENC : ADDI_FM_MMR6<"addiu", 0xc>;
  50 class ADDU_MMR6_ENC : ARITH_FM_MMR6<"addu", 0x150>;
  51 class ADDIUPC_MMR6_ENC : PCREL19_FM_MMR6<0b00>;
  52 class ALUIPC_MMR6_ENC : PCREL16_FM_MMR6<0b11111>;
  53 class AND_MMR6_ENC : ARITH_FM_MMR6<"and", 0x250>;
  54 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
  55 class AUIPC_MMR6_ENC  : PCREL16_FM_MMR6<0b11110>;
  56 class ALIGN_MMR6_ENC : POOL32A_ALIGN_FM_MMR6<0b011111>;
  57 class AUI_MMR6_ENC : AUI_FM_MMR6;
  58 class BALC_MMR6_ENC  : BRANCH_OFF26_FM<0b101101>;
  59 class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
  60 class BC16_MMR6_ENC : BC16_FM_MM16R6;
  61 class BEQZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x23>;
  62 class BNEZC16_MMR6_ENC : BEQZC_BNEZC_FM_MM16R6<0x2b>;
  63 class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
  64 class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">;
  65 class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
  66 class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>;
  67 class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>,
  68                       DecodeDisambiguates<"POP75GroupBranchMMR6">;
  69 class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>,
  70                        DecodeDisambiguates<"BlezGroupBranchMMR6">;
  71 class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>,
  72                       DecodeDisambiguates<"POP65GroupBranchMMR6">;
  73 class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>,
  74                        DecodeDisambiguates<"BgtzGroupBranchMMR6">;
  75 class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>;
  76 class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>;
  77 class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>,
  78                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  79 class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>,
  80                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  81 class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>,
  82                        DecodeDisambiguates<"POP75GroupBranchMMR6">;
  83 class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>,
  84                        DecodeDisambiguates<"POP65GroupBranchMMR6">;
  85 class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>,
  86                          DecodeDisambiguates<"POP35GroupBranchMMR6">;
  87 class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>,
  88                          DecodeDisambiguates<"POP37GroupBranchMMR6">;
  89 class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>,
  90                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  91 class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>,
  92                          MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">;
  93 class BGEZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezalc", 0b110000>,
  94                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  95 class BLEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezalc", 0b110000>,
  96                          MMDecodeDisambiguatedBy<"BlezGroupBranchMMR6">;
  97 class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
  98 class CLO_MMR6_ENC : POOL32A_2R_FM_MMR6<0b0100101100>;
  99 class CLZ_MMR6_ENC : SPECIAL_2R_FM_MMR6<0b010000>;
 100 class DIV_MMR6_ENC : ARITH_FM_MMR6<"div", 0x118>;
 101 class DIVU_MMR6_ENC : ARITH_FM_MMR6<"divu", 0x198>;
 102 class EHB_MMR6_ENC : BARRIER_MMR6_ENC<"ehb", 0x3>;
 103 class EI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"ei", 0x15d>;
 104 class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
 105 class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
 106 class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
 107 class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
 108 class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
 109 class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
 110 class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
 111 class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
 112 class JIC_MMR6_ENC   : JMP_IDX_COMPACT_FM<0b101000>;
 113 class JRC16_MMR6_ENC: POOL16C_JALRC_FM_MM16R6<0x3>;
 114 class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>;
 115 class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>;
 116 class LWPC_MMR6_ENC  : PCREL19_FM_MMR6<0b01>;
 117 class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>;
 118 class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>;
 119 class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>;
 120 class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>;
 121 class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>;
 122 class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>;
 123 class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>;
 124 class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>;
 125 class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>;
 126 class MUH_MMR6_ENC : ARITH_FM_MMR6<"muh", 0x58>;
 127 class MULU_MMR6_ENC : ARITH_FM_MMR6<"mulu", 0x98>;
 128 class MUHU_MMR6_ENC : ARITH_FM_MMR6<"muhu", 0xd8>;
 129 class MTC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mtc0", 0b01011, 0b111100>;
 130 class MTC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mtc1", 0b10100000>;
 131 class MTC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mtc2", 0b0101110100>;
 132 class MTHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mthc0", 0b01011, 0b110100>;
 133 class MTHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mthc2", 0b1001110100>;
 134 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
 135 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
 136 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
 137 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
 138 class SB16_MMR6_ENC : LOAD_STORE_FM_MM16<0x22>;
 139 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
 140 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
 141 class SH16_MMR6_ENC : LOAD_STORE_FM_MM16<0x2a>;
 142 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
 143 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
 144 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
 145 class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0x3e>;
 146 class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
 147 class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
 148 class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
 149 class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>;
 150 class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>;
 151 class LB_MMR6_ENC : LB32_FM_MMR6;
 152 class LBU_MMR6_ENC : LBU32_FM_MMR6;
 153 class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
 154 class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
 155 class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
 156 class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
 157 class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
 158 class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
 159 class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
 160 class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
 161 class SIGRIE_MMR6_ENC : SIGRIE_FM_MM, MMR6Arch<"sigrie">;
 162 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 163 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 164 class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
 165 class ABS_D_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.d", 1, 0b0001101>;
 166 class FLOOR_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.s", 0, 0b00001100>;
 167 class FLOOR_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.l.d", 1, 0b00001100>;
 168 class FLOOR_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.s", 0, 0b00101100>;
 169 class FLOOR_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"floor.w.d", 1, 0b00101100>;
 170 class CEIL_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.s", 0, 0b01001100>;
 171 class CEIL_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.l.d", 1, 0b01001100>;
 172 class CEIL_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.s", 0, 0b01101100>;
 173 class CEIL_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"ceil.w.d", 1, 0b01101100>;
 174 class TRUNC_L_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.s", 0, 0b10001100>;
 175 class TRUNC_L_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.l.d", 1, 0b10001100>;
 176 class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 177 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 178 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 179 class SH_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b001110>;
 180 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 181 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 182 class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
 183 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 184 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 185 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
 186                                                        0b11001100>;
 187 class ROUND_L_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.d", 1,
 188                                                        0b11001100>;
 189 class ROUND_W_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.s", 0,
 190                                                        0b11101100>;
 191 class ROUND_W_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.w.d", 1,
 192                                                        0b11101100>;
 193 class SEL_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.s", 0, 0b010111000>;
 194 class SEL_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"sel.d", 1, 0b010111000>;
 195 class SELEQZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.s", 0, 0b000111000>;
 196 class SELEQZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"seleqz.d", 1, 0b000111000>;
 197 class SELNEZ_S_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.s", 0, 0b001111000>;
 198 class SELNEZ_D_MMR6_ENC : POOL32F_SEL_FM_MMR6<"selnez.d", 1, 0b001111000>;
 199 class CLASS_S_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.s", 0, 0b001100000>;
 200 class CLASS_D_MMR6_ENC : POOL32F_CLASS_FM_MMR6<"class.d", 1, 0b001100000>;
 201 class EXT_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ext", 0b101100>;
 202 class INS_MMR6_ENC : POOL32A_EXT_INS_FM_MMR6<"ins", 0b001100>;
 203 class JALRC_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc", 0b0000111100>;
 204 class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6<"bovc">;
 205 class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
 206 class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
 207 class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
 208 class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
 209 class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
 210 class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
 211 class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
 212 class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
 213 class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
 214 class LI16_MMR6_ENC : LI_FM_MM16;
 215 class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
 216 class MOVEP_MMR6_ENC  : POOL16C_MOVEP16_FM_MMR6;
 217 class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
 218 class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
 219 class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
 220 class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
 221 class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
 222 class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
 223 class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
 224 class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
 225 class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
 226 class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
 227 class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
 228 class LDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"ldc1", 0b101111>;
 229 class SDC1_MMR6_ENC : LDWC1_SDWC1_FM_MMR6<"sdc1", 0b101110>;
 230 class LDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"ldc2", 0b0010>;
 231 class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>;
 232 class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>;
 233 class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>;
 234
 235 class LL_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"ll", 0b0011, 0b000>;
 236 class SC_MMR6_ENC  : POOL32C_LL_E_SC_E_FM_MMR6<"sc", 0b1011, 0b000>;
 237
 238 /// Floating Point Instructions
 239 class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
 240 class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
 241 class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
 242 class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
 243 class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
 244 class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
 245 class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
 246 class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
 247 class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
 248 class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
 249 class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>;
 250 class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>;
 251 class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>;
 252 class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>;
 253 class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>;
 254 class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>;
 255 class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>;
 256 class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>;
 257
 258 class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>;
 259 class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>;
 260 class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>;
 261 class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>;
 262 class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>;
 263 class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>;
 264
 265 //===----------------------------------------------------------------------===//
 266 //
 267 // Instruction Descriptions
 268 //
 269 //===----------------------------------------------------------------------===//
 270
 271 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 272                                   RegisterOperand GPROpnd>
 273     : BRANCH_DESC_BASE {
 274   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 275   dag OutOperandList = (outs);
 276   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
 277   list<Register> Defs = [AT];
 278   InstrItinClass Itinerary = II_BCCZC;
 279 }
 280
 281 class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
 282                                                       GPR32Opnd> {
 283   list<Register> Defs = [RA];
 284 }
 285
 286 class BGEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezalc", brtarget_mm,
 287                                                       GPR32Opnd> {
 288   list<Register> Defs = [RA];
 289 }
 290
 291 class BGTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzalc", brtarget_mm,
 292                                                       GPR32Opnd> {
 293   list<Register> Defs = [RA];
 294 }
 295
 296 class BLEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezalc", brtarget_mm,
 297                                                       GPR32Opnd> {
 298   list<Register> Defs = [RA];
 299 }
 300
 301 class BLTZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzalc", brtarget_mm,
 302                                                       GPR32Opnd> {
 303   list<Register> Defs = [RA];
 304 }
 305
 306 class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
 307                                                       GPR32Opnd> {
 308   list<Register> Defs = [RA];
 309 }
 310
 311 class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm,
 312                                                     GPR32Opnd>;
 313 class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm,
 314                                                     GPR32Opnd>;
 315 class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm,
 316                                                     GPR32Opnd>;
 317 class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm,
 318                                                     GPR32Opnd>;
 319
 320 class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
 321                                 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
 322   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
 323   dag OutOperandList = (outs);
 324   string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
 325   list<Register> Defs = [AT];
 326   InstrItinClass Itinerary = II_BCCC;
 327 }
 328
 329 class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
 330                                                  GPR32Opnd>;
 331 class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm,
 332                                                  GPR32Opnd>;
 333 class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm,
 334                                                  GPR32Opnd>;
 335 class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm,
 336                                                  GPR32Opnd>;
 337 class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
 338                                                  GPR32Opnd>;
 339 class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
 340                                                  GPR32Opnd>;
 341
 342 class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
 343 class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
 344 class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
 345 class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
 346 class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
 347 class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
 348 class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
 349
 350 class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
 351     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
 352   dag InOperandList = (ins opnd:$offset);
 353   dag OutOperandList = (outs);
 354   string AsmString = !strconcat(instr_asm, "\t$offset");
 355   bit isBarrier = 1;
 356   InstrItinClass Itinerary = Itin;
 357 }
 358
 359 class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
 360   bit isCall = 1;
 361   list<Register> Defs = [RA];
 362 }
 363 class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
 364   list<dag> Pattern = [(br bb:$offset)];
 365 }
 366
 367 class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
 368                                        !strconcat("bc16", "\t$offset"), [],
 369                                        II_BC, FrmI>,
 370                        MMR6Arch<"bc16"> {
 371   let isBranch = 1;
 372   let isTerminator = 1;
 373   let isBarrier = 1;
 374   let hasDelaySlot = 0;
 375   let AdditionalPredicates = [RelocPIC];
 376   let Defs = [AT];
 377 }
 378
 379 class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
 380     : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>,
 381       MMR6Arch<instr_asm> {
 382   let isBranch = 1;
 383   let isTerminator = 1;
 384   let hasDelaySlot = 0;
 385   let Defs = [AT];
 386 }
 387 class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
 388 class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
 389
 390 class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
 391 class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
 392
 393 class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
 394     : MMR6Arch<instr_asm> {
 395   dag OutOperandList = (outs GPROpnd:$rd);
 396   dag InOperandList = (ins GPROpnd:$rt);
 397   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 398   list<dag> Pattern = [];
 399   InstrItinClass Itinerary = II_BITSWAP;
 400 }
 401
 402 class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
 403
 404 class BRK_MMR6_DESC : BRK_FT<"break">;
 405
 406 class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
 407                            RegisterOperand GPROpnd, InstrItinClass Itin>
 408       : MMR6Arch<instr_asm> {
 409   dag OutOperandList = (outs);
 410   dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
 411   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
 412   list<dag> Pattern = [];
 413   string DecoderMethod = "DecodeCacheOpMM";
 414   InstrItinClass Itinerary = Itin;
 415 }
 416
 417 class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd,
 418                                              II_CACHE>;
 419 class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd,
 420                                              II_PREF>;
 421
 422 class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
 423                             RegisterOperand GPROpnd, InstrItinClass Itin>
 424     : MMR6Arch<instr_asm> {
 425   dag OutOperandList = (outs GPROpnd:$rt);
 426   dag InOperandList = (ins MemOpnd:$addr);
 427   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
 428   string DecoderMethod = "DecodeLoadByte15";
 429   bit mayLoad = 1;
 430   InstrItinClass Itinerary = Itin;
 431 }
 432 class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
 433 class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
 434                                             II_LBU>;
 435
 436 class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 437                              InstrItinClass Itin> : MMR6Arch<instr_asm> {
 438   dag OutOperandList = (outs GPROpnd:$rt);
 439   dag InOperandList = (ins GPROpnd:$rs);
 440   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 441   InstrItinClass Itinerary = Itin;
 442 }
 443
 444 class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
 445 class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
 446
 447 class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
 448 class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
 449 class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
 450
 451 class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
 452 class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
 453 class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
 454
 455 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 456     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 457                       [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
 458       MMR6Arch<opstr> {
 459   let isCall = 1;
 460   let hasDelaySlot = 0;
 461   let Defs = [RA];
 462   let hasPostISelHook = 1;
 463 }
 464 class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
 465
 466 class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
 467                                      RegisterOperand GPROpnd,
 468                                      InstrItinClass Itin>
 469     : MMR6Arch<opstr> {
 470   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
 471   string AsmString = !strconcat(opstr, "\t$rt, $offset");
 472   list<dag> Pattern = [];
 473   bit isTerminator = 1;
 474   bit hasDelaySlot = 0;
 475   InstrItinClass Itinerary = Itin;
 476 }
 477
 478 class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
 479                                                        GPR32Opnd, II_JIALC> {
 480   bit isCall = 1;
 481   list<Register> Defs = [RA];
 482 }
 483
 484 class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
 485                                                      GPR32Opnd, II_JIC> {
 486   bit isBarrier = 1;
 487   list<Register> Defs = [AT];
 488 }
 489
 490 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
 491     : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
 492                       [], II_JR, FrmR>,
 493       MMR6Arch<opstr> {
 494   let hasDelaySlot = 0;
 495   let isBranch = 1;
 496   let isIndirectBranch = 1;
 497 }
 498 class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
 499
 500 class JRCADDIUSP_MMR6_DESC
 501     : MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
 502                       [], II_JRADDIUSP, FrmR>,
 503       MMR6Arch<"jrcaddiusp"> {
 504   let hasDelaySlot = 0;
 505   let isTerminator = 1;
 506   let isBarrier = 1;
 507   let isBranch = 1;
 508   let isIndirectBranch = 1;
 509 }
 510
 511 class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 512                       Operand ImmOpnd, InstrItinClass Itin>
 513     : MMR6Arch<instr_asm> {
 514   dag OutOperandList = (outs GPROpnd:$rd);
 515   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
 516   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
 517   list<dag> Pattern = [];
 518   InstrItinClass Itinerary = Itin;
 519 }
 520
 521 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
 522                                              II_ALIGN>;
 523
 524 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 525                          InstrItinClass Itin> : MMR6Arch<instr_asm> {
 526   dag OutOperandList = (outs GPROpnd:$rt);
 527   dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
 528   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
 529   list<dag> Pattern = [];
 530   InstrItinClass Itinerary = Itin;
 531 }
 532
 533 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
 534
 535 class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 536                             InstrItinClass Itin> : MMR6Arch<instr_asm> {
 537   dag OutOperandList = (outs GPROpnd:$rt);
 538   dag InOperandList = (ins simm16:$imm);
 539   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 540   list<dag> Pattern = [];
 541   InstrItinClass Itinerary = Itin;
 542 }
 543
 544 class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
 545 class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
 546
 547 class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 548                          Operand ImmOpnd, InstrItinClass Itin>
 549     : MMR6Arch<instr_asm> {
 550   dag OutOperandList = (outs GPROpnd:$rd);
 551   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
 552   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
 553   list<dag> Pattern = [];
 554   InstrItinClass Itinerary = Itin;
 555 }
 556
 557 class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
 558
 559 class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 560                            Operand ImmOpnd, InstrItinClass Itin>
 561     : MMR6Arch<instr_asm> {
 562   dag OutOperandList = (outs GPROpnd:$rt);
 563   dag InOperandList = (ins ImmOpnd:$imm);
 564   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
 565   list<dag> Pattern = [];
 566   InstrItinClass Itinerary = Itin;
 567 }
 568
 569 class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
 570                                                simm19_lsl2, II_ADDIUPC>;
 571 class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
 572                                            II_LWPC>;
 573
 574 class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
 575                                InstrItinClass Itin> : MMR6Arch<instr_asm> {
 576   dag OutOperandList = (outs GPROpnd:$rd);
 577   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 578   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 579   list<dag> Pattern = [];
 580   InstrItinClass Itinerary = Itin;
 581 }
 582
 583 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
 584                                                   II_SELCCZ>;
 585 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
 586                                                   II_SELCCZ>;
 587 class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
 588 class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
 589   dag OutOperandList = (outs GPR32Opnd:$rt);
 590   dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
 591   string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
 592   list<dag> Pattern = [];
 593   InstrItinClass Itinerary = II_RDHWR;
 594   Format Form = FrmR;
 595 }
 596
 597 class WAIT_MMR6_DESC : WaitMM<"wait">;
 598 // FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
 599 //        Assemblers targeting specifically Release 6 should reject the SSNOP
 600 //        instruction with an error.
 601 class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
 602 class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
 603
 604 class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
 605                             InstrItinClass Itin,
 606                             SDPatternOperator OpNode=null_frag>
 607     : MipsR6Inst {
 608   dag OutOperandList = (outs GPROpnd:$rd);
 609   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
 610   string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
 611   list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
 612   string BaseOpcode = opstr;
 613   Format f = FrmR;
 614   let isCommutable = 0;
 615   let isReMaterializable = 1;
 616   InstrItinClass Itinerary = Itin;
 617
 618   // This instruction doesn't trap division by zero itself. We must insert
 619   // teq instructions as well.
 620   bit usesCustomInserter = 1;
 621 }
 622 class DIV_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
 623 class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
 624 class MOD_MMR6_DESC  : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
 625 class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
 626 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
 627 class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
 628 class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
 629 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
 630 class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
 631                                   or> {
 632   int AddedComplexity = 1;
 633 }
 634 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
 635 class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
 636                                    immZExt16, xor>;
 637 class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
 638   InstrItinClass Itinerary = II_SW;
 639 }
 640 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
 641                                  InstrItinClass Itin> {
 642   dag InOperandList = (ins RO:$rs);
 643   dag OutOperandList = (outs RO:$rt);
 644   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 645   list<dag> Pattern = [];
 646   Format f = FrmR;
 647   string BaseOpcode = instr_asm;
 648   bit hasSideEffects = 0;
 649   InstrItinClass Itinerary = Itin;
 650 }
 651 class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
 652                                                     II_WRPGPR>;
 653 class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
 654
 655 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 656                          RegisterOperand SrcRC, InstrItinClass Itin> {
 657   dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
 658   dag OutOperandList = (outs DstRC:$rs);
 659   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 660   list<dag> Pattern = [];
 661   Format f = FrmFR;
 662   string BaseOpcode = opstr;
 663   InstrItinClass Itinerary = Itin;
 664 }
 665 class MTC1_MMR6_DESC_BASE<
 666       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 667       InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
 668       : MipsR6Inst {
 669   dag InOperandList = (ins SrcRC:$rt);
 670   dag OutOperandList = (outs DstRC:$fs);
 671   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 672   list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
 673   Format f = FrmFR;
 674   InstrItinClass Itinerary = Itin;
 675   string BaseOpcode = opstr;
 676 }
 677 class MTC1_64_MMR6_DESC_BASE<
 678       string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
 679       InstrItinClass Itin = NoItinerary> : MipsR6Inst {
 680   dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
 681   dag OutOperandList = (outs DstRC:$fs);
 682   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 683   list<dag> Pattern = [];
 684   Format f = FrmFR;
 685   InstrItinClass Itinerary = Itin;
 686   string BaseOpcode = opstr;
 687   // $fs_in is part of a white lie to work around a widespread bug in the FPU
 688   // implementation. See expandBuildPairF64 for details.
 689   let Constraints = "$fs = $fs_in";
 690 }
 691 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 692                          RegisterOperand SrcRC, InstrItinClass Itin> {
 693   dag InOperandList = (ins SrcRC:$rt);
 694   dag OutOperandList = (outs DstRC:$impl);
 695   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 696   list<dag> Pattern = [];
 697   Format f = FrmFR;
 698   string BaseOpcode = opstr;
 699   InstrItinClass Itinerary = Itin;
 700 }
 701
 702 class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
 703                                            II_MTC0>;
 704 class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
 705                                            II_MTC1, bitconvert>, HARDFLOAT;
 706 class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
 707                                            II_MTC2>;
 708 class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
 709                                             II_MTHC0>;
 710 class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
 711                                             II_MTC2>;
 712
 713 class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 714                           RegisterOperand SrcRC, InstrItinClass Itin> {
 715   dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
 716   dag OutOperandList = (outs DstRC:$rt);
 717   string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
 718   list<dag> Pattern = [];
 719   Format f = FrmFR;
 720   string BaseOpcode = opstr;
 721   InstrItinClass Itinerary = Itin;
 722 }
 723 class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 724                           RegisterOperand SrcRC,
 725                           InstrItinClass Itin = NoItinerary,
 726                           SDPatternOperator OpNode = null_frag> : MipsR6Inst {
 727   dag InOperandList = (ins SrcRC:$fs);
 728   dag OutOperandList = (outs DstRC:$rt);
 729   string AsmString = !strconcat(opstr, "\t$rt, $fs");
 730   list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
 731   Format f = FrmFR;
 732   InstrItinClass Itinerary = Itin;
 733   string BaseOpcode = opstr;
 734 }
 735 class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
 736                           RegisterOperand SrcRC, InstrItinClass Itin> {
 737   dag InOperandList = (ins SrcRC:$impl);
 738   dag OutOperandList = (outs DstRC:$rt);
 739   string AsmString = !strconcat(opstr, "\t$rt, $impl");
 740   list<dag> Pattern = [];
 741   Format f = FrmFR;
 742   string BaseOpcode = opstr;
 743   InstrItinClass Itinerary = Itin;
 744 }
 745 class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
 746                                            II_MFC0>;
 747 class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
 748                                            II_MFC1, bitconvert>, HARDFLOAT;
 749 class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
 750                                            II_MFC2>;
 751 class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
 752                                             II_MFHC0>;
 753 class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
 754                                             II_MFC2>;
 755
 756 class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 757   dag InOperandList = (ins mem_mm_16:$addr);
 758   dag OutOperandList = (outs FGR64Opnd:$ft);
 759   string AsmString = !strconcat("ldc1", "\t$ft, $addr");
 760   list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
 761   Format f = FrmFI;
 762   InstrItinClass Itinerary = II_LDC1;
 763   string BaseOpcode = "ldc1";
 764   bit mayLoad = 1;
 765   let DecoderMethod = "DecodeFMemMMR2";
 766 }
 767
 768 class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
 769   dag InOperandList = (ins FGR64Opnd:$ft, mem_mm_16:$addr);
 770   dag OutOperandList = (outs);
 771   string AsmString = !strconcat("sdc1", "\t$ft, $addr");
 772   list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
 773   Format f = FrmFI;
 774   InstrItinClass Itinerary = II_SDC1;
 775   string BaseOpcode = "sdc1";
 776   bit mayStore = 1;
 777   let DecoderMethod = "DecodeFMemMMR2";
 778 }
 779
 780 class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 781   dag OutOperandList = (outs COP2Opnd:$rt);
 782   dag InOperandList = (ins mem_mm_11:$addr);
 783   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 784   list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
 785   Format f = FrmFI;
 786   InstrItinClass Itinerary = itin;
 787   string BaseOpcode = opstr;
 788   bit mayLoad = 1;
 789   string DecoderMethod = "DecodeFMemCop2MMR6";
 790 }
 791 class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
 792 class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
 793
 794 class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 795   dag OutOperandList = (outs);
 796   dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
 797   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 798   list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
 799   Format f = FrmFI;
 800   InstrItinClass Itinerary = itin;
 801   string BaseOpcode = opstr;
 802   bit mayStore = 1;
 803   string DecoderMethod = "DecodeFMemCop2MMR6";
 804 }
 805 class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
 806 class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
 807
 808 class GINV_MMR6_DESC_BASE<string opstr,
 809                           RegisterOperand SrcRC, InstrItinClass Itin> {
 810   dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
 811   dag OutOperandList = (outs);
 812   string AsmString = !strconcat(opstr, "\t$rs, $type");
 813   list<dag> Pattern = [];
 814   Format f = FrmFR;
 815   string BaseOpcode = opstr;
 816   InstrItinClass Itinerary = Itin;
 817 }
 818
 819 class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
 820                                             II_GINVI> {
 821   dag InOperandList = (ins GPR32Opnd:$rs);
 822   string AsmString = "ginvi\t$rs";
 823 }
 824 class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
 825                                             II_GINVT>;
 826
 827 class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 828   dag OutOperandList = (outs GPR32Opnd:$dst);
 829   dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
 830   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 831   InstrItinClass Itinerary = itin;
 832   string BaseOpcode = opstr;
 833   bit mayStore = 1;
 834   string Constraints = "$rt = $dst";
 835   string DecoderMethod = "DecodeMemMMImm9";
 836 }
 837
 838 class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
 839   dag OutOperandList = (outs GPR32Opnd:$rt);
 840   dag InOperandList = (ins mem_mm_9:$addr);
 841   string AsmString = !strconcat(opstr, "\t$rt, $addr");
 842   InstrItinClass Itinerary = itin;
 843   string BaseOpcode = opstr;
 844   bit mayLoad = 1;
 845   string DecoderMethod = "DecodeMemMMImm9";
 846 }
 847
 848 class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
 849 class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
 850
 851 /// Floating Point Instructions
 852 class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
 853                             InstrItinClass Itin, bit isComm,
 854                             SDPatternOperator OpNode = null_frag> : HARDFLOAT {
 855   dag OutOperandList = (outs RC:$fd);
 856   dag InOperandList = (ins RC:$ft, RC:$fs);
 857   string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
 858   list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
 859   InstrItinClass Itinerary = Itin;
 860   bit isCommutable = isComm;
 861 }
 862 class FADD_S_MMR6_DESC
 863   : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
 864 class FSUB_S_MMR6_DESC
 865   : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
 866 class FMUL_S_MMR6_DESC
 867   : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
 868 class FDIV_S_MMR6_DESC
 869   : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
 870 class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
 871                                             II_MADDF_S>, HARDFLOAT;
 872 class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
 873                                             II_MADDF_D>, HARDFLOAT;
 874 class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
 875                                             II_MSUBF_S>, HARDFLOAT;
 876 class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
 877                                             II_MSUBF_D>, HARDFLOAT;
 878
 879 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
 880                                RegisterOperand SrcRC, InstrItinClass Itin,
 881                                SDPatternOperator OpNode = null_frag>
 882                                : HARDFLOAT, NeverHasSideEffects {
 883   dag OutOperandList = (outs DstRC:$ft);
 884   dag InOperandList = (ins SrcRC:$fs);
 885   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 886   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 887   InstrItinClass Itinerary = Itin;
 888   Format Form = FrmFR;
 889 }
 890 class FMOV_S_MMR6_DESC
 891   : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
 892 class FNEG_S_MMR6_DESC
 893   : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
 894
 895 class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
 896                         HARDFLOAT;
 897 class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
 898                         HARDFLOAT;
 899 class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
 900                         HARDFLOAT;
 901 class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
 902                         HARDFLOAT;
 903
 904 class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
 905                          HARDFLOAT;
 906 class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
 907                          HARDFLOAT;
 908 class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
 909                          HARDFLOAT;
 910 class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
 911                          HARDFLOAT;
 912
 913 class CVT_MMR6_DESC_BASE<
 914     string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
 915     InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
 916     : HARDFLOAT, NeverHasSideEffects {
 917   dag OutOperandList = (outs DstRC:$ft);
 918   dag InOperandList = (ins SrcRC:$fs);
 919   string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
 920   list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
 921   InstrItinClass Itinerary = Itin;
 922   Format Form = FrmFR;
 923 }
 924
 925 class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
 926                                              II_CVT>;
 927 class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
 928                                              II_CVT>;
 929 class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
 930                                              II_CVT>;
 931 class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
 932                                              II_CVT>, FGR_64;
 933 class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
 934                                              II_CVT>;
 935 class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
 936                                              II_CVT>, FGR_64;
 937
 938 multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
 939                        RegisterOperand FGROpnd, InstrItinClass Itin> {
 940   def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 941       !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
 942       CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT,
 943       ISA_MICROMIPS32R6;
 944   def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 945       !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
 946       CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT,
 947       ISA_MICROMIPS32R6;
 948   def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 949       !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
 950       CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT,
 951       ISA_MICROMIPS32R6;
 952   def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 953       !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
 954       CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT,
 955       ISA_MICROMIPS32R6;
 956   def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 957       !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
 958       CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT,
 959       ISA_MICROMIPS32R6;
 960   def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 961       !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
 962       CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT,
 963       ISA_MICROMIPS32R6;
 964   def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 965       !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
 966       CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT,
 967       ISA_MICROMIPS32R6;
 968   def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 969       !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
 970       CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT,
 971       ISA_MICROMIPS32R6;
 972   def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 973       !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
 974       CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT,
 975       ISA_MICROMIPS32R6;
 976   def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 977       !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
 978       CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT,
 979       ISA_MICROMIPS32R6;
 980   def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 981       !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
 982       CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT,
 983       ISA_MICROMIPS32R6;
 984   def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 985       !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
 986       CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT,
 987       ISA_MICROMIPS32R6;
 988   def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 989       !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
 990       CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT,
 991       ISA_MICROMIPS32R6;
 992   def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 993       !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
 994       CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT,
 995       ISA_MICROMIPS32R6;
 996   def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
 997       !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
 998       CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT,
 999       ISA_MICROMIPS32R6;
1000   def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
1001       !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
1002       CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT,
1003       ISA_MICROMIPS32R6;
1004 }
1005
1006 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
1007                              RegisterOperand SrcRC, InstrItinClass Itin,
1008                              SDPatternOperator OpNode = null_frag>
1009     : HARDFLOAT, NeverHasSideEffects {
1010   dag OutOperandList = (outs DstRC:$ft);
1011   dag InOperandList  = (ins SrcRC:$fs);
1012   string AsmString   = !strconcat(instr_asm, "\t$ft, $fs");
1013   list<dag>  Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
1014   InstrItinClass Itinerary = Itin;
1015   Format Form = FrmFR;
1016   list<Predicate> EncodingPredicates = [HasStdEnc];
1017 }
1018
1019 class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
1020                                                     FGR32Opnd, II_FLOOR>;
1021 class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
1022                                                     FGR64Opnd, II_FLOOR>;
1023 class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
1024                                                     FGR32Opnd, II_FLOOR>;
1025 class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
1026                                                     AFGR64Opnd, II_FLOOR>;
1027 class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
1028                                                    FGR32Opnd, II_CEIL>;
1029 class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
1030                                                    FGR64Opnd, II_CEIL>;
1031 class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
1032                                                    FGR32Opnd, II_CEIL>;
1033 class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
1034                                                    AFGR64Opnd, II_CEIL>;
1035 class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
1036                                                     FGR32Opnd, II_TRUNC>;
1037 class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
1038                                                     FGR64Opnd, II_TRUNC>;
1039 class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
1040                                                     FGR32Opnd, II_TRUNC>;
1041 class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
1042                                                     AFGR64Opnd, II_TRUNC>;
1043 class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
1044                                                  II_SQRT_S, fsqrt>;
1045 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
1046                                                  II_SQRT_D, fsqrt>;
1047 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
1048                                                    FGR32Opnd, II_ROUND>;
1049 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
1050                                                    FGR64Opnd, II_ROUND>;
1051 class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
1052                                                    FGR32Opnd, II_ROUND>;
1053 class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
1054                                                    FGR64Opnd, II_ROUND>;
1055
1056 class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>;
1057 class SEL_D_MMR6_DESC : COP1_SEL_D_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>;
1058
1059 class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
1060                                               II_SELCCZ_S>;
1061 class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
1062                                               II_SELCCZ_D>;
1063 class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
1064                                               II_SELCCZ_S>;
1065 class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
1066                                               II_SELCCZ_D>;
1067 class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
1068                                               II_RINT_S>;
1069 class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
1070                                               II_RINT_S>;
1071 class CLASS_S_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
1072                                               II_CLASS_S>;
1073 class CLASS_D_MMR6_DESC  : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
1074                                               II_CLASS_S>;
1075
1076 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1077                            InstrItinClass Itin>
1078     : Store<opstr, RO>, MMR6Arch<opstr> {
1079   let DecoderMethod = "DecodeMemMMImm16";
1080   InstrItinClass Itinerary = Itin;
1081 }
1082 class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
1083
1084 class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
1085 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
1086       MMR6Arch<"addu16"> {
1087   int AddedComplexity = 1;
1088 }
1089 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
1090       MMR6Arch<"and16">;
1091 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
1092       MMR6Arch<"andi16">;
1093 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
1094   int AddedComplexity = 1;
1095 }
1096 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
1097 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
1098       MMR6Arch<"sll16">;
1099 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
1100       MMR6Arch<"srl16">;
1101 class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">;
1102 class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
1103       MMR6Arch<"li16">, IsAsCheapAsAMove;
1104 class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
1105 class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
1106                                   GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
1107                         MMR6Arch<"movep">;
1108 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">;
1109 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
1110       MMR6Arch<"subu16"> {
1111   int AddedComplexity = 1;
1112 }
1113 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
1114       MMR6Arch<"xor16">;
1115
1116 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
1117   dag OutOperandList = (outs GPR32Opnd:$rt);
1118   dag InOperandList = (ins mem:$addr);
1119   string AsmString = "lw\t$rt, $addr";
1120   let DecoderMethod = "DecodeMemMMImm16";
1121   let canFoldAsLoad = 1;
1122   let mayLoad = 1;
1123   list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
1124   InstrItinClass Itinerary = II_LW;
1125 }
1126
1127 class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
1128   dag OutOperandList = (outs GPR32Opnd:$rt);
1129   dag InOperandList = (ins uimm16:$imm16);
1130   string AsmString = "lui\t$rt, $imm16";
1131   list<dag> Pattern = [];
1132   bit hasSideEffects = 0;
1133   bit isReMaterializable = 1;
1134   InstrItinClass Itinerary = II_LUI;
1135   Format Form = FrmI;
1136 }
1137
1138 class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
1139   dag OutOperandList = (outs);
1140   dag InOperandList = (ins uimm5:$stype);
1141   string AsmString = !strconcat("sync", "\t$stype");
1142   list<dag> Pattern = [(MipsSync immZExt5:$stype)];
1143   InstrItinClass Itinerary = II_SYNC;
1144   bit HasSideEffects = 1;
1145 }
1146
1147 class SYNCI_MMR6_DESC : SYNCI_FT<"synci", mem_mm_16> {
1148   let DecoderMethod = "DecodeSynciR6";
1149 }
1150
1151 class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
1152   dag OutOperandList = (outs GPR32Opnd:$rt);
1153   dag InOperandList = (ins GPR32Opnd:$rd);
1154   string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
1155   InstrItinClass Itinerary = II_RDPGPR;
1156 }
1157
1158 class SDBBP_MMR6_DESC : MipsR6Inst {
1159   dag OutOperandList = (outs);
1160   dag InOperandList = (ins uimm20:$code_);
1161   string AsmString = !strconcat("sdbbp", "\t$code_");
1162   list<dag> Pattern = [];
1163   InstrItinClass Itinerary = II_SDBBP;
1164 }
1165
1166 class SIGRIE_MMR6_DESC : MipsR6Inst {
1167   dag OutOperandList = (outs);
1168   dag InOperandList = (ins uimm16:$code_);
1169   string AsmString = !strconcat("sigrie", "\t$code_");
1170   list<dag> Pattern = [];
1171   InstrItinClass Itinerary = II_SIGRIE;
1172 }
1173
1174 class LWM16_MMR6_DESC
1175     : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
1176                       !strconcat("lwm16", "\t$rt, $addr"), [],
1177                       II_LWM, FrmI>,
1178       MMR6Arch<"lwm16"> {
1179   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1180   let mayLoad = 1;
1181   ComplexPattern Addr = addr;
1182 }
1183
1184 class SWM16_MMR6_DESC
1185     : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
1186                       !strconcat("swm16", "\t$rt, $addr"), [],
1187                       II_SWM, FrmI>,
1188       MMR6Arch<"swm16"> {
1189   let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
1190   let mayStore = 1;
1191   ComplexPattern Addr = addr;
1192 }
1193
1194 class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd, DAGOperand RO,
1195                           SDPatternOperator OpNode, InstrItinClass Itin,
1196                           Operand MemOpnd>
1197     : MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
1198                       !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
1199       MMR6Arch<opstr> {
1200   let DecoderMethod = "DecodeMemMMImm4";
1201   let mayStore = 1;
1202 }
1203 class SB16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, GPRMM16Opnd,
1204                                            truncstorei8, II_SB, mem_mm_4>;
1205 class SH16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, GPRMM16Opnd,
1206                                            truncstorei16, II_SH, mem_mm_4_lsl1>;
1207 class SW16_MMR6_DESC : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, GPRMM16Opnd,
1208                                            store, II_SW, mem_mm_4_lsl2>;
1209
1210 class SWSP_MMR6_DESC
1211     : MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
1212                       !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
1213       MMR6Arch<"sw"> {
1214   let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
1215   let mayStore = 1;
1216 }
1217
1218 class JALRC_HB_MMR6_DESC {
1219   dag OutOperandList = (outs GPR32Opnd:$rt);
1220   dag InOperandList = (ins GPR32Opnd:$rs);
1221   string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
1222   list<dag> Pattern = [];
1223   InstrItinClass Itinerary = II_JALR_HB;
1224   Format Form = FrmJ;
1225   bit isIndirectBranch = 1;
1226   bit hasDelaySlot = 0;
1227 }
1228
1229 class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1230   dag OutOperandList = (outs);
1231   dag InOperandList = (ins);
1232   string AsmString = opstr;
1233   list<dag> Pattern = [];
1234   InstrItinClass Itinerary = Itin;
1235 }
1236
1237 class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
1238 class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
1239
1240 class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
1241   dag OutOperandList = (outs GPR32Opnd:$rs);
1242   dag InOperandList = (ins);
1243   string AsmString = !strconcat(opstr, "\t$rs");
1244   list<dag> Pattern = [];
1245   InstrItinClass Itinerary = Itin;
1246   bit hasUnModeledSideEffects = 1;
1247 }
1248
1249 class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
1250 class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
1251
1252 class BEQZC_MMR6_DESC
1253     : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1254       MMR6Arch<"beqzc">;
1255 class BNEZC_MMR6_DESC
1256     : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
1257       MMR6Arch<"bnezc">;
1258
1259 class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
1260     InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
1261            !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
1262     HARDFLOAT, BRANCH_DESC_BASE {
1263   list<Register> Defs = [AT];
1264 }
1265
1266 class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
1267 class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
1268
1269 class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
1270     : BRANCH_DESC_BASE {
1271   dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
1272   dag OutOperandList = (outs);
1273   string AsmString = !strconcat(opstr, "\t$rt, $offset");
1274   list<Register> Defs = [AT];
1275   InstrItinClass Itinerary = Itin;
1276 }
1277
1278 class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
1279 class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
1280
1281 class EXT_MMR6_DESC {
1282   dag OutOperandList = (outs GPR32Opnd:$rt);
1283   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_plus1:$size);
1284   string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
1285   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
1286                        imm:$size))];
1287   InstrItinClass Itinerary = II_EXT;
1288   Format Form = FrmR;
1289   string BaseOpcode = "ext";
1290 }
1291
1292 class INS_MMR6_DESC {
1293   dag OutOperandList = (outs GPR32Opnd:$rt);
1294   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$pos, uimm5_inssize_plus1:$size,
1295                        GPR32Opnd:$src);
1296   string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
1297   list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
1298                        imm:$size, GPR32Opnd:$src))];
1299   InstrItinClass Itinerary = II_INS;
1300   Format Form = FrmR;
1301   string BaseOpcode = "ins";
1302   string Constraints = "$src = $rt";
1303 }
1304
1305 class JALRC_MMR6_DESC {
1306   dag OutOperandList = (outs GPR32Opnd:$rt);
1307   dag InOperandList = (ins GPR32Opnd:$rs);
1308   string AsmString = !strconcat("jalrc", "\t$rt, $rs");
1309   list<dag> Pattern = [];
1310   InstrItinClass Itinerary = II_JALRC;
1311   bit isCall = 1;
1312   bit hasDelaySlot = 0;
1313   list<Register> Defs = [RA];
1314 }
1315
1316 class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
1317                                RegisterOperand GPROpnd>
1318     : BRANCH_DESC_BASE {
1319   dag InOperandList = (ins GPROpnd:$rt, GPROpnd:$rs, opnd:$offset);
1320   dag OutOperandList = (outs);
1321   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
1322   list<Register> Defs = [AT];
1323   InstrItinClass Itinerary = II_BCCC;
1324 }
1325
1326 class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
1327 class BNVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bnvc", brtargetr6, GPR32Opnd>;
1328
1329 //===----------------------------------------------------------------------===//
1330 //
1331 // Instruction Definitions
1332 //
1333 //===----------------------------------------------------------------------===//
1334
1335 let DecoderNamespace = "MicroMipsR6" in {
1336 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
1337 def ADDIU_MMR6 : StdMMR6Rel, ADDIU_MMR6_DESC, ADDIU_MMR6_ENC, ISA_MICROMIPS32R6;
1338 def ADDU_MMR6 : StdMMR6Rel, ADDU_MMR6_DESC, ADDU_MMR6_ENC, ISA_MICROMIPS32R6;
1339 def ADDIUPC_MMR6 : R6MMR6Rel, ADDIUPC_MMR6_ENC, ADDIUPC_MMR6_DESC,
1340                    ISA_MICROMIPS32R6;
1341 def ALUIPC_MMR6 : R6MMR6Rel, ALUIPC_MMR6_ENC, ALUIPC_MMR6_DESC,
1342                   ISA_MICROMIPS32R6;
1343 def AND_MMR6 : StdMMR6Rel, AND_MMR6_DESC, AND_MMR6_ENC, ISA_MICROMIPS32R6;
1344 def ANDI_MMR6 : StdMMR6Rel, ANDI_MMR6_DESC, ANDI_MMR6_ENC, ISA_MICROMIPS32R6;
1345 def AUIPC_MMR6 : R6MMR6Rel, AUIPC_MMR6_ENC, AUIPC_MMR6_DESC, ISA_MICROMIPS32R6;
1346 def ALIGN_MMR6 : R6MMR6Rel, ALIGN_MMR6_ENC, ALIGN_MMR6_DESC, ISA_MICROMIPS32R6;
1347 def AUI_MMR6 : R6MMR6Rel, AUI_MMR6_ENC, AUI_MMR6_DESC, ISA_MICROMIPS32R6;
1348 def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
1349 def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
1350 def BC16_MMR6 : StdMMR6Rel, BC16_MMR6_DESC, BC16_MMR6_ENC, ISA_MICROMIPS32R6;
1351 def BEQZC_MMR6 : R6MMR6Rel, BEQZC_MMR6_ENC, BEQZC_MMR6_DESC,
1352                  ISA_MICROMIPS32R6;
1353 def BEQZC16_MMR6 : StdMMR6Rel, BEQZC16_MMR6_DESC, BEQZC16_MMR6_ENC,
1354                    ISA_MICROMIPS32R6;
1355 def BNEZC_MMR6 : R6MMR6Rel, BNEZC_MMR6_ENC, BNEZC_MMR6_DESC,
1356                  ISA_MICROMIPS32R6;
1357 def BNEZC16_MMR6 : StdMMR6Rel, BNEZC16_MMR6_DESC, BNEZC16_MMR6_ENC,
1358                    ISA_MICROMIPS32R6;
1359 def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
1360                    ISA_MICROMIPS32R6;
1361 def BEQZALC_MMR6 : R6MMR6Rel, BEQZALC_MMR6_ENC, BEQZALC_MMR6_DESC,
1362                    ISA_MICROMIPS32R6;
1363 def BNEZALC_MMR6 : R6MMR6Rel, BNEZALC_MMR6_ENC, BNEZALC_MMR6_DESC,
1364                    ISA_MICROMIPS32R6;
1365 def BREAK_MMR6 : StdMMR6Rel, BRK_MMR6_DESC, BRK_MMR6_ENC, ISA_MICROMIPS32R6;
1366 def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
1367 def CLO_MMR6 : R6MMR6Rel, CLO_MMR6_ENC, CLO_MMR6_DESC, ISA_MICROMIPS32R6;
1368 def CLZ_MMR6 : R6MMR6Rel, CLZ_MMR6_ENC, CLZ_MMR6_DESC, ISA_MICROMIPS32R6;
1369 def DIV_MMR6 : R6MMR6Rel, DIV_MMR6_DESC, DIV_MMR6_ENC, ISA_MICROMIPS32R6;
1370 def DIVU_MMR6 : R6MMR6Rel, DIVU_MMR6_DESC, DIVU_MMR6_ENC, ISA_MICROMIPS32R6;
1371 def EHB_MMR6 : StdMMR6Rel, EHB_MMR6_DESC, EHB_MMR6_ENC, ISA_MICROMIPS32R6;
1372 def EI_MMR6 : StdMMR6Rel, EI_MMR6_DESC, EI_MMR6_ENC, ISA_MICROMIPS32R6;
1373 def DI_MMR6 : StdMMR6Rel, DI_MMR6_DESC, DI_MMR6_ENC, ISA_MICROMIPS32R6;
1374 def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
1375 def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
1376 def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
1377                   ISA_MICROMIPS32R6;
1378 def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
1379                  ISA_MICROMIPS32R6, ASE_GINV;
1380 def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
1381                  ISA_MICROMIPS32R6, ASE_GINV;
1382 let FastISelShouldIgnore = 1 in
1383 def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
1384                    ISA_MICROMIPS32R6;
1385 def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
1386 def JIC_MMR6 : R6MMR6Rel, JIC_MMR6_ENC, JIC_MMR6_DESC, ISA_MICROMIPS32R6;
1387 def JRC16_MMR6 : R6MMR6Rel, JRC16_MMR6_DESC, JRC16_MMR6_ENC, ISA_MICROMIPS32R6;
1388 def JRCADDIUSP_MMR6 : R6MMR6Rel, JRCADDIUSP_MMR6_DESC, JRCADDIUSP_MMR6_ENC,
1389                       ISA_MICROMIPS32R6;
1390 def LSA_MMR6 : R6MMR6Rel, LSA_MMR6_ENC, LSA_MMR6_DESC, ISA_MICROMIPS32R6;
1391 def LWPC_MMR6 : R6MMR6Rel, LWPC_MMR6_ENC, LWPC_MMR6_DESC, ISA_MICROMIPS32R6;
1392 def LWM16_MMR6 : StdMMR6Rel, LWM16_MMR6_DESC, LWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1393 def MTC0_MMR6 : StdMMR6Rel, MTC0_MMR6_ENC, MTC0_MMR6_DESC, ISA_MICROMIPS32R6;
1394 def MTC1_MMR6 : StdMMR6Rel, MTC1_MMR6_DESC, MTC1_MMR6_ENC, ISA_MICROMIPS32R6;
1395 def MTC2_MMR6 : StdMMR6Rel, MTC2_MMR6_ENC, MTC2_MMR6_DESC, ISA_MICROMIPS32R6;
1396 def MTHC0_MMR6 : R6MMR6Rel, MTHC0_MMR6_ENC, MTHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1397 def MTHC2_MMR6 : StdMMR6Rel, MTHC2_MMR6_ENC, MTHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1398 def MFC0_MMR6 : StdMMR6Rel, MFC0_MMR6_ENC, MFC0_MMR6_DESC, ISA_MICROMIPS32R6;
1399 def MFC1_MMR6 : StdMMR6Rel, MFC1_MMR6_DESC, MFC1_MMR6_ENC, ISA_MICROMIPS32R6;
1400 def MFC2_MMR6 : StdMMR6Rel, MFC2_MMR6_ENC, MFC2_MMR6_DESC, ISA_MICROMIPS32R6;
1401 def MFHC0_MMR6 : R6MMR6Rel, MFHC0_MMR6_ENC, MFHC0_MMR6_DESC, ISA_MICROMIPS32R6;
1402 def MFHC2_MMR6 : StdMMR6Rel, MFHC2_MMR6_ENC, MFHC2_MMR6_DESC, ISA_MICROMIPS32R6;
1403 def MOD_MMR6 : R6MMR6Rel, MOD_MMR6_DESC, MOD_MMR6_ENC, ISA_MICROMIPS32R6;
1404 def MODU_MMR6 : R6MMR6Rel, MODU_MMR6_DESC, MODU_MMR6_ENC, ISA_MICROMIPS32R6;
1405 def MUL_MMR6 : R6MMR6Rel, MUL_MMR6_DESC, MUL_MMR6_ENC, ISA_MICROMIPS32R6;
1406 def MUH_MMR6 : R6MMR6Rel, MUH_MMR6_DESC, MUH_MMR6_ENC, ISA_MICROMIPS32R6;
1407 def MULU_MMR6 : R6MMR6Rel, MULU_MMR6_DESC, MULU_MMR6_ENC, ISA_MICROMIPS32R6;
1408 def MUHU_MMR6 : R6MMR6Rel, MUHU_MMR6_DESC, MUHU_MMR6_ENC, ISA_MICROMIPS32R6;
1409 def NOR_MMR6 : StdMMR6Rel, NOR_MMR6_DESC, NOR_MMR6_ENC, ISA_MICROMIPS32R6;
1410 def OR_MMR6 : StdMMR6Rel, OR_MMR6_DESC, OR_MMR6_ENC, ISA_MICROMIPS32R6;
1411 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
1412 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
1413 def SB16_MMR6 : StdMMR6Rel, SB16_MMR6_DESC, SB16_MMR6_ENC, ISA_MICROMIPS32R6;
1414 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
1415                   ISA_MICROMIPS32R6;
1416 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
1417                   ISA_MICROMIPS32R6;
1418 def SH16_MMR6 : StdMMR6Rel, SH16_MMR6_DESC, SH16_MMR6_ENC, ISA_MICROMIPS32R6;
1419 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
1420 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
1421 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
1422 def SW16_MMR6 : StdMMR6Rel, SW16_MMR6_DESC, SW16_MMR6_ENC, ISA_MICROMIPS32R6;
1423 def SWM16_MMR6 : StdMMR6Rel, SWM16_MMR6_DESC, SWM16_MMR6_ENC, ISA_MICROMIPS32R6;
1424 def SWSP_MMR6 : StdMMR6Rel, SWSP_MMR6_DESC, SWSP_MMR6_ENC, ISA_MICROMIPS32R6;
1425 def WRPGPR_MMR6 : StdMMR6Rel, WRPGPR_MMR6_ENC, WRPGPR_MMR6_DESC,
1426                   ISA_MICROMIPS32R6;
1427 def WSBH_MMR6 : StdMMR6Rel, WSBH_MMR6_ENC, WSBH_MMR6_DESC, ISA_MICROMIPS32R6;
1428 def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
1429 def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
1430 def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
1431 def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
1432 def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
1433 def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
1434 def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
1435 def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
1436 def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
1437                   ISA_MICROMIPS32R6;
1438 def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
1439 def SIGRIE_MMR6 : R6MMR6Rel, SIGRIE_MMR6_DESC, SIGRIE_MMR6_ENC, ISA_MICROMIPS32R6;
1440 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
1441 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
1442 let DecoderMethod = "DecodeMemMMImm16" in {
1443   def SW_MMR6 : StdMMR6Rel, SW_MMR6_DESC, SW_MMR6_ENC, ISA_MICROMIPS32R6;
1444 }
1445 /// Floating Point Instructions
1446 def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
1447                   ISA_MICROMIPS32R6;
1448 def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
1449                   ISA_MICROMIPS32R6;
1450 def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
1451                   ISA_MICROMIPS32R6;
1452 def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
1453                   ISA_MICROMIPS32R6;
1454 def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
1455                    ISA_MICROMIPS32R6;
1456 def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
1457                    ISA_MICROMIPS32R6;
1458 def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
1459                    ISA_MICROMIPS32R6;
1460 def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
1461                    ISA_MICROMIPS32R6;
1462 def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
1463                   ISA_MICROMIPS32R6;
1464 def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
1465                   ISA_MICROMIPS32R6;
1466 def MAX_S_MMR6 : R6MMR6Rel, MAX_S_MMR6_ENC, MAX_S_MMR6_DESC, ISA_MICROMIPS32R6;
1467 def MAX_D_MMR6 : R6MMR6Rel, MAX_D_MMR6_ENC, MAX_D_MMR6_DESC, ISA_MICROMIPS32R6;
1468 def MIN_S_MMR6 : R6MMR6Rel, MIN_S_MMR6_ENC, MIN_S_MMR6_DESC, ISA_MICROMIPS32R6;
1469 def MIN_D_MMR6 : R6MMR6Rel, MIN_D_MMR6_ENC, MIN_D_MMR6_DESC, ISA_MICROMIPS32R6;
1470 def MAXA_S_MMR6 : R6MMR6Rel, MAXA_S_MMR6_ENC, MAXA_S_MMR6_DESC,
1471                   ISA_MICROMIPS32R6;
1472 def MAXA_D_MMR6 : R6MMR6Rel, MAXA_D_MMR6_ENC, MAXA_D_MMR6_DESC,
1473                   ISA_MICROMIPS32R6;
1474 def MINA_S_MMR6 : R6MMR6Rel, MINA_S_MMR6_ENC, MINA_S_MMR6_DESC,
1475                   ISA_MICROMIPS32R6;
1476 def MINA_D_MMR6 : R6MMR6Rel, MINA_D_MMR6_ENC, MINA_D_MMR6_DESC,
1477                   ISA_MICROMIPS32R6;
1478 def CVT_L_S_MMR6 : StdMMR6Rel, CVT_L_S_MMR6_ENC, CVT_L_S_MMR6_DESC,
1479                    ISA_MICROMIPS32R6;
1480 def CVT_L_D_MMR6 : StdMMR6Rel, CVT_L_D_MMR6_ENC, CVT_L_D_MMR6_DESC,
1481                    ISA_MICROMIPS32R6;
1482 def CVT_W_S_MMR6 : StdMMR6Rel, CVT_W_S_MMR6_ENC, CVT_W_S_MMR6_DESC,
1483                    ISA_MICROMIPS32R6;
1484 def CVT_D_L_MMR6 : StdMMR6Rel, CVT_D_L_MMR6_ENC, CVT_D_L_MMR6_DESC,
1485                    ISA_MICROMIPS32R6;
1486 def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC,
1487                    ISA_MICROMIPS32R6;
1488 def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC,
1489                    ISA_MICROMIPS32R6;
1490 defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>;
1491 defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>;
1492 def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
1493                      ISA_MICROMIPS32R6;
1494 def FLOOR_L_D_MMR6 : StdMMR6Rel, FLOOR_L_D_MMR6_ENC, FLOOR_L_D_MMR6_DESC,
1495                      ISA_MICROMIPS32R6;
1496 def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC,
1497                      ISA_MICROMIPS32R6;
1498 def FLOOR_W_D_MMR6 : StdMMR6Rel, FLOOR_W_D_MMR6_ENC, FLOOR_W_D_MMR6_DESC,
1499                      ISA_MICROMIPS32R6;
1500 def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC,
1501                     ISA_MICROMIPS32R6;
1502 def CEIL_L_D_MMR6 : StdMMR6Rel, CEIL_L_D_MMR6_ENC, CEIL_L_D_MMR6_DESC,
1503                     ISA_MICROMIPS32R6;
1504 def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC,
1505                     ISA_MICROMIPS32R6;
1506 def CEIL_W_D_MMR6 : StdMMR6Rel, CEIL_W_D_MMR6_ENC, CEIL_W_D_MMR6_DESC,
1507                     ISA_MICROMIPS32R6;
1508 def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC,
1509                      ISA_MICROMIPS32R6;
1510 def TRUNC_L_D_MMR6 : StdMMR6Rel, TRUNC_L_D_MMR6_ENC, TRUNC_L_D_MMR6_DESC,
1511                      ISA_MICROMIPS32R6;
1512 def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC,
1513                      ISA_MICROMIPS32R6;
1514 def TRUNC_W_D_MMR6 : StdMMR6Rel, TRUNC_W_D_MMR6_ENC, TRUNC_W_D_MMR6_DESC,
1515                      ISA_MICROMIPS32R6;
1516 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
1517 def SH_MMR6 : StdMMR6Rel, SH_MMR6_DESC, SH_MMR6_ENC, ISA_MICROMIPS32R6;
1518 def LW_MMR6 : StdMMR6Rel, LW_MMR6_DESC, LW_MMR6_ENC, ISA_MICROMIPS32R6;
1519 def LUI_MMR6 : R6MMR6Rel, LUI_MMR6_DESC, LUI_MMR6_ENC, ISA_MICROMIPS32R6;
1520 def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
1521                   ISA_MICROMIPS32R6;
1522 def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
1523                   ISA_MICROMIPS32R6;
1524 def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
1525                   ISA_MICROMIPS32R6;
1526 def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
1527                   ISA_MICROMIPS32R6;
1528 def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
1529                   ISA_MICROMIPS32R6;
1530 def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
1531                   ISA_MICROMIPS32R6;
1532 def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
1533                   ISA_MICROMIPS32R6;
1534 def BREAK16_MMR6 : StdMMR6Rel, BREAK16_MMR6_DESC, BREAK16_MMR6_ENC,
1535                    ISA_MICROMIPS32R6;
1536 def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
1537                 ISA_MICROMIPS32R6;
1538 def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
1539                   ISA_MICROMIPS32R6;
1540 def MOVEP_MMR6  : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1541                   ISA_MICROMIPS32R6;
1542 def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
1543                    ISA_MICROMIPS32R6;
1544 def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,
1545                   ISA_MICROMIPS32R6;
1546 def XOR16_MMR6 : StdMMR6Rel, XOR16_MMR6_DESC, XOR16_MMR6_ENC,
1547                  ISA_MICROMIPS32R6;
1548 def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
1549                     ISA_MICROMIPS32R6;
1550 def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
1551 def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
1552 def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
1553 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
1554                   ISA_MICROMIPS32R6;
1555 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
1556 def ROUND_L_S_MMR6 : StdMMR6Rel, ROUND_L_S_MMR6_ENC, ROUND_L_S_MMR6_DESC,
1557                      ISA_MICROMIPS32R6;
1558 def ROUND_L_D_MMR6 : StdMMR6Rel, ROUND_L_D_MMR6_ENC, ROUND_L_D_MMR6_DESC,
1559                      ISA_MICROMIPS32R6;
1560 def ROUND_W_S_MMR6 : StdMMR6Rel, ROUND_W_S_MMR6_ENC, ROUND_W_S_MMR6_DESC,
1561                      ISA_MICROMIPS32R6;
1562 def ROUND_W_D_MMR6 : StdMMR6Rel, ROUND_W_D_MMR6_ENC, ROUND_W_D_MMR6_DESC,
1563                      ISA_MICROMIPS32R6;
1564 def SEL_S_MMR6 : R6MMR6Rel, SEL_S_MMR6_ENC, SEL_S_MMR6_DESC, ISA_MICROMIPS32R6;
1565 def SEL_D_MMR6 : R6MMR6Rel, SEL_D_MMR6_ENC, SEL_D_MMR6_DESC, ISA_MICROMIPS32R6;
1566 def SELEQZ_S_MMR6 : R6MMR6Rel, SELEQZ_S_MMR6_ENC, SELEQZ_S_MMR6_DESC,
1567                     ISA_MICROMIPS32R6;
1568 def SELEQZ_D_MMR6 : R6MMR6Rel, SELEQZ_D_MMR6_ENC, SELEQZ_D_MMR6_DESC,
1569                     ISA_MICROMIPS32R6;
1570 def SELNEZ_S_MMR6 : R6MMR6Rel, SELNEZ_S_MMR6_ENC, SELNEZ_S_MMR6_DESC,
1571                     ISA_MICROMIPS32R6;
1572 def SELNEZ_D_MMR6 : R6MMR6Rel, SELNEZ_D_MMR6_ENC, SELNEZ_D_MMR6_DESC,
1573                     ISA_MICROMIPS32R6;
1574 def CLASS_S_MMR6 : StdMMR6Rel, CLASS_S_MMR6_ENC, CLASS_S_MMR6_DESC,
1575                    ISA_MICROMIPS32R6;
1576 def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
1577                    ISA_MICROMIPS32R6;
1578 def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
1579                   ISA_MICROMIPS32R6;
1580 def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
1581                    ISA_MICROMIPS32R6;
1582 def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
1583 def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
1584 def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
1585                    ISA_MICROMIPS32R6;
1586 def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
1587                    ISA_MICROMIPS32R6;
1588 def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
1589                    ISA_MICROMIPS32R6;
1590 def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
1591                    ISA_MICROMIPS32R6;
1592 let DecoderNamespace = "MicroMipsFP64" in {
1593   def LDC1_D64_MMR6 : StdMMR6Rel, LDC1_D64_MMR6_DESC, LDC1_MMR6_ENC,
1594                       ISA_MICROMIPS32R6 {
1595     let BaseOpcode = "LDC164";
1596   }
1597   def SDC1_D64_MMR6 : StdMMR6Rel, SDC1_D64_MMR6_DESC, SDC1_MMR6_ENC,
1598                       ISA_MICROMIPS32R6;
1599 }
1600 def LDC2_MMR6 : StdMMR6Rel, LDC2_MMR6_ENC, LDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1601 def SDC2_MMR6 : StdMMR6Rel, SDC2_MMR6_ENC, SDC2_MMR6_DESC, ISA_MICROMIPS32R6;
1602 def LWC2_MMR6 : StdMMR6Rel, LWC2_MMR6_ENC, LWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1603 def SWC2_MMR6 : StdMMR6Rel, SWC2_MMR6_ENC, SWC2_MMR6_DESC, ISA_MICROMIPS32R6;
1604 def LL_MMR6   : R6MMR6Rel, LL_MMR6_ENC, LL_MMR6_DESC, ISA_MICROMIPS32R6;
1605 def SC_MMR6   : R6MMR6Rel, SC_MMR6_ENC, SC_MMR6_DESC, ISA_MICROMIPS32R6;
1606 }
1607
1608 def BOVC_MMR6 : R6MMR6Rel, BOVC_MMR6_ENC, BOVC_MMR6_DESC, ISA_MICROMIPS32R6,
1609                 MMDecodeDisambiguatedBy<"POP35GroupBranchMMR6">;
1610 def BNVC_MMR6 : R6MMR6Rel, BNVC_MMR6_ENC, BNVC_MMR6_DESC, ISA_MICROMIPS32R6,
1611                 MMDecodeDisambiguatedBy<"POP37GroupBranchMMR6">;
1612 def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
1613 def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
1614 def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
1615 def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
1616 def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6,
1617                 DecodeDisambiguates<"POP35GroupBranchMMR6">;
1618 def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6,
1619                 DecodeDisambiguates<"POP37GroupBranchMMR6">;
1620 def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1621 def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1622 def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6;
1623 def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6;
1624 def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC,
1625                    ISA_MICROMIPS32R6;
1626 def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC,
1627                    ISA_MICROMIPS32R6;
1628 def BLEZALC_MMR6 : R6MMR6Rel, BLEZALC_MMR6_ENC, BLEZALC_MMR6_DESC,
1629                    ISA_MICROMIPS32R6;
1630 def BLTZALC_MMR6 : R6MMR6Rel, BLTZALC_MMR6_ENC, BLTZALC_MMR6_DESC,
1631                    ISA_MICROMIPS32R6;
1632
1633 //===----------------------------------------------------------------------===//
1634 //
1635 // MicroMips instruction aliases
1636 //
1637 //===----------------------------------------------------------------------===//
1638
1639 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1640 def : MipsInstAlias<"di", (DI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
1641 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;
1642 def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1643                                       !strconcat("b", "\t$offset")> {
1644   string DecoderNamespace = "MicroMipsR6";
1645 }
1646 def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
1647 def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
1648 def : MipsInstAlias<"sigrie", (SIGRIE_MMR6 0), 1>, ISA_MICROMIPS32R6;
1649 def : MipsInstAlias<"rdhwr $rt, $rs",
1650                     (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1651                     ISA_MICROMIPS32R6;
1652 def : MipsInstAlias<"mtc0 $rt, $rs",
1653                     (MTC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1654                     ISA_MICROMIPS32R6;
1655 def : MipsInstAlias<"mthc0 $rt, $rs",
1656                     (MTHC0_MMR6 COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1657                     ISA_MICROMIPS32R6;
1658 def : MipsInstAlias<"mfc0 $rt, $rs",
1659                     (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1660                     ISA_MICROMIPS32R6;
1661 def : MipsInstAlias<"mfhc0 $rt, $rs",
1662                     (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1663                     ISA_MICROMIPS32R6;
1664 def : MipsInstAlias<"jalrc.hb $rs", (JALRC_HB_MMR6 RA, GPR32Opnd:$rs), 1>,
1665                     ISA_MICROMIPS32R6;
1666 def : MipsInstAlias<"jal $offset", (BALC_MMR6 brtarget26_mm:$offset), 0>,
1667                     ISA_MICROMIPS32R6;
1668 def : MipsInstAlias<"dvp", (DVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1669 def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
1670 def : MipsInstAlias<"jalrc $rs", (JALRC_MMR6 RA, GPR32Opnd:$rs), 1>,
1671       ISA_MICROMIPS32R6;
1672 def : MipsInstAlias<"and $rs, $rt, $imm",
1673                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1674                     ISA_MICROMIPS32R6;
1675 def : MipsInstAlias<"and $rs, $imm",
1676                     (ANDI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1677                     ISA_MICROMIPS32R6;
1678 def : MipsInstAlias<"or $rs, $rt, $imm",
1679                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1680                     ISA_MICROMIPS32R6;
1681 def : MipsInstAlias<"or $rs, $imm",
1682                     (ORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1683                     ISA_MICROMIPS32R6;
1684 def : MipsInstAlias<"xor $rs, $rt, $imm",
1685                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>,
1686                     ISA_MICROMIPS32R6;
1687 def : MipsInstAlias<"xor $rs, $imm",
1688                     (XORI_MMR6 GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>,
1689                     ISA_MICROMIPS32R6;
1690 def : MipsInstAlias<"not $rt, $rs",
1691                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1692                     ISA_MICROMIPS32R6;
1693 def : MipsInstAlias<"not $rt",
1694                     (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1695                     ISA_MICROMIPS32R6;
1696 def : MipsInstAlias<"lapc $rd, $imm",
1697                     (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)>,
1698                     ISA_MICROMIPS32R6;
1699 def : MipsInstAlias<"neg $rt, $rs",
1700                     (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1701       ISA_MICROMIPS32R6;
1702 def : MipsInstAlias<"neg $rt",
1703                     (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1704       ISA_MICROMIPS32R6;
1705 def : MipsInstAlias<"negu $rt, $rs",
1706                     (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1707       ISA_MICROMIPS32R6;
1708 def : MipsInstAlias<"negu $rt",
1709                     (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1710       ISA_MICROMIPS32R6;
1711 def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
1712                                                          brtarget7_mm:$offset),
1713                     0>, ISA_MICROMIPS32R6;
1714 def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
1715                                                          brtarget7_mm:$offset),
1716                     0>, ISA_MICROMIPS32R6;
1717 def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
1718                     ISA_MICROMIPS32R6;
1719
1720 //===----------------------------------------------------------------------===//
1721 //
1722 // MicroMips arbitrary patterns that map to one or more instructions
1723 //
1724 //===----------------------------------------------------------------------===//
1725
1726 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1727               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
1728 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1729               (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;
1730
1731 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
1732               (OR_MM (SELNEZ_MMR6 i32:$t, i32:$cond),
1733                      (SELEQZ_MMR6 i32:$f, i32:$cond))>,
1734               ISA_MICROMIPS32R6;
1735 def : MipsPat<(select i32:$cond, i32:$t, immz),
1736               (SELNEZ_MMR6 i32:$t, i32:$cond)>,
1737               ISA_MICROMIPS32R6;
1738 def : MipsPat<(select i32:$cond, immz, i32:$f),
1739               (SELEQZ_MMR6 i32:$f, i32:$cond)>,
1740               ISA_MICROMIPS32R6;
1741
1742 defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
1743                       SELNEZ_MMR6, immZExt16, i32>, ISA_MICROMIPS32R6;
1744
1745 defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1746 defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6;
1747
1748 def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
1749 def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6;
1750 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
1751               (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6;
1752
1753 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1754               (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>,
1755               ISA_MICROMIPS32R6;
1756 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1757               (ANDI_MMR6 GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1758 def : MipsPat<(i32 immZExt16:$imm),
1759               (XORI_MMR6 ZERO, immZExt16:$imm)>, ISA_MICROMIPS32R6;
1760 def : MipsPat<(not GPRMM16:$in),
1761               (NOT16_MMR6 GPRMM16:$in)>, ISA_MICROMIPS32R6;
1762 def : MipsPat<(not GPR32:$in),
1763               (NOR_MMR6 GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS32R6;
1764 // Patterns for load with a reg+imm operand.
1765 let AddedComplexity = 41 in {
1766   def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6;
1767   def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6;
1768 }
1769
1770 def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
1771
1772 def TAILCALLREG_MMR6  : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
1773
1774 def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
1775                                                          GPR32Opnd>,
1776                                 ISA_MICROMIPS32R6;
1777
1778 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1779               (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
1780
1781 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1782               (TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
1783
1784
1785 def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
1786               (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1787 def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst),
1788               (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
1789
1790 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1791               (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1792       ISA_MICROMIPS32R6;
1793 def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1794               (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
1795       ISA_MICROMIPS32R6;
1796 def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1797               (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1798       ISA_MICROMIPS32R6;
1799 def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
1800               (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
1801       ISA_MICROMIPS32R6;
1802 def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1803               (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1804       ISA_MICROMIPS32R6;
1805 def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1806               (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
1807       ISA_MICROMIPS32R6;
1808
1809 def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1810               (BEQZC_MMR6  (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1811       ISA_MICROMIPS32R6;
1812 def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst),
1813               (BEQZC_MMR6  (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
1814       ISA_MICROMIPS32R6;
1815
1816 def : MipsPat<(brcond GPR32:$cond, bb:$dst),
1817               (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;