lib/Target/Mips/Mips.td

   1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 // This is the top level entry point for the Mips target.
   9 //===----------------------------------------------------------------------===//
  10
  11 //===----------------------------------------------------------------------===//
  12 // Target-independent interfaces
  13 //===----------------------------------------------------------------------===//
  14
  15 include "llvm/Target/Target.td"
  16
  17 // The overall idea of the PredicateControl class is to chop the Predicates list
  18 // into subsets that are usually overridden independently. This allows
  19 // subclasses to partially override the predicates of their superclasses without
  20 // having to re-add all the existing predicates.
  21 class PredicateControl {
  22   // Predicates for the encoding scheme in use such as HasStdEnc
  23   list<Predicate> EncodingPredicates = [];
  24   // Predicates for the GPR size such as IsGP64bit
  25   list<Predicate> GPRPredicates = [];
  26   // Predicates for the PTR size such as IsPTR64bit
  27   list<Predicate> PTRPredicates = [];
  28   // Predicates for the FGR size and layout such as IsFP64bit
  29   list<Predicate> FGRPredicates = [];
  30   // Predicates for the instruction group membership such as ISA's.
  31   list<Predicate> InsnPredicates = [];
  32   // Predicate for the ASE that an instruction belongs to.
  33   list<Predicate> ASEPredicate = [];
  34   // Predicate for marking the instruction as usable in hard-float mode only.
  35   list<Predicate> HardFloatPredicate = [];
  36   // Predicates for anything else
  37   list<Predicate> AdditionalPredicates = [];
  38   list<Predicate> Predicates = !listconcat(EncodingPredicates,
  39                                            GPRPredicates,
  40                                            PTRPredicates,
  41                                            FGRPredicates,
  42                                            InsnPredicates,
  43                                            HardFloatPredicate,
  44                                            ASEPredicate,
  45                                            AdditionalPredicates);
  46 }
  47
  48 // Like Requires<> but for the AdditionalPredicates list
  49 class AdditionalRequires<list<Predicate> preds> {
  50   list<Predicate> AdditionalPredicates = preds;
  51 }
  52
  53 //===----------------------------------------------------------------------===//
  54 // Register File, Calling Conv, Instruction Descriptions
  55 //===----------------------------------------------------------------------===//
  56
  57 include "MipsRegisterInfo.td"
  58 include "MipsSchedule.td"
  59 include "MipsInstrInfo.td"
  60 include "MipsCallingConv.td"
  61 include "MipsRegisterBanks.td"
  62
  63 // Avoid forward declaration issues.
  64 include "MipsScheduleP5600.td"
  65 include "MipsScheduleGeneric.td"
  66
  67 def MipsInstrInfo : InstrInfo;
  68
  69 //===----------------------------------------------------------------------===//
  70 // Mips Subtarget features                                                    //
  71 //===----------------------------------------------------------------------===//
  72
  73 def FeatureNoABICalls  : SubtargetFeature<"noabicalls", "NoABICalls", "true",
  74                                 "Disable SVR4-style position-independent code">;
  75 def FeaturePTR64Bit    : SubtargetFeature<"ptr64", "IsPTR64bit", "true",
  76                                 "Pointers are 64-bit wide">;
  77 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
  78                                 "General Purpose Registers are 64-bit wide">;
  79 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
  80                                 "Support 64-bit FP registers">;
  81 def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
  82                                 "Support for FPXX">;
  83 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
  84                                 "IEEE 754-2008 NaN encoding">;
  85 def FeatureAbs2008     : SubtargetFeature<"abs2008", "Abs2008", "true",
  86                                           "Disable IEEE 754-2008 abs.fmt mode">;
  87 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
  88                                 "true", "Only supports single precision float">;
  89 def FeatureSoftFloat   : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
  90                                 "Does not support floating point instructions">;
  91 def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
  92                               "Disable odd numbered single-precision "
  93                               "registers">;
  94 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
  95                                 "true", "Enable vector FPU instructions">;
  96 def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
  97                                 "Mips I ISA Support [highly experimental]">;
  98 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
  99                                 "Mips II ISA Support [highly experimental]",
 100                                 [FeatureMips1]>;
 101 def FeatureMips3_32    : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
 102                                 "Subset of MIPS-III that is also in MIPS32 "
 103                                 "[highly experimental]">;
 104 def FeatureMips3_32r2  : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
 105                                 "Subset of MIPS-III that is also in MIPS32r2 "
 106                                 "[highly experimental]">;
 107 def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
 108                                 "MIPS III ISA Support [highly experimental]",
 109                                 [FeatureMips2, FeatureMips3_32,
 110                                  FeatureMips3_32r2, FeatureGP64Bit,
 111                                  FeatureFP64Bit]>;
 112 def FeatureMips4_32    : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
 113                                 "Subset of MIPS-IV that is also in MIPS32 "
 114                                 "[highly experimental]">;
 115 def FeatureMips4_32r2  : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
 116                                 "Subset of MIPS-IV that is also in MIPS32r2 "
 117                                 "[highly experimental]">;
 118 def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
 119                                 "Mips4", "MIPS IV ISA Support",
 120                                 [FeatureMips3, FeatureMips4_32,
 121                                  FeatureMips4_32r2]>;
 122 def FeatureMips5_32r2  : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
 123                                 "Subset of MIPS-V that is also in MIPS32r2 "
 124                                 "[highly experimental]">;
 125 def FeatureMips5       : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
 126                                 "MIPS V ISA Support [highly experimental]",
 127                                 [FeatureMips4, FeatureMips5_32r2]>;
 128 def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
 129                                 "Mips32 ISA Support",
 130                                 [FeatureMips2, FeatureMips3_32,
 131                                  FeatureMips4_32]>;
 132 def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
 133                                 "Mips32r2", "Mips32r2 ISA Support",
 134                                 [FeatureMips3_32r2, FeatureMips4_32r2,
 135                                  FeatureMips5_32r2, FeatureMips32]>;
 136 def FeatureMips32r3    : SubtargetFeature<"mips32r3", "MipsArchVersion",
 137                                 "Mips32r3", "Mips32r3 ISA Support",
 138                                 [FeatureMips32r2]>;
 139 def FeatureMips32r5    : SubtargetFeature<"mips32r5", "MipsArchVersion",
 140                                 "Mips32r5", "Mips32r5 ISA Support",
 141                                 [FeatureMips32r3]>;
 142 def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
 143                                 "Mips32r6",
 144                                 "Mips32r6 ISA Support [experimental]",
 145                                 [FeatureMips32r5, FeatureFP64Bit,
 146                                  FeatureNaN2008, FeatureAbs2008]>;
 147 def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
 148                                 "Mips64", "Mips64 ISA Support",
 149                                 [FeatureMips5, FeatureMips32]>;
 150 def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
 151                                 "Mips64r2", "Mips64r2 ISA Support",
 152                                 [FeatureMips64, FeatureMips32r2]>;
 153 def FeatureMips64r3    : SubtargetFeature<"mips64r3", "MipsArchVersion",
 154                                 "Mips64r3", "Mips64r3 ISA Support",
 155                                 [FeatureMips64r2, FeatureMips32r3]>;
 156 def FeatureMips64r5    : SubtargetFeature<"mips64r5", "MipsArchVersion",
 157                                 "Mips64r5", "Mips64r5 ISA Support",
 158                                 [FeatureMips64r3, FeatureMips32r5]>;
 159 def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
 160                                 "Mips64r6",
 161                                 "Mips64r6 ISA Support [experimental]",
 162                                 [FeatureMips32r6, FeatureMips64r5,
 163                                  FeatureNaN2008, FeatureAbs2008]>;
 164 def FeatureSym32       : SubtargetFeature<"sym32", "HasSym32", "true",
 165                                           "Symbols are 32 bit on Mips64">;
 166
 167 def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
 168                                       "Mips16 mode">;
 169
 170 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
 171 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
 172                                     "Mips DSP-R2 ASE", [FeatureDSP]>;
 173 def FeatureDSPR3
 174     : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
 175                        [ FeatureDSP, FeatureDSPR2 ]>;
 176
 177 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
 178
 179 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
 180
 181 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;
 182
 183 def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true",
 184                                    "Mips Virtualization ASE">;
 185
 186 def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
 187                                    "Mips Global Invalidate ASE">;
 188
 189 def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
 190                                          "microMips mode">;
 191
 192 def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
 193                                 "true", "Octeon cnMIPS Support",
 194                                 [FeatureMips64r2]>;
 195
 196 def FeatureUseTCCInDIV : SubtargetFeature<
 197                                "use-tcc-in-div",
 198                                "UseTCCInDIV", "false",
 199                                "Force the assembler to use trapping">;
 200
 201 def FeatureMadd4 : SubtargetFeature<"nomadd4", "DisableMadd4", "true",
 202                                     "Disable 4-operand madd.fmt and related instructions">;
 203
 204 def FeatureMT : SubtargetFeature<"mt", "HasMT", "true", "Mips MT ASE">;
 205
 206 def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
 207                                         "Disable use of the jal instruction">;
 208
 209 def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
 210                                                     "UseIndirectJumpsHazard",
 211                                                     "true", "Use indirect jump"
 212                         " guards to prevent certain speculation based attacks">;
 213 //===----------------------------------------------------------------------===//
 214 // Mips processors supported.
 215 //===----------------------------------------------------------------------===//
 216
 217 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 218                                  "MipsSubtarget::CPU::P5600",
 219                                  "The P5600 Processor", [FeatureMips32r5]>;
 220
 221 class Proc<string Name, list<SubtargetFeature> Features>
 222  : ProcessorModel<Name, MipsGenericModel, Features>;
 223
 224 def : Proc<"mips1", [FeatureMips1]>;
 225 def : Proc<"mips2", [FeatureMips2]>;
 226 def : Proc<"mips32", [FeatureMips32]>;
 227 def : Proc<"mips32r2", [FeatureMips32r2]>;
 228 def : Proc<"mips32r3", [FeatureMips32r3]>;
 229 def : Proc<"mips32r5", [FeatureMips32r5]>;
 230 def : Proc<"mips32r6", [FeatureMips32r6]>;
 231
 232 def : Proc<"mips3", [FeatureMips3]>;
 233 def : Proc<"mips4", [FeatureMips4]>;
 234 def : Proc<"mips5", [FeatureMips5]>;
 235 def : Proc<"mips64", [FeatureMips64]>;
 236 def : Proc<"mips64r2", [FeatureMips64r2]>;
 237 def : Proc<"mips64r3", [FeatureMips64r3]>;
 238 def : Proc<"mips64r5", [FeatureMips64r5]>;
 239 def : Proc<"mips64r6", [FeatureMips64r6]>;
 240 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
 241 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
 242
 243 def MipsAsmParser : AsmParser {
 244   let ShouldEmitMatchRegisterName = 0;
 245 }
 246
 247 def MipsAsmParserVariant : AsmParserVariant {
 248   int Variant = 0;
 249
 250   // Recognize hard coded registers.
 251   string RegisterPrefix = "$";
 252 }
 253
 254 def Mips : Target {
 255   let InstructionSet = MipsInstrInfo;
 256   let AssemblyParsers = [MipsAsmParser];
 257   let AssemblyParserVariants = [MipsAsmParserVariant];
 258   let AllowRegisterRenaming = 1;
 259 }