lib/Target/Mips/Mips16ISelLowering.cpp

   1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Subclass of MipsTargetLowering specialized for mips16.
  10 //
  11 //===----------------------------------------------------------------------===//
  12 #include "Mips16ISelLowering.h"
  13 #include "MCTargetDesc/MipsBaseInfo.h"
  14 #include "Mips16HardFloatInfo.h"
  15 #include "MipsMachineFunction.h"
  16 #include "MipsRegisterInfo.h"
  17 #include "MipsTargetMachine.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/TargetInstrInfo.h"
  20 #include "llvm/Support/CommandLine.h"
  21
  22 using namespace llvm;
  23
  24 #define DEBUG_TYPE "mips-lower"
  25
  26 static cl::opt<bool> DontExpandCondPseudos16(
  27   "mips16-dont-expand-cond-pseudo",
  28   cl::init(false),
  29   cl::desc("Don't expand conditional move related "
  30            "pseudos for Mips 16"),
  31   cl::Hidden);
  32
  33 namespace {
  34 struct Mips16Libcall {
  35   RTLIB::Libcall Libcall;
  36   const char *Name;
  37
  38   bool operator<(const Mips16Libcall &RHS) const {
  39     return std::strcmp(Name, RHS.Name) < 0;
  40   }
  41 };
  42
  43 struct Mips16IntrinsicHelperType{
  44   const char* Name;
  45   const char* Helper;
  46
  47   bool operator<(const Mips16IntrinsicHelperType &RHS) const {
  48     return std::strcmp(Name, RHS.Name) < 0;
  49   }
  50   bool operator==(const Mips16IntrinsicHelperType &RHS) const {
  51     return std::strcmp(Name, RHS.Name) == 0;
  52   }
  53 };
  54 }
  55
  56 // Libcalls for which no helper is generated. Sorted by name for binary search.
  57 static const Mips16Libcall HardFloatLibCalls[] = {
  58   { RTLIB::ADD_F64, "__mips16_adddf3" },
  59   { RTLIB::ADD_F32, "__mips16_addsf3" },
  60   { RTLIB::DIV_F64, "__mips16_divdf3" },
  61   { RTLIB::DIV_F32, "__mips16_divsf3" },
  62   { RTLIB::OEQ_F64, "__mips16_eqdf2" },
  63   { RTLIB::OEQ_F32, "__mips16_eqsf2" },
  64   { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
  65   { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
  66   { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
  67   { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
  68   { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
  69   { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
  70   { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
  71   { RTLIB::OGE_F64, "__mips16_gedf2" },
  72   { RTLIB::OGE_F32, "__mips16_gesf2" },
  73   { RTLIB::OGT_F64, "__mips16_gtdf2" },
  74   { RTLIB::OGT_F32, "__mips16_gtsf2" },
  75   { RTLIB::OLE_F64, "__mips16_ledf2" },
  76   { RTLIB::OLE_F32, "__mips16_lesf2" },
  77   { RTLIB::OLT_F64, "__mips16_ltdf2" },
  78   { RTLIB::OLT_F32, "__mips16_ltsf2" },
  79   { RTLIB::MUL_F64, "__mips16_muldf3" },
  80   { RTLIB::MUL_F32, "__mips16_mulsf3" },
  81   { RTLIB::UNE_F64, "__mips16_nedf2" },
  82   { RTLIB::UNE_F32, "__mips16_nesf2" },
  83   { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
  84   { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
  85   { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
  86   { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
  87   { RTLIB::SUB_F64, "__mips16_subdf3" },
  88   { RTLIB::SUB_F32, "__mips16_subsf3" },
  89   { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
  90   { RTLIB::UO_F64, "__mips16_unorddf2" },
  91   { RTLIB::UO_F32, "__mips16_unordsf2" }
  92 };
  93
  94 static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
  95   {"__fixunsdfsi", "__mips16_call_stub_2" },
  96   {"ceil",  "__mips16_call_stub_df_2"},
  97   {"ceilf", "__mips16_call_stub_sf_1"},
  98   {"copysign",  "__mips16_call_stub_df_10"},
  99   {"copysignf", "__mips16_call_stub_sf_5"},
 100   {"cos",  "__mips16_call_stub_df_2"},
 101   {"cosf", "__mips16_call_stub_sf_1"},
 102   {"exp2",  "__mips16_call_stub_df_2"},
 103   {"exp2f", "__mips16_call_stub_sf_1"},
 104   {"floor",  "__mips16_call_stub_df_2"},
 105   {"floorf", "__mips16_call_stub_sf_1"},
 106   {"log2",  "__mips16_call_stub_df_2"},
 107   {"log2f", "__mips16_call_stub_sf_1"},
 108   {"nearbyint",  "__mips16_call_stub_df_2"},
 109   {"nearbyintf", "__mips16_call_stub_sf_1"},
 110   {"rint",  "__mips16_call_stub_df_2"},
 111   {"rintf", "__mips16_call_stub_sf_1"},
 112   {"sin",  "__mips16_call_stub_df_2"},
 113   {"sinf", "__mips16_call_stub_sf_1"},
 114   {"sqrt",  "__mips16_call_stub_df_2"},
 115   {"sqrtf", "__mips16_call_stub_sf_1"},
 116   {"trunc",  "__mips16_call_stub_df_2"},
 117   {"truncf", "__mips16_call_stub_sf_1"},
 118 };
 119
 120 Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
 121                                            const MipsSubtarget &STI)
 122     : MipsTargetLowering(TM, STI) {
 123
 124   // Set up the register classes
 125   addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
 126
 127   if (!Subtarget.useSoftFloat())
 128     setMips16HardFloatLibCalls();
 129
 130   setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);
 131   setOperationAction(ISD::ATOMIC_CMP_SWAP,    MVT::i32,   Expand);
 132   setOperationAction(ISD::ATOMIC_SWAP,        MVT::i32,   Expand);
 133   setOperationAction(ISD::ATOMIC_LOAD_ADD,    MVT::i32,   Expand);
 134   setOperationAction(ISD::ATOMIC_LOAD_SUB,    MVT::i32,   Expand);
 135   setOperationAction(ISD::ATOMIC_LOAD_AND,    MVT::i32,   Expand);
 136   setOperationAction(ISD::ATOMIC_LOAD_OR,     MVT::i32,   Expand);
 137   setOperationAction(ISD::ATOMIC_LOAD_XOR,    MVT::i32,   Expand);
 138   setOperationAction(ISD::ATOMIC_LOAD_NAND,   MVT::i32,   Expand);
 139   setOperationAction(ISD::ATOMIC_LOAD_MIN,    MVT::i32,   Expand);
 140   setOperationAction(ISD::ATOMIC_LOAD_MAX,    MVT::i32,   Expand);
 141   setOperationAction(ISD::ATOMIC_LOAD_UMIN,   MVT::i32,   Expand);
 142   setOperationAction(ISD::ATOMIC_LOAD_UMAX,   MVT::i32,   Expand);
 143
 144   setOperationAction(ISD::ROTR, MVT::i32,  Expand);
 145   setOperationAction(ISD::ROTR, MVT::i64,  Expand);
 146   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
 147   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
 148
 149   computeRegisterProperties(STI.getRegisterInfo());
 150 }
 151
 152 const MipsTargetLowering *
 153 llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
 154                                  const MipsSubtarget &STI) {
 155   return new Mips16TargetLowering(TM, STI);
 156 }
 157
 158 bool
 159 Mips16TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
 160                                                      unsigned,
 161                                                      unsigned,
 162                                                      bool *Fast) const {
 163   return false;
 164 }
 165
 166 MachineBasicBlock *
 167 Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
 168                                                   MachineBasicBlock *BB) const {
 169   switch (MI.getOpcode()) {
 170   default:
 171     return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
 172   case Mips::SelBeqZ:
 173     return emitSel16(Mips::BeqzRxImm16, MI, BB);
 174   case Mips::SelBneZ:
 175     return emitSel16(Mips::BnezRxImm16, MI, BB);
 176   case Mips::SelTBteqZCmpi:
 177     return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
 178   case Mips::SelTBteqZSlti:
 179     return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
 180   case Mips::SelTBteqZSltiu:
 181     return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
 182   case Mips::SelTBtneZCmpi:
 183     return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
 184   case Mips::SelTBtneZSlti:
 185     return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
 186   case Mips::SelTBtneZSltiu:
 187     return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
 188   case Mips::SelTBteqZCmp:
 189     return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
 190   case Mips::SelTBteqZSlt:
 191     return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
 192   case Mips::SelTBteqZSltu:
 193     return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
 194   case Mips::SelTBtneZCmp:
 195     return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
 196   case Mips::SelTBtneZSlt:
 197     return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
 198   case Mips::SelTBtneZSltu:
 199     return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
 200   case Mips::BteqzT8CmpX16:
 201     return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
 202   case Mips::BteqzT8SltX16:
 203     return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
 204   case Mips::BteqzT8SltuX16:
 205     // TBD: figure out a way to get this or remove the instruction
 206     // altogether.
 207     return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
 208   case Mips::BtnezT8CmpX16:
 209     return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
 210   case Mips::BtnezT8SltX16:
 211     return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
 212   case Mips::BtnezT8SltuX16:
 213     // TBD: figure out a way to get this or remove the instruction
 214     // altogether.
 215     return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
 216   case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
 217     Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
 218   case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
 219     Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
 220   case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
 221     Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
 222   case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
 223     Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
 224   case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
 225     Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
 226   case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
 227     Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
 228     break;
 229   case Mips::SltCCRxRy16:
 230     return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
 231     break;
 232   case Mips::SltiCCRxImmX16:
 233     return emitFEXT_CCRXI16_ins
 234       (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
 235   case Mips::SltiuCCRxImmX16:
 236     return emitFEXT_CCRXI16_ins
 237       (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
 238   case Mips::SltuCCRxRy16:
 239     return emitFEXT_CCRX16_ins
 240       (Mips::SltuRxRy16, MI, BB);
 241   }
 242 }
 243
 244 bool Mips16TargetLowering::isEligibleForTailCallOptimization(
 245     const CCState &CCInfo, unsigned NextStackOffset,
 246     const MipsFunctionInfo &FI) const {
 247   // No tail call optimization for mips16.
 248   return false;
 249 }
 250
 251 void Mips16TargetLowering::setMips16HardFloatLibCalls() {
 252   for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
 253     assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
 254            "Array not sorted!");
 255     if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
 256       setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
 257   }
 258
 259   setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
 260   setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
 261 }
 262
 263 //
 264 // The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
 265 // cleaner way to do all of this but it will have to wait until the traditional
 266 // gcc mechanism is completed.
 267 //
 268 // For Pic, in order for Mips16 code to call Mips32 code which according the abi
 269 // have either arguments or returned values placed in floating point registers,
 270 // we use a set of helper functions. (This includes functions which return type
 271 //  complex which on Mips are returned in a pair of floating point registers).
 272 //
 273 // This is an encoding that we inherited from gcc.
 274 // In Mips traditional O32, N32 ABI, floating point numbers are passed in
 275 // floating point argument registers 1,2 only when the first and optionally
 276 // the second arguments are float (sf) or double (df).
 277 // For Mips16 we are only concerned with the situations where floating point
 278 // arguments are being passed in floating point registers by the ABI, because
 279 // Mips16 mode code cannot execute floating point instructions to load those
 280 // values and hence helper functions are needed.
 281 // The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
 282 // the helper function suffixs for these are:
 283 //                        0,  1,    5,        9,         2,   6,        10
 284 // this suffix can then be calculated as follows:
 285 // for a given argument Arg:
 286 //     Arg1x, Arg2x = 1 :  Arg is sf
 287 //                    2 :  Arg is df
 288 //                    0:   Arg is neither sf or df
 289 // So this stub is the string for number Arg1x + Arg2x*4.
 290 // However not all numbers between 0 and 10 are possible, we check anyway and
 291 // assert if the impossible exists.
 292 //
 293
 294 unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
 295   (ArgListTy &Args) const {
 296   unsigned int resultNum = 0;
 297   if (Args.size() >= 1) {
 298     Type *t = Args[0].Ty;
 299     if (t->isFloatTy()) {
 300       resultNum = 1;
 301     }
 302     else if (t->isDoubleTy()) {
 303       resultNum = 2;
 304     }
 305   }
 306   if (resultNum) {
 307     if (Args.size() >=2) {
 308       Type *t = Args[1].Ty;
 309       if (t->isFloatTy()) {
 310         resultNum += 4;
 311       }
 312       else if (t->isDoubleTy()) {
 313         resultNum += 8;
 314       }
 315     }
 316   }
 317   return resultNum;
 318 }
 319
 320 //
 321 // Prefixes are attached to stub numbers depending on the return type.
 322 // return type: float  sf_
 323 //              double df_
 324 //              single complex sc_
 325 //              double complext dc_
 326 //              others  NO PREFIX
 327 //
 328 //
 329 // The full name of a helper function is__mips16_call_stub +
 330 //    return type dependent prefix + stub number
 331 //
 332 // FIXME: This is something that probably should be in a different source file
 333 // and perhaps done differently but my main purpose is to not waste runtime
 334 // on something that we can enumerate in the source. Another possibility is
 335 // to have a python script to generate these mapping tables. This will do
 336 // for now. There are a whole series of helper function mapping arrays, one
 337 // for each return type class as outlined above. There there are 11 possible
 338 // entries. Ones with 0 are ones which should never be selected.
 339 //
 340 // All the arrays are similar except for ones which return neither
 341 // sf, df, sc, dc, in which we only care about ones which have sf or df as a
 342 // first parameter.
 343 //
 344 #define P_ "__mips16_call_stub_"
 345 #define MAX_STUB_NUMBER 10
 346 #define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
 347 #define T P "0" , T1
 348 #define P P_
 349 static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
 350   {nullptr, T1 };
 351 #undef P
 352 #define P P_ "sf_"
 353 static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
 354   { T };
 355 #undef P
 356 #define P P_ "df_"
 357 static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
 358   { T };
 359 #undef P
 360 #define P P_ "sc_"
 361 static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
 362   { T };
 363 #undef P
 364 #define P P_ "dc_"
 365 static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
 366   { T };
 367 #undef P
 368 #undef P_
 369
 370
 371 const char* Mips16TargetLowering::
 372   getMips16HelperFunction
 373     (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
 374   const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
 375 #ifndef NDEBUG
 376   const unsigned int maxStubNum = 10;
 377   assert(stubNum <= maxStubNum);
 378   const bool validStubNum[maxStubNum+1] =
 379     {true, true, true, false, false, true, true, false, false, true, true};
 380   assert(validStubNum[stubNum]);
 381 #endif
 382   const char *result;
 383   if (RetTy->isFloatTy()) {
 384     result = sfMips16Helper[stubNum];
 385   }
 386   else if (RetTy ->isDoubleTy()) {
 387     result = dfMips16Helper[stubNum];
 388   } else if (StructType *SRetTy = dyn_cast<StructType>(RetTy)) {
 389     // check if it's complex
 390     if (SRetTy->getNumElements() == 2) {
 391       if ((SRetTy->getElementType(0)->isFloatTy()) &&
 392           (SRetTy->getElementType(1)->isFloatTy())) {
 393         result = scMips16Helper[stubNum];
 394       } else if ((SRetTy->getElementType(0)->isDoubleTy()) &&
 395                  (SRetTy->getElementType(1)->isDoubleTy())) {
 396         result = dcMips16Helper[stubNum];
 397       } else {
 398         llvm_unreachable("Uncovered condition");
 399       }
 400     } else {
 401       llvm_unreachable("Uncovered condition");
 402     }
 403   } else {
 404     if (stubNum == 0) {
 405       needHelper = false;
 406       return "";
 407     }
 408     result = vMips16Helper[stubNum];
 409   }
 410   needHelper = true;
 411   return result;
 412 }
 413
 414 void Mips16TargetLowering::
 415 getOpndList(SmallVectorImpl<SDValue> &Ops,
 416             std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
 417             bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
 418             bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
 419             SDValue Chain) const {
 420   SelectionDAG &DAG = CLI.DAG;
 421   MachineFunction &MF = DAG.getMachineFunction();
 422   MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
 423   const char* Mips16HelperFunction = nullptr;
 424   bool NeedMips16Helper = false;
 425
 426   if (Subtarget.inMips16HardFloat()) {
 427     //
 428     // currently we don't have symbols tagged with the mips16 or mips32
 429     // qualifier so we will assume that we don't know what kind it is.
 430     // and generate the helper
 431     //
 432     bool LookupHelper = true;
 433     if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
 434       Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
 435
 436       if (std::binary_search(std::begin(HardFloatLibCalls),
 437                              std::end(HardFloatLibCalls), Find))
 438         LookupHelper = false;
 439       else {
 440         const char *Symbol = S->getSymbol();
 441         Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
 442         const Mips16HardFloatInfo::FuncSignature *Signature =
 443             Mips16HardFloatInfo::findFuncSignature(Symbol);
 444         if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) ==
 445                                          FuncInfo->StubsNeeded.end()))) {
 446           FuncInfo->StubsNeeded[Symbol] = Signature;
 447           //
 448           // S2 is normally saved if the stub is for a function which
 449           // returns a float or double value and is not otherwise. This is
 450           // because more work is required after the function the stub
 451           // is calling completes, and so the stub cannot directly return
 452           // and the stub has no stack space to store the return address so
 453           // S2 is used for that purpose.
 454           // In order to take advantage of not saving S2, we need to also
 455           // optimize the call in the stub and this requires some further
 456           // functionality in MipsAsmPrinter which we don't have yet.
 457           // So for now we always save S2. The optimization will be done
 458           // in a follow-on patch.
 459           //
 460           if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
 461             FuncInfo->setSaveS2();
 462         }
 463         // one more look at list of intrinsics
 464         const Mips16IntrinsicHelperType *Helper =
 465             std::lower_bound(std::begin(Mips16IntrinsicHelper),
 466                              std::end(Mips16IntrinsicHelper), IntrinsicFind);
 467         if (Helper != std::end(Mips16IntrinsicHelper) &&
 468             *Helper == IntrinsicFind) {
 469           Mips16HelperFunction = Helper->Helper;
 470           NeedMips16Helper = true;
 471           LookupHelper = false;
 472         }
 473
 474       }
 475     } else if (GlobalAddressSDNode *G =
 476                    dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
 477       Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
 478                              G->getGlobal()->getName().data() };
 479
 480       if (std::binary_search(std::begin(HardFloatLibCalls),
 481                              std::end(HardFloatLibCalls), Find))
 482         LookupHelper = false;
 483     }
 484     if (LookupHelper)
 485       Mips16HelperFunction =
 486         getMips16HelperFunction(CLI.RetTy, CLI.getArgs(), NeedMips16Helper);
 487   }
 488
 489   SDValue JumpTarget = Callee;
 490
 491   // T9 should contain the address of the callee function if
 492   // -relocation-model=pic or it is an indirect call.
 493   if (IsPICCall || !GlobalOrExternal) {
 494     unsigned V0Reg = Mips::V0;
 495     if (NeedMips16Helper) {
 496       RegsToPass.push_front(std::make_pair(V0Reg, Callee));
 497       JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
 498                                          getPointerTy(DAG.getDataLayout()));
 499       ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
 500       JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG,
 501                                  MipsII::MO_GOT, Chain,
 502                                  FuncInfo->callPtrInfo(S->getSymbol()));
 503     } else
 504       RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
 505   }
 506
 507   Ops.push_back(JumpTarget);
 508
 509   MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
 510                                   InternalLinkage, IsCallReloc, CLI, Callee,
 511                                   Chain);
 512 }
 513
 514 MachineBasicBlock *
 515 Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
 516                                 MachineBasicBlock *BB) const {
 517   if (DontExpandCondPseudos16)
 518     return BB;
 519   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 520   DebugLoc DL = MI.getDebugLoc();
 521   // To "insert" a SELECT_CC instruction, we actually have to insert the
 522   // diamond control-flow pattern.  The incoming instruction knows the
 523   // destination vreg to set, the condition code register to branch on, the
 524   // true/false values to select between, and a branch opcode to use.
 525   const BasicBlock *LLVM_BB = BB->getBasicBlock();
 526   MachineFunction::iterator It = ++BB->getIterator();
 527
 528   //  thisMBB:
 529   //  ...
 530   //   TrueVal = ...
 531   //   setcc r1, r2, r3
 532   //   bNE   r1, r0, copy1MBB
 533   //   fallthrough --> copy0MBB
 534   MachineBasicBlock *thisMBB  = BB;
 535   MachineFunction *F = BB->getParent();
 536   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
 537   MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
 538   F->insert(It, copy0MBB);
 539   F->insert(It, sinkMBB);
 540
 541   // Transfer the remainder of BB and its successor edges to sinkMBB.
 542   sinkMBB->splice(sinkMBB->begin(), BB,
 543                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
 544   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 545
 546   // Next, add the true and fallthrough blocks as its successors.
 547   BB->addSuccessor(copy0MBB);
 548   BB->addSuccessor(sinkMBB);
 549
 550   BuildMI(BB, DL, TII->get(Opc))
 551       .addReg(MI.getOperand(3).getReg())
 552       .addMBB(sinkMBB);
 553
 554   //  copy0MBB:
 555   //   %FalseValue = ...
 556   //   # fallthrough to sinkMBB
 557   BB = copy0MBB;
 558
 559   // Update machine-CFG edges
 560   BB->addSuccessor(sinkMBB);
 561
 562   //  sinkMBB:
 563   //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
 564   //  ...
 565   BB = sinkMBB;
 566
 567   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
 568       .addReg(MI.getOperand(1).getReg())
 569       .addMBB(thisMBB)
 570       .addReg(MI.getOperand(2).getReg())
 571       .addMBB(copy0MBB);
 572
 573   MI.eraseFromParent(); // The pseudo instruction is gone now.
 574   return BB;
 575 }
 576
 577 MachineBasicBlock *
 578 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
 579                                  MachineBasicBlock *BB) const {
 580   if (DontExpandCondPseudos16)
 581     return BB;
 582   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 583   DebugLoc DL = MI.getDebugLoc();
 584   // To "insert" a SELECT_CC instruction, we actually have to insert the
 585   // diamond control-flow pattern.  The incoming instruction knows the
 586   // destination vreg to set, the condition code register to branch on, the
 587   // true/false values to select between, and a branch opcode to use.
 588   const BasicBlock *LLVM_BB = BB->getBasicBlock();
 589   MachineFunction::iterator It = ++BB->getIterator();
 590
 591   //  thisMBB:
 592   //  ...
 593   //   TrueVal = ...
 594   //   setcc r1, r2, r3
 595   //   bNE   r1, r0, copy1MBB
 596   //   fallthrough --> copy0MBB
 597   MachineBasicBlock *thisMBB  = BB;
 598   MachineFunction *F = BB->getParent();
 599   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
 600   MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
 601   F->insert(It, copy0MBB);
 602   F->insert(It, sinkMBB);
 603
 604   // Transfer the remainder of BB and its successor edges to sinkMBB.
 605   sinkMBB->splice(sinkMBB->begin(), BB,
 606                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
 607   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 608
 609   // Next, add the true and fallthrough blocks as its successors.
 610   BB->addSuccessor(copy0MBB);
 611   BB->addSuccessor(sinkMBB);
 612
 613   BuildMI(BB, DL, TII->get(Opc2))
 614       .addReg(MI.getOperand(3).getReg())
 615       .addReg(MI.getOperand(4).getReg());
 616   BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
 617
 618   //  copy0MBB:
 619   //   %FalseValue = ...
 620   //   # fallthrough to sinkMBB
 621   BB = copy0MBB;
 622
 623   // Update machine-CFG edges
 624   BB->addSuccessor(sinkMBB);
 625
 626   //  sinkMBB:
 627   //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
 628   //  ...
 629   BB = sinkMBB;
 630
 631   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
 632       .addReg(MI.getOperand(1).getReg())
 633       .addMBB(thisMBB)
 634       .addReg(MI.getOperand(2).getReg())
 635       .addMBB(copy0MBB);
 636
 637   MI.eraseFromParent(); // The pseudo instruction is gone now.
 638   return BB;
 639
 640 }
 641
 642 MachineBasicBlock *
 643 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
 644                                   MachineInstr &MI,
 645                                   MachineBasicBlock *BB) const {
 646   if (DontExpandCondPseudos16)
 647     return BB;
 648   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 649   DebugLoc DL = MI.getDebugLoc();
 650   // To "insert" a SELECT_CC instruction, we actually have to insert the
 651   // diamond control-flow pattern.  The incoming instruction knows the
 652   // destination vreg to set, the condition code register to branch on, the
 653   // true/false values to select between, and a branch opcode to use.
 654   const BasicBlock *LLVM_BB = BB->getBasicBlock();
 655   MachineFunction::iterator It = ++BB->getIterator();
 656
 657   //  thisMBB:
 658   //  ...
 659   //   TrueVal = ...
 660   //   setcc r1, r2, r3
 661   //   bNE   r1, r0, copy1MBB
 662   //   fallthrough --> copy0MBB
 663   MachineBasicBlock *thisMBB  = BB;
 664   MachineFunction *F = BB->getParent();
 665   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
 666   MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
 667   F->insert(It, copy0MBB);
 668   F->insert(It, sinkMBB);
 669
 670   // Transfer the remainder of BB and its successor edges to sinkMBB.
 671   sinkMBB->splice(sinkMBB->begin(), BB,
 672                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
 673   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 674
 675   // Next, add the true and fallthrough blocks as its successors.
 676   BB->addSuccessor(copy0MBB);
 677   BB->addSuccessor(sinkMBB);
 678
 679   BuildMI(BB, DL, TII->get(Opc2))
 680       .addReg(MI.getOperand(3).getReg())
 681       .addImm(MI.getOperand(4).getImm());
 682   BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
 683
 684   //  copy0MBB:
 685   //   %FalseValue = ...
 686   //   # fallthrough to sinkMBB
 687   BB = copy0MBB;
 688
 689   // Update machine-CFG edges
 690   BB->addSuccessor(sinkMBB);
 691
 692   //  sinkMBB:
 693   //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
 694   //  ...
 695   BB = sinkMBB;
 696
 697   BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
 698       .addReg(MI.getOperand(1).getReg())
 699       .addMBB(thisMBB)
 700       .addReg(MI.getOperand(2).getReg())
 701       .addMBB(copy0MBB);
 702
 703   MI.eraseFromParent(); // The pseudo instruction is gone now.
 704   return BB;
 705
 706 }
 707
 708 MachineBasicBlock *
 709 Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
 710                                           MachineInstr &MI,
 711                                           MachineBasicBlock *BB) const {
 712   if (DontExpandCondPseudos16)
 713     return BB;
 714   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 715   unsigned regX = MI.getOperand(0).getReg();
 716   unsigned regY = MI.getOperand(1).getReg();
 717   MachineBasicBlock *target = MI.getOperand(2).getMBB();
 718   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
 719       .addReg(regX)
 720       .addReg(regY);
 721   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
 722   MI.eraseFromParent(); // The pseudo instruction is gone now.
 723   return BB;
 724 }
 725
 726 MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
 727     unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
 728     MachineInstr &MI, MachineBasicBlock *BB) const {
 729   if (DontExpandCondPseudos16)
 730     return BB;
 731   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 732   unsigned regX = MI.getOperand(0).getReg();
 733   int64_t imm = MI.getOperand(1).getImm();
 734   MachineBasicBlock *target = MI.getOperand(2).getMBB();
 735   unsigned CmpOpc;
 736   if (isUInt<8>(imm))
 737     CmpOpc = CmpiOpc;
 738   else if ((!ImmSigned && isUInt<16>(imm)) ||
 739            (ImmSigned && isInt<16>(imm)))
 740     CmpOpc = CmpiXOpc;
 741   else
 742     llvm_unreachable("immediate field not usable");
 743   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
 744   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
 745   MI.eraseFromParent(); // The pseudo instruction is gone now.
 746   return BB;
 747 }
 748
 749 static unsigned Mips16WhichOp8uOr16simm
 750   (unsigned shortOp, unsigned longOp, int64_t Imm) {
 751   if (isUInt<8>(Imm))
 752     return shortOp;
 753   else if (isInt<16>(Imm))
 754     return longOp;
 755   else
 756     llvm_unreachable("immediate field not usable");
 757 }
 758
 759 MachineBasicBlock *
 760 Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
 761                                           MachineBasicBlock *BB) const {
 762   if (DontExpandCondPseudos16)
 763     return BB;
 764   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 765   unsigned CC = MI.getOperand(0).getReg();
 766   unsigned regX = MI.getOperand(1).getReg();
 767   unsigned regY = MI.getOperand(2).getReg();
 768   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
 769       .addReg(regX)
 770       .addReg(regY);
 771   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
 772       .addReg(Mips::T8);
 773   MI.eraseFromParent(); // The pseudo instruction is gone now.
 774   return BB;
 775 }
 776
 777 MachineBasicBlock *
 778 Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
 779                                            MachineInstr &MI,
 780                                            MachineBasicBlock *BB) const {
 781   if (DontExpandCondPseudos16)
 782     return BB;
 783   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
 784   unsigned CC = MI.getOperand(0).getReg();
 785   unsigned regX = MI.getOperand(1).getReg();
 786   int64_t Imm = MI.getOperand(2).getImm();
 787   unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
 788   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
 789   BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
 790       .addReg(Mips::T8);
 791   MI.eraseFromParent(); // The pseudo instruction is gone now.
 792   return BB;
 793
 794 }