lib/Target/Mips/MipsISelLowering.h

   1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that Mips uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
  15 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
  16
  17 #include "MCTargetDesc/MipsABIInfo.h"
  18 #include "MCTargetDesc/MipsBaseInfo.h"
  19 #include "MCTargetDesc/MipsMCTargetDesc.h"
  20 #include "Mips.h"
  21 #include "llvm/CodeGen/CallingConvLower.h"
  22 #include "llvm/CodeGen/ISDOpcodes.h"
  23 #include "llvm/CodeGen/MachineMemOperand.h"
  24 #include "llvm/CodeGen/SelectionDAG.h"
  25 #include "llvm/CodeGen/SelectionDAGNodes.h"
  26 #include "llvm/CodeGen/TargetLowering.h"
  27 #include "llvm/CodeGen/ValueTypes.h"
  28 #include "llvm/IR/CallingConv.h"
  29 #include "llvm/IR/InlineAsm.h"
  30 #include "llvm/IR/Type.h"
  31 #include "llvm/Support/MachineValueType.h"
  32 #include "llvm/Target/TargetMachine.h"
  33 #include <algorithm>
  34 #include <cassert>
  35 #include <deque>
  36 #include <string>
  37 #include <utility>
  38 #include <vector>
  39
  40 namespace llvm {
  41
  42 class Argument;
  43 class CCState;
  44 class CCValAssign;
  45 class FastISel;
  46 class FunctionLoweringInfo;
  47 class MachineBasicBlock;
  48 class MachineFrameInfo;
  49 class MachineInstr;
  50 class MipsCCState;
  51 class MipsFunctionInfo;
  52 class MipsSubtarget;
  53 class MipsTargetMachine;
  54 class TargetLibraryInfo;
  55 class TargetRegisterClass;
  56
  57   namespace MipsISD {
  58
  59     enum NodeType : unsigned {
  60       // Start the numbering from where ISD NodeType finishes.
  61       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  62
  63       // Jump and link (call)
  64       JmpLink,
  65
  66       // Tail call
  67       TailCall,
  68
  69       // Get the Highest (63-48) 16 bits from a 64-bit immediate
  70       Highest,
  71
  72       // Get the Higher (47-32) 16 bits from a 64-bit immediate
  73       Higher,
  74
  75       // Get the High 16 bits from a 32/64-bit immediate
  76       // No relation with Mips Hi register
  77       Hi,
  78
  79       // Get the Lower 16 bits from a 32/64-bit immediate
  80       // No relation with Mips Lo register
  81       Lo,
  82
  83       // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
  84       GotHi,
  85
  86       // Get the High 16 bits from a 32-bit immediate for accessing TLS.
  87       TlsHi,
  88
  89       // Handle gp_rel (small data/bss sections) relocation.
  90       GPRel,
  91
  92       // Thread Pointer
  93       ThreadPointer,
  94
  95       // Vector Floating Point Multiply and Subtract
  96       FMS,
  97
  98       // Floating Point Branch Conditional
  99       FPBrcond,
 100
 101       // Floating Point Compare
 102       FPCmp,
 103
 104       // Floating point select
 105       FSELECT,
 106
 107       // Node used to generate an MTC1 i32 to f64 instruction
 108       MTC1_D64,
 109
 110       // Floating Point Conditional Moves
 111       CMovFP_T,
 112       CMovFP_F,
 113
 114       // FP-to-int truncation node.
 115       TruncIntFP,
 116
 117       // Return
 118       Ret,
 119
 120       // Interrupt, exception, error trap Return
 121       ERet,
 122
 123       // Software Exception Return.
 124       EH_RETURN,
 125
 126       // Node used to extract integer from accumulator.
 127       MFHI,
 128       MFLO,
 129
 130       // Node used to insert integers to accumulator.
 131       MTLOHI,
 132
 133       // Mult nodes.
 134       Mult,
 135       Multu,
 136
 137       // MAdd/Sub nodes
 138       MAdd,
 139       MAddu,
 140       MSub,
 141       MSubu,
 142
 143       // DivRem(u)
 144       DivRem,
 145       DivRemU,
 146       DivRem16,
 147       DivRemU16,
 148
 149       BuildPairF64,
 150       ExtractElementF64,
 151
 152       Wrapper,
 153
 154       DynAlloc,
 155
 156       Sync,
 157
 158       Ext,
 159       Ins,
 160       CIns,
 161
 162       // EXTR.W instrinsic nodes.
 163       EXTP,
 164       EXTPDP,
 165       EXTR_S_H,
 166       EXTR_W,
 167       EXTR_R_W,
 168       EXTR_RS_W,
 169       SHILO,
 170       MTHLIP,
 171
 172       // DPA.W intrinsic nodes.
 173       MULSAQ_S_W_PH,
 174       MAQ_S_W_PHL,
 175       MAQ_S_W_PHR,
 176       MAQ_SA_W_PHL,
 177       MAQ_SA_W_PHR,
 178       DPAU_H_QBL,
 179       DPAU_H_QBR,
 180       DPSU_H_QBL,
 181       DPSU_H_QBR,
 182       DPAQ_S_W_PH,
 183       DPSQ_S_W_PH,
 184       DPAQ_SA_L_W,
 185       DPSQ_SA_L_W,
 186       DPA_W_PH,
 187       DPS_W_PH,
 188       DPAQX_S_W_PH,
 189       DPAQX_SA_W_PH,
 190       DPAX_W_PH,
 191       DPSX_W_PH,
 192       DPSQX_S_W_PH,
 193       DPSQX_SA_W_PH,
 194       MULSA_W_PH,
 195
 196       MULT,
 197       MULTU,
 198       MADD_DSP,
 199       MADDU_DSP,
 200       MSUB_DSP,
 201       MSUBU_DSP,
 202
 203       // DSP shift nodes.
 204       SHLL_DSP,
 205       SHRA_DSP,
 206       SHRL_DSP,
 207
 208       // DSP setcc and select_cc nodes.
 209       SETCC_DSP,
 210       SELECT_CC_DSP,
 211
 212       // Vector comparisons.
 213       // These take a vector and return a boolean.
 214       VALL_ZERO,
 215       VANY_ZERO,
 216       VALL_NONZERO,
 217       VANY_NONZERO,
 218
 219       // These take a vector and return a vector bitmask.
 220       VCEQ,
 221       VCLE_S,
 222       VCLE_U,
 223       VCLT_S,
 224       VCLT_U,
 225
 226       // Vector Shuffle with mask as an operand
 227       VSHF,  // Generic shuffle
 228       SHF,   // 4-element set shuffle.
 229       ILVEV, // Interleave even elements
 230       ILVOD, // Interleave odd elements
 231       ILVL,  // Interleave left elements
 232       ILVR,  // Interleave right elements
 233       PCKEV, // Pack even elements
 234       PCKOD, // Pack odd elements
 235
 236       // Vector Lane Copy
 237       INSVE, // Copy element from one vector to another
 238
 239       // Combined (XOR (OR $a, $b), -1)
 240       VNOR,
 241
 242       // Extended vector element extraction
 243       VEXTRACT_SEXT_ELT,
 244       VEXTRACT_ZEXT_ELT,
 245
 246       // Load/Store Left/Right nodes.
 247       LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
 248       LWR,
 249       SWL,
 250       SWR,
 251       LDL,
 252       LDR,
 253       SDL,
 254       SDR
 255     };
 256
 257   } // ene namespace MipsISD
 258
 259   //===--------------------------------------------------------------------===//
 260   // TargetLowering Implementation
 261   //===--------------------------------------------------------------------===//
 262
 263   class MipsTargetLowering : public TargetLowering  {
 264     bool isMicroMips;
 265
 266   public:
 267     explicit MipsTargetLowering(const MipsTargetMachine &TM,
 268                                 const MipsSubtarget &STI);
 269
 270     static const MipsTargetLowering *create(const MipsTargetMachine &TM,
 271                                             const MipsSubtarget &STI);
 272
 273     /// createFastISel - This method returns a target specific FastISel object,
 274     /// or null if the target does not support "fast" ISel.
 275     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 276                              const TargetLibraryInfo *libInfo) const override;
 277
 278     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
 279       return MVT::i32;
 280     }
 281
 282     EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
 283                             ISD::NodeType) const override;
 284
 285     bool isCheapToSpeculateCttz() const override;
 286     bool isCheapToSpeculateCtlz() const override;
 287
 288     /// Return the register type for a given MVT, ensuring vectors are treated
 289     /// as a series of gpr sized integers.
 290     MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
 291                                       EVT VT) const override;
 292
 293     /// Return the number of registers for a given MVT, ensuring vectors are
 294     /// treated as a series of gpr sized integers.
 295     unsigned getNumRegistersForCallingConv(LLVMContext &Context,
 296                                            CallingConv::ID CC,
 297                                            EVT VT) const override;
 298
 299     /// Break down vectors to the correct number of gpr sized integers.
 300     unsigned getVectorTypeBreakdownForCallingConv(
 301         LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
 302         unsigned &NumIntermediates, MVT &RegisterVT) const override;
 303
 304     /// Return the correct alignment for the current calling convention.
 305     unsigned getABIAlignmentForCallingConv(Type *ArgTy,
 306                                            DataLayout DL) const override {
 307       if (ArgTy->isVectorTy())
 308         return std::min(DL.getABITypeAlignment(ArgTy), 8U);
 309       return DL.getABITypeAlignment(ArgTy);
 310     }
 311
 312     ISD::NodeType getExtendForAtomicOps() const override {
 313       return ISD::SIGN_EXTEND;
 314     }
 315
 316     void LowerOperationWrapper(SDNode *N,
 317                                SmallVectorImpl<SDValue> &Results,
 318                                SelectionDAG &DAG) const override;
 319
 320     /// LowerOperation - Provide custom lowering hooks for some operations.
 321     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 322
 323     /// ReplaceNodeResults - Replace the results of node with an illegal result
 324     /// type with new values built out of custom code.
 325     ///
 326     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 327                             SelectionDAG &DAG) const override;
 328
 329     /// getTargetNodeName - This method returns the name of a target specific
 330     //  DAG node.
 331     const char *getTargetNodeName(unsigned Opcode) const override;
 332
 333     /// getSetCCResultType - get the ISD::SETCC result ValueType
 334     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 335                            EVT VT) const override;
 336
 337     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 338
 339     MachineBasicBlock *
 340     EmitInstrWithCustomInserter(MachineInstr &MI,
 341                                 MachineBasicBlock *MBB) const override;
 342
 343     void AdjustInstrPostInstrSelection(MachineInstr &MI,
 344                                        SDNode *Node) const override;
 345
 346     void HandleByVal(CCState *, unsigned &, unsigned) const override;
 347
 348     unsigned getRegisterByName(const char* RegName, EVT VT,
 349                                SelectionDAG &DAG) const override;
 350
 351     /// If a physical register, this returns the register that receives the
 352     /// exception address on entry to an EH pad.
 353     unsigned
 354     getExceptionPointerRegister(const Constant *PersonalityFn) const override {
 355       return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
 356     }
 357
 358     /// If a physical register, this returns the register that receives the
 359     /// exception typeid on entry to a landing pad.
 360     unsigned
 361     getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
 362       return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
 363     }
 364
 365     /// Returns true if a cast between SrcAS and DestAS is a noop.
 366     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
 367       // Mips doesn't have any special address spaces so we just reserve
 368       // the first 256 for software use (e.g. OpenCL) and treat casts
 369       // between them as noops.
 370       return SrcAS < 256 && DestAS < 256;
 371     }
 372
 373     bool isJumpTableRelative() const override {
 374       return getTargetMachine().isPositionIndependent();
 375     }
 376
 377    CCAssignFn *CCAssignFnForCall() const;
 378
 379    CCAssignFn *CCAssignFnForReturn() const;
 380
 381   protected:
 382     SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
 383
 384     // This method creates the following nodes, which are necessary for
 385     // computing a local symbol's address:
 386     //
 387     // (add (load (wrapper $gp, %got(sym)), %lo(sym))
 388     template <class NodeTy>
 389     SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
 390                          bool IsN32OrN64) const {
 391       unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
 392       SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
 393                                 getTargetNode(N, Ty, DAG, GOTFlag));
 394       SDValue Load =
 395           DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
 396                       MachinePointerInfo::getGOT(DAG.getMachineFunction()));
 397       unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
 398       SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
 399                                getTargetNode(N, Ty, DAG, LoFlag));
 400       return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
 401     }
 402
 403     // This method creates the following nodes, which are necessary for
 404     // computing a global symbol's address:
 405     //
 406     // (load (wrapper $gp, %got(sym)))
 407     template <class NodeTy>
 408     SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
 409                           unsigned Flag, SDValue Chain,
 410                           const MachinePointerInfo &PtrInfo) const {
 411       SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
 412                                 getTargetNode(N, Ty, DAG, Flag));
 413       return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
 414     }
 415
 416     // This method creates the following nodes, which are necessary for
 417     // computing a global symbol's address in large-GOT mode:
 418     //
 419     // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
 420     template <class NodeTy>
 421     SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
 422                                   SelectionDAG &DAG, unsigned HiFlag,
 423                                   unsigned LoFlag, SDValue Chain,
 424                                   const MachinePointerInfo &PtrInfo) const {
 425       SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
 426                                getTargetNode(N, Ty, DAG, HiFlag));
 427       Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
 428       SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
 429                                     getTargetNode(N, Ty, DAG, LoFlag));
 430       return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
 431     }
 432
 433     // This method creates the following nodes, which are necessary for
 434     // computing a symbol's address in non-PIC mode:
 435     //
 436     // (add %hi(sym), %lo(sym))
 437     //
 438     // This method covers O32, N32 and N64 in sym32 mode.
 439     template <class NodeTy>
 440     SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
 441                           SelectionDAG &DAG) const {
 442       SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
 443       SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
 444       return DAG.getNode(ISD::ADD, DL, Ty,
 445                          DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
 446                          DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
 447    }
 448
 449    // This method creates the following nodes, which are necessary for
 450    // computing a symbol's address in non-PIC mode for N64.
 451    //
 452    // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
 453    //            16), %lo(%sym))
 454    //
 455    // FIXME: This method is not efficent for (micro)MIPS64R6.
 456    template <class NodeTy>
 457    SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
 458                           SelectionDAG &DAG) const {
 459       SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
 460       SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
 461
 462       SDValue Highest =
 463           DAG.getNode(MipsISD::Highest, DL, Ty,
 464                       getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
 465       SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
 466       SDValue HigherPart =
 467           DAG.getNode(ISD::ADD, DL, Ty, Highest,
 468                       DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
 469       SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
 470       SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
 471       SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
 472                                 DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
 473       SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
 474
 475       return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
 476                          DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
 477    }
 478
 479     // This method creates the following nodes, which are necessary for
 480     // computing a symbol's address using gp-relative addressing:
 481     //
 482     // (add $gp, %gp_rel(sym))
 483     template <class NodeTy>
 484     SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
 485                          SelectionDAG &DAG, bool IsN64) const {
 486       SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
 487       return DAG.getNode(
 488           ISD::ADD, DL, Ty,
 489           DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
 490           DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
 491     }
 492
 493     /// This function fills Ops, which is the list of operands that will later
 494     /// be used when a function call node is created. It also generates
 495     /// copyToReg nodes to set up argument registers.
 496     virtual void
 497     getOpndList(SmallVectorImpl<SDValue> &Ops,
 498                 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
 499                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
 500                 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
 501                 SDValue Chain) const;
 502
 503   protected:
 504     SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
 505     SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 506
 507     // Subtarget Info
 508     const MipsSubtarget &Subtarget;
 509     // Cache the ABI from the TargetMachine, we use it everywhere.
 510     const MipsABIInfo &ABI;
 511
 512   private:
 513     // Create a TargetGlobalAddress node.
 514     SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
 515                           unsigned Flag) const;
 516
 517     // Create a TargetExternalSymbol node.
 518     SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
 519                           unsigned Flag) const;
 520
 521     // Create a TargetBlockAddress node.
 522     SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
 523                           unsigned Flag) const;
 524
 525     // Create a TargetJumpTable node.
 526     SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
 527                           unsigned Flag) const;
 528
 529     // Create a TargetConstantPool node.
 530     SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
 531                           unsigned Flag) const;
 532
 533     // Lower Operand helpers
 534     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 535                             CallingConv::ID CallConv, bool isVarArg,
 536                             const SmallVectorImpl<ISD::InputArg> &Ins,
 537                             const SDLoc &dl, SelectionDAG &DAG,
 538                             SmallVectorImpl<SDValue> &InVals,
 539                             TargetLowering::CallLoweringInfo &CLI) const;
 540
 541     // Lower Operand specifics
 542     SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 543     SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 544     SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 545     SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 546     SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 547     SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
 548     SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 549     SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
 550     SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 551     SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
 552     SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
 553     SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
 554     SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 555     SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 556     SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
 557     SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
 558     SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
 559     SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
 560                                  bool IsSRA) const;
 561     SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
 562     SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
 563
 564     /// isEligibleForTailCallOptimization - Check whether the call is eligible
 565     /// for tail call optimization.
 566     virtual bool
 567     isEligibleForTailCallOptimization(const CCState &CCInfo,
 568                                       unsigned NextStackOffset,
 569                                       const MipsFunctionInfo &FI) const = 0;
 570
 571     /// copyByValArg - Copy argument registers which were used to pass a byval
 572     /// argument to the stack. Create a stack frame object for the byval
 573     /// argument.
 574     void copyByValRegs(SDValue Chain, const SDLoc &DL,
 575                        std::vector<SDValue> &OutChains, SelectionDAG &DAG,
 576                        const ISD::ArgFlagsTy &Flags,
 577                        SmallVectorImpl<SDValue> &InVals,
 578                        const Argument *FuncArg, unsigned FirstReg,
 579                        unsigned LastReg, const CCValAssign &VA,
 580                        MipsCCState &State) const;
 581
 582     /// passByValArg - Pass a byval argument in registers or on stack.
 583     void passByValArg(SDValue Chain, const SDLoc &DL,
 584                       std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
 585                       SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
 586                       MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
 587                       unsigned FirstReg, unsigned LastReg,
 588                       const ISD::ArgFlagsTy &Flags, bool isLittle,
 589                       const CCValAssign &VA) const;
 590
 591     /// writeVarArgRegs - Write variable function arguments passed in registers
 592     /// to the stack. Also create a stack frame object for the first variable
 593     /// argument.
 594     void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
 595                          const SDLoc &DL, SelectionDAG &DAG,
 596                          CCState &State) const;
 597
 598     SDValue
 599     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 600                          const SmallVectorImpl<ISD::InputArg> &Ins,
 601                          const SDLoc &dl, SelectionDAG &DAG,
 602                          SmallVectorImpl<SDValue> &InVals) const override;
 603
 604     SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
 605                            SDValue Arg, const SDLoc &DL, bool IsTailCall,
 606                            SelectionDAG &DAG) const;
 607
 608     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 609                       SmallVectorImpl<SDValue> &InVals) const override;
 610
 611     bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
 612                         bool isVarArg,
 613                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 614                         LLVMContext &Context) const override;
 615
 616     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 617                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 618                         const SmallVectorImpl<SDValue> &OutVals,
 619                         const SDLoc &dl, SelectionDAG &DAG) const override;
 620
 621     SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
 622                                  const SDLoc &DL, SelectionDAG &DAG) const;
 623
 624     bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
 625
 626     // Inline asm support
 627     ConstraintType getConstraintType(StringRef Constraint) const override;
 628
 629     /// Examine constraint string and operand type and determine a weight value.
 630     /// The operand object must already have been set up with the operand type.
 631     ConstraintWeight getSingleConstraintMatchWeight(
 632       AsmOperandInfo &info, const char *constraint) const override;
 633
 634     /// This function parses registers that appear in inline-asm constraints.
 635     /// It returns pair (0, 0) on failure.
 636     std::pair<unsigned, const TargetRegisterClass *>
 637     parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
 638
 639     std::pair<unsigned, const TargetRegisterClass *>
 640     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 641                                  StringRef Constraint, MVT VT) const override;
 642
 643     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 644     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
 645     /// true it means one of the asm constraint of the inline asm instruction
 646     /// being processed is 'm'.
 647     void LowerAsmOperandForConstraint(SDValue Op,
 648                                       std::string &Constraint,
 649                                       std::vector<SDValue> &Ops,
 650                                       SelectionDAG &DAG) const override;
 651
 652     unsigned
 653     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 654       if (ConstraintCode == "R")
 655         return InlineAsm::Constraint_R;
 656       else if (ConstraintCode == "ZC")
 657         return InlineAsm::Constraint_ZC;
 658       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 659     }
 660
 661     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 662                                Type *Ty, unsigned AS,
 663                                Instruction *I = nullptr) const override;
 664
 665     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 666
 667     EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
 668                             unsigned SrcAlign,
 669                             bool IsMemset, bool ZeroMemset,
 670                             bool MemcpyStrSrc,
 671                             MachineFunction &MF) const override;
 672
 673     /// isFPImmLegal - Returns true if the target can instruction select the
 674     /// specified FP immediate natively. If false, the legalizer will
 675     /// materialize the FP immediate as a load from a constant pool.
 676     bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
 677
 678     unsigned getJumpTableEncoding() const override;
 679     bool useSoftFloat() const override;
 680
 681     bool shouldInsertFencesForAtomic(const Instruction *I) const override {
 682       return true;
 683     }
 684
 685     /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
 686     MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
 687                                                 MachineBasicBlock *BB,
 688                                                 unsigned Size, unsigned DstReg,
 689                                                 unsigned SrcRec) const;
 690
 691     MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
 692                                         MachineBasicBlock *BB) const;
 693     MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
 694                                                 MachineBasicBlock *BB,
 695                                                 unsigned Size) const;
 696     MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
 697                                          MachineBasicBlock *BB) const;
 698     MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
 699                                                  MachineBasicBlock *BB,
 700                                                  unsigned Size) const;
 701     MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
 702     MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
 703                                         bool isFPCmp, unsigned Opc) const;
 704     MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI,
 705                                           MachineBasicBlock *BB) const;
 706   };
 707
 708   /// Create MipsTargetLowering objects.
 709   const MipsTargetLowering *
 710   createMips16TargetLowering(const MipsTargetMachine &TM,
 711                              const MipsSubtarget &STI);
 712   const MipsTargetLowering *
 713   createMipsSETargetLowering(const MipsTargetMachine &TM,
 714                              const MipsSubtarget &STI);
 715
 716 namespace Mips {
 717
 718 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 719                          const TargetLibraryInfo *libInfo);
 720
 721 } // end namespace Mips
 722
 723 } // end namespace llvm
 724
 725 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H