1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 #include "MipsMachineFunction.h"
10 #include "MCTargetDesc/MipsABIInfo.h"
11 #include "MipsSubtarget.h"
12 #include "MipsTargetMachine.h"
13 #include "llvm/CodeGen/MachineFrameInfo.h"
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/PseudoSourceValue.h"
16 #include "llvm/CodeGen/TargetRegisterInfo.h"
17 #include "llvm/Support/CommandLine.h"
22 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden
, cl::init(true),
23 cl::desc("Always use $gp as the global base register."));
25 MipsFunctionInfo::~MipsFunctionInfo() = default;
27 bool MipsFunctionInfo::globalBaseRegSet() const {
31 static const TargetRegisterClass
&getGlobalBaseRegClass(MachineFunction
&MF
) {
32 auto &STI
= static_cast<const MipsSubtarget
&>(MF
.getSubtarget());
33 auto &TM
= static_cast<const MipsTargetMachine
&>(MF
.getTarget());
35 if (STI
.inMips16Mode())
36 return Mips::CPU16RegsRegClass
;
38 if (STI
.inMicroMipsMode())
39 return Mips::GPRMM16RegClass
;
41 if (TM
.getABI().IsN64())
42 return Mips::GPR64RegClass
;
44 return Mips::GPR32RegClass
;
47 unsigned MipsFunctionInfo::getGlobalBaseReg() {
50 MF
.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF
));
54 void MipsFunctionInfo::createEhDataRegsFI() {
55 const TargetRegisterInfo
&TRI
= *MF
.getSubtarget().getRegisterInfo();
56 for (int I
= 0; I
< 4; ++I
) {
57 const TargetRegisterClass
&RC
=
58 static_cast<const MipsTargetMachine
&>(MF
.getTarget()).getABI().IsN64()
60 : Mips::GPR32RegClass
;
62 EhDataRegFI
[I
] = MF
.getFrameInfo().CreateStackObject(TRI
.getSpillSize(RC
),
63 TRI
.getSpillAlignment(RC
), false);
67 void MipsFunctionInfo::createISRRegFI() {
68 // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
69 // The current implementation only supports Mips32r2+ not Mips64rX. Status
70 // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture,
71 // however Mips32r2+ is the supported architecture.
72 const TargetRegisterClass
&RC
= Mips::GPR32RegClass
;
73 const TargetRegisterInfo
&TRI
= *MF
.getSubtarget().getRegisterInfo();
75 for (int I
= 0; I
< 2; ++I
)
76 ISRDataRegFI
[I
] = MF
.getFrameInfo().CreateStackObject(
77 TRI
.getSpillSize(RC
), TRI
.getSpillAlignment(RC
), false);
80 bool MipsFunctionInfo::isEhDataRegFI(int FI
) const {
81 return CallsEhReturn
&& (FI
== EhDataRegFI
[0] || FI
== EhDataRegFI
[1]
82 || FI
== EhDataRegFI
[2] || FI
== EhDataRegFI
[3]);
85 bool MipsFunctionInfo::isISRRegFI(int FI
) const {
86 return IsISR
&& (FI
== ISRDataRegFI
[0] || FI
== ISRDataRegFI
[1]);
88 MachinePointerInfo
MipsFunctionInfo::callPtrInfo(const char *ES
) {
89 return MachinePointerInfo(MF
.getPSVManager().getExternalSymbolCallEntry(ES
));
92 MachinePointerInfo
MipsFunctionInfo::callPtrInfo(const GlobalValue
*GV
) {
93 return MachinePointerInfo(MF
.getPSVManager().getGlobalValueCallEntry(GV
));
96 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass
*RC
) {
97 const TargetRegisterInfo
&TRI
= *MF
.getSubtarget().getRegisterInfo();
98 if (MoveF64ViaSpillFI
== -1) {
99 MoveF64ViaSpillFI
= MF
.getFrameInfo().CreateStackObject(
100 TRI
.getSpillSize(*RC
), TRI
.getSpillAlignment(*RC
), false);
102 return MoveF64ViaSpillFI
;
105 void MipsFunctionInfo::anchor() {}