lib/Target/Mips/MipsRegisterBankInfo.cpp

   1 //===- MipsRegisterBankInfo.cpp ---------------------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file implements the targeting of the RegisterBankInfo class for Mips.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MipsInstrInfo.h"
  14 #include "MipsRegisterBankInfo.h"
  15 #include "llvm/CodeGen/MachineRegisterInfo.h"
  16
  17 #define GET_TARGET_REGBANK_IMPL
  18
  19 #define DEBUG_TYPE "registerbankinfo"
  20
  21 #include "MipsGenRegisterBank.inc"
  22
  23 namespace llvm {
  24 namespace Mips {
  25 enum PartialMappingIdx {
  26   PMI_GPR,
  27   PMI_Min = PMI_GPR,
  28 };
  29
  30 RegisterBankInfo::PartialMapping PartMappings[]{
  31     {0, 32, GPRBRegBank}
  32 };
  33
  34 enum ValueMappingIdx { InvalidIdx = 0, GPRIdx = 1 };
  35
  36 RegisterBankInfo::ValueMapping ValueMappings[] = {
  37     // invalid
  38     {nullptr, 0},
  39     // 3 operands in GPRs
  40     {&PartMappings[PMI_GPR - PMI_Min], 1},
  41     {&PartMappings[PMI_GPR - PMI_Min], 1},
  42     {&PartMappings[PMI_GPR - PMI_Min], 1}};
  43
  44 } // end namespace Mips
  45 } // end namespace llvm
  46
  47 using namespace llvm;
  48
  49 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
  50     : MipsGenRegisterBankInfo() {}
  51
  52 const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
  53     const TargetRegisterClass &RC) const {
  54   using namespace Mips;
  55
  56   switch (RC.getID()) {
  57   case Mips::GPR32RegClassID:
  58   case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
  59   case Mips::GPRMM16MovePPairFirstRegClassID:
  60   case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID:
  61   case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
  62   case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
  63   case Mips::SP32RegClassID:
  64     return getRegBank(Mips::GPRBRegBankID);
  65   default:
  66     llvm_unreachable("Register class not supported");
  67   }
  68 }
  69
  70 const RegisterBankInfo::InstructionMapping &
  71 MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
  72
  73   unsigned Opc = MI.getOpcode();
  74
  75   const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
  76   if (Mapping.isValid())
  77     return Mapping;
  78
  79   using namespace TargetOpcode;
  80
  81   unsigned NumOperands = MI.getNumOperands();
  82   const ValueMapping *OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
  83
  84   switch (Opc) {
  85   case G_TRUNC:
  86   case G_ADD:
  87   case G_SUB:
  88   case G_MUL:
  89   case G_LOAD:
  90   case G_STORE:
  91   case G_ZEXTLOAD:
  92   case G_SEXTLOAD:
  93   case G_GEP:
  94   case G_AND:
  95   case G_OR:
  96   case G_XOR:
  97   case G_SHL:
  98   case G_ASHR:
  99   case G_LSHR:
 100   case G_SDIV:
 101   case G_UDIV:
 102   case G_SREM:
 103   case G_UREM:
 104     OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
 105     break;
 106   case G_CONSTANT:
 107   case G_FRAME_INDEX:
 108   case G_GLOBAL_VALUE:
 109   case G_BRCOND:
 110     OperandsMapping =
 111         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
 112     break;
 113   case G_ICMP:
 114     OperandsMapping =
 115         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
 116                             &Mips::ValueMappings[Mips::GPRIdx],
 117                             &Mips::ValueMappings[Mips::GPRIdx]});
 118     break;
 119   case G_SELECT:
 120     OperandsMapping =
 121         getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx],
 122                             &Mips::ValueMappings[Mips::GPRIdx],
 123                             &Mips::ValueMappings[Mips::GPRIdx],
 124                             &Mips::ValueMappings[Mips::GPRIdx]});
 125     break;
 126   default:
 127     return getInvalidInstructionMapping();
 128   }
 129
 130   return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
 131                                NumOperands);
 132 }