lib/Target/Mips/MipsSEISelLowering.h

   1 //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Subclass of MipsTargetLowering specialized for mips32/64.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
  14 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
  15
  16 #include "MipsISelLowering.h"
  17 #include "llvm/CodeGen/SelectionDAGNodes.h"
  18 #include "llvm/Support/MachineValueType.h"
  19
  20 namespace llvm {
  21
  22 class MachineBasicBlock;
  23 class MachineInstr;
  24 class MipsSubtarget;
  25 class MipsTargetMachine;
  26 class SelectionDAG;
  27 class TargetRegisterClass;
  28
  29   class MipsSETargetLowering : public MipsTargetLowering  {
  30   public:
  31     explicit MipsSETargetLowering(const MipsTargetMachine &TM,
  32                                   const MipsSubtarget &STI);
  33
  34     /// Enable MSA support for the given integer type and Register
  35     /// class.
  36     void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
  37
  38     /// Enable MSA support for the given floating-point type and
  39     /// Register class.
  40     void addMSAFloatType(MVT::SimpleValueType Ty,
  41                          const TargetRegisterClass *RC);
  42
  43     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0,
  44                                         unsigned Align = 1,
  45                                         bool *Fast = nullptr) const override;
  46
  47     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  48
  49     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
  50
  51     MachineBasicBlock *
  52     EmitInstrWithCustomInserter(MachineInstr &MI,
  53                                 MachineBasicBlock *MBB) const override;
  54
  55     bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
  56       return false;
  57     }
  58
  59     const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
  60
  61   private:
  62     bool isEligibleForTailCallOptimization(
  63         const CCState &CCInfo, unsigned NextStackOffset,
  64         const MipsFunctionInfo &FI) const override;
  65
  66     void
  67     getOpndList(SmallVectorImpl<SDValue> &Ops,
  68                 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
  69                 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
  70                 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
  71                 SDValue Chain) const override;
  72
  73     SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
  74     SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
  75
  76     SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
  77                         SelectionDAG &DAG) const;
  78
  79     SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  80     SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  81     SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
  82     SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
  83     SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
  84     /// Lower VECTOR_SHUFFLE into one of a number of instructions
  85     /// depending on the indices in the shuffle.
  86     SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
  87     SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
  88
  89     MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
  90                                     MachineBasicBlock *BB) const;
  91     MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
  92                                             MachineBasicBlock *BB,
  93                                             unsigned BranchOp) const;
  94     /// Emit the COPY_FW pseudo instruction
  95     MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
  96                                    MachineBasicBlock *BB) const;
  97     /// Emit the COPY_FD pseudo instruction
  98     MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
  99                                    MachineBasicBlock *BB) const;
 100     /// Emit the INSERT_FW pseudo instruction
 101     MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
 102                                      MachineBasicBlock *BB) const;
 103     /// Emit the INSERT_FD pseudo instruction
 104     MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
 105                                      MachineBasicBlock *BB) const;
 106     /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
 107     MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
 108                                           MachineBasicBlock *BB,
 109                                           unsigned EltSizeInBytes,
 110                                           bool IsFP) const;
 111     /// Emit the FILL_FW pseudo instruction
 112     MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
 113                                    MachineBasicBlock *BB) const;
 114     /// Emit the FILL_FD pseudo instruction
 115     MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
 116                                    MachineBasicBlock *BB) const;
 117     /// Emit the FEXP2_W_1 pseudo instructions.
 118     MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
 119                                      MachineBasicBlock *BB) const;
 120     /// Emit the FEXP2_D_1 pseudo instructions.
 121     MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
 122                                      MachineBasicBlock *BB) const;
 123     /// Emit the FILL_FW pseudo instruction
 124     MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
 125                                    MachineBasicBlock *BB) const;
 126     /// Emit the FILL_FD pseudo instruction
 127     MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
 128                                    MachineBasicBlock *BB) const;
 129     /// Emit the FEXP2_W_1 pseudo instructions.
 130     MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
 131                                            MachineBasicBlock *BB,
 132                                            bool IsFGR64) const;
 133     /// Emit the FEXP2_D_1 pseudo instructions.
 134     MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
 135                                           MachineBasicBlock *BBi,
 136                                           bool IsFGR64) const;
 137   };
 138
 139 } // end namespace llvm
 140
 141 #endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H