lib/Target/Sparc/SparcTargetMachine.cpp

   1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "SparcTargetMachine.h"
  13 #include "LeonPasses.h"
  14 #include "Sparc.h"
  15 #include "SparcTargetObjectFile.h"
  16 #include "llvm/CodeGen/Passes.h"
  17 #include "llvm/CodeGen/TargetPassConfig.h"
  18 #include "llvm/IR/LegacyPassManager.h"
  19 #include "llvm/Support/TargetRegistry.h"
  20 using namespace llvm;
  21
  22 extern "C" void LLVMInitializeSparcTarget() {
  23   // Register the target.
  24   RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
  25   RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
  26   RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
  27 }
  28
  29 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
  30   // Sparc is typically big endian, but some are little.
  31   std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
  32   Ret += "-m:e";
  33
  34   // Some ABIs have 32bit pointers.
  35   if (!is64Bit)
  36     Ret += "-p:32:32";
  37
  38   // Alignments for 64 bit integers.
  39   Ret += "-i64:64";
  40
  41   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
  42   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
  43   if (is64Bit)
  44     Ret += "-n32:64";
  45   else
  46     Ret += "-f128:64-n32";
  47
  48   if (is64Bit)
  49     Ret += "-S128";
  50   else
  51     Ret += "-S64";
  52
  53   return Ret;
  54 }
  55
  56 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
  57   if (!RM.hasValue())
  58     return Reloc::Static;
  59   return *RM;
  60 }
  61
  62 // Code models. Some only make sense for 64-bit code.
  63 //
  64 // SunCC  Reloc   CodeModel  Constraints
  65 // abs32  Static  Small      text+data+bss linked below 2^32 bytes
  66 // abs44  Static  Medium     text+data+bss linked below 2^44 bytes
  67 // abs64  Static  Large      text smaller than 2^31 bytes
  68 // pic13  PIC_    Small      GOT < 2^13 bytes
  69 // pic32  PIC_    Medium     GOT < 2^32 bytes
  70 //
  71 // All code models require that the text segment is smaller than 2GB.
  72 static CodeModel::Model
  73 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
  74                            bool Is64Bit, bool JIT) {
  75   if (CM) {
  76     if (*CM == CodeModel::Tiny)
  77       report_fatal_error("Target does not support the tiny CodeModel");
  78     if (*CM == CodeModel::Kernel)
  79       report_fatal_error("Target does not support the kernel CodeModel");
  80     return *CM;
  81   }
  82   if (Is64Bit) {
  83     if (JIT)
  84       return CodeModel::Large;
  85     return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
  86   }
  87   return CodeModel::Small;
  88 }
  89
  90 /// Create an ILP32 architecture model
  91 SparcTargetMachine::SparcTargetMachine(
  92     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
  93     const TargetOptions &Options, Optional<Reloc::Model> RM,
  94     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
  95     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
  96                         getEffectiveRelocModel(RM),
  97                         getEffectiveSparcCodeModel(
  98                             CM, getEffectiveRelocModel(RM), is64bit, JIT),
  99                         OL),
 100       TLOF(make_unique<SparcELFTargetObjectFile>()),
 101       Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
 102   initAsmInfo();
 103 }
 104
 105 SparcTargetMachine::~SparcTargetMachine() {}
 106
 107 const SparcSubtarget *
 108 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
 109   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 110   Attribute FSAttr = F.getFnAttribute("target-features");
 111
 112   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
 113                         ? CPUAttr.getValueAsString().str()
 114                         : TargetCPU;
 115   std::string FS = !FSAttr.hasAttribute(Attribute::None)
 116                        ? FSAttr.getValueAsString().str()
 117                        : TargetFS;
 118
 119   // FIXME: This is related to the code below to reset the target options,
 120   // we need to know whether or not the soft float flag is set on the
 121   // function, so we can enable it as a subtarget feature.
 122   bool softFloat =
 123       F.hasFnAttribute("use-soft-float") &&
 124       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
 125
 126   if (softFloat)
 127     FS += FS.empty() ? "+soft-float" : ",+soft-float";
 128
 129   auto &I = SubtargetMap[CPU + FS];
 130   if (!I) {
 131     // This needs to be done before we create a new subtarget since any
 132     // creation will depend on the TM and the code generation flags on the
 133     // function that reside in TargetOptions.
 134     resetTargetOptions(F);
 135     I = llvm::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
 136                                           this->is64Bit);
 137   }
 138   return I.get();
 139 }
 140
 141 namespace {
 142 /// Sparc Code Generator Pass Configuration Options.
 143 class SparcPassConfig : public TargetPassConfig {
 144 public:
 145   SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
 146     : TargetPassConfig(TM, PM) {}
 147
 148   SparcTargetMachine &getSparcTargetMachine() const {
 149     return getTM<SparcTargetMachine>();
 150   }
 151
 152   void addIRPasses() override;
 153   bool addInstSelector() override;
 154   void addPreEmitPass() override;
 155 };
 156 } // namespace
 157
 158 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
 159   return new SparcPassConfig(*this, PM);
 160 }
 161
 162 void SparcPassConfig::addIRPasses() {
 163   addPass(createAtomicExpandPass());
 164
 165   TargetPassConfig::addIRPasses();
 166 }
 167
 168 bool SparcPassConfig::addInstSelector() {
 169   addPass(createSparcISelDag(getSparcTargetMachine()));
 170   return false;
 171 }
 172
 173 void SparcPassConfig::addPreEmitPass(){
 174   addPass(createSparcDelaySlotFillerPass());
 175
 176   if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
 177   {
 178     addPass(new InsertNOPLoad());
 179   }
 180   if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
 181     addPass(new DetectRoundChange());
 182   }
 183   if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
 184   {
 185     addPass(new FixAllFDIVSQRT());
 186   }
 187 }
 188
 189 void SparcV8TargetMachine::anchor() { }
 190
 191 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
 192                                            StringRef CPU, StringRef FS,
 193                                            const TargetOptions &Options,
 194                                            Optional<Reloc::Model> RM,
 195                                            Optional<CodeModel::Model> CM,
 196                                            CodeGenOpt::Level OL, bool JIT)
 197     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
 198
 199 void SparcV9TargetMachine::anchor() { }
 200
 201 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
 202                                            StringRef CPU, StringRef FS,
 203                                            const TargetOptions &Options,
 204                                            Optional<Reloc::Model> RM,
 205                                            Optional<CodeModel::Model> CM,
 206                                            CodeGenOpt::Level OL, bool JIT)
 207     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
 208
 209 void SparcelTargetMachine::anchor() {}
 210
 211 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
 212                                            StringRef CPU, StringRef FS,
 213                                            const TargetOptions &Options,
 214                                            Optional<Reloc::Model> RM,
 215                                            Optional<CodeModel::Model> CM,
 216                                            CodeGenOpt::Level OL, bool JIT)
 217     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}