lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

   1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This file provides WebAssembly-specific target descriptions.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
  15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
  16
  17 #include "llvm/BinaryFormat/Wasm.h"
  18 #include "llvm/MC/MCInstrDesc.h"
  19 #include "llvm/Support/DataTypes.h"
  20 #include <memory>
  21
  22 namespace llvm {
  23
  24 class MCAsmBackend;
  25 class MCCodeEmitter;
  26 class MCContext;
  27 class MCInstrInfo;
  28 class MCObjectTargetWriter;
  29 class MCSubtargetInfo;
  30 class MVT;
  31 class Target;
  32 class Triple;
  33 class raw_pwrite_stream;
  34
  35 Target &getTheWebAssemblyTarget32();
  36 Target &getTheWebAssemblyTarget64();
  37
  38 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
  39
  40 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
  41
  42 std::unique_ptr<MCObjectTargetWriter>
  43 createWebAssemblyWasmObjectWriter(bool Is64Bit);
  44
  45 namespace WebAssembly {
  46 enum OperandType {
  47   /// Basic block label in a branch construct.
  48   OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
  49   /// Local index.
  50   OPERAND_LOCAL,
  51   /// Global index.
  52   OPERAND_GLOBAL,
  53   /// 32-bit integer immediates.
  54   OPERAND_I32IMM,
  55   /// 64-bit integer immediates.
  56   OPERAND_I64IMM,
  57   /// 32-bit floating-point immediates.
  58   OPERAND_F32IMM,
  59   /// 64-bit floating-point immediates.
  60   OPERAND_F64IMM,
  61   /// 8-bit vector lane immediate
  62   OPERAND_VEC_I8IMM,
  63   /// 16-bit vector lane immediate
  64   OPERAND_VEC_I16IMM,
  65   /// 32-bit vector lane immediate
  66   OPERAND_VEC_I32IMM,
  67   /// 64-bit vector lane immediate
  68   OPERAND_VEC_I64IMM,
  69   /// 32-bit unsigned function indices.
  70   OPERAND_FUNCTION32,
  71   /// 32-bit unsigned memory offsets.
  72   OPERAND_OFFSET32,
  73   /// p2align immediate for load and store address alignment.
  74   OPERAND_P2ALIGN,
  75   /// signature immediate for block/loop.
  76   OPERAND_SIGNATURE,
  77   /// type signature immediate for call_indirect.
  78   OPERAND_TYPEINDEX,
  79   /// Event index.
  80   OPERAND_EVENT,
  81   /// A list of branch targets for br_list.
  82   OPERAND_BRLIST,
  83 };
  84 } // end namespace WebAssembly
  85
  86 namespace WebAssemblyII {
  87
  88 /// Target Operand Flag enum.
  89 enum TOF {
  90   MO_NO_FLAG = 0,
  91
  92   // Flags to indicate the type of the symbol being referenced
  93   MO_SYMBOL_FUNCTION = 0x1,
  94   MO_SYMBOL_GLOBAL = 0x2,
  95   MO_SYMBOL_EVENT = 0x4,
  96   MO_SYMBOL_MASK = 0x7,
  97 };
  98 } // end namespace WebAssemblyII
  99
 100 } // end namespace llvm
 101
 102 // Defines symbolic names for WebAssembly registers. This defines a mapping from
 103 // register name to register number.
 104 //
 105 #define GET_REGINFO_ENUM
 106 #include "WebAssemblyGenRegisterInfo.inc"
 107
 108 // Defines symbolic names for the WebAssembly instructions.
 109 //
 110 #define GET_INSTRINFO_ENUM
 111 #include "WebAssemblyGenInstrInfo.inc"
 112
 113 #define GET_SUBTARGETINFO_ENUM
 114 #include "WebAssemblyGenSubtargetInfo.inc"
 115
 116 namespace llvm {
 117 namespace WebAssembly {
 118
 119 /// Return the default p2align value for a load or store with the given opcode.
 120 inline unsigned GetDefaultP2Align(unsigned Opcode) {
 121   switch (Opcode) {
 122   case WebAssembly::LOAD8_S_I32:
 123   case WebAssembly::LOAD8_S_I32_S:
 124   case WebAssembly::LOAD8_U_I32:
 125   case WebAssembly::LOAD8_U_I32_S:
 126   case WebAssembly::LOAD8_S_I64:
 127   case WebAssembly::LOAD8_S_I64_S:
 128   case WebAssembly::LOAD8_U_I64:
 129   case WebAssembly::LOAD8_U_I64_S:
 130   case WebAssembly::ATOMIC_LOAD8_U_I32:
 131   case WebAssembly::ATOMIC_LOAD8_U_I32_S:
 132   case WebAssembly::ATOMIC_LOAD8_U_I64:
 133   case WebAssembly::ATOMIC_LOAD8_U_I64_S:
 134   case WebAssembly::STORE8_I32:
 135   case WebAssembly::STORE8_I32_S:
 136   case WebAssembly::STORE8_I64:
 137   case WebAssembly::STORE8_I64_S:
 138   case WebAssembly::ATOMIC_STORE8_I32:
 139   case WebAssembly::ATOMIC_STORE8_I32_S:
 140   case WebAssembly::ATOMIC_STORE8_I64:
 141   case WebAssembly::ATOMIC_STORE8_I64_S:
 142   case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
 143   case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
 144   case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
 145   case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
 146   case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
 147   case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
 148   case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
 149   case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
 150   case WebAssembly::ATOMIC_RMW8_U_AND_I32:
 151   case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
 152   case WebAssembly::ATOMIC_RMW8_U_AND_I64:
 153   case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
 154   case WebAssembly::ATOMIC_RMW8_U_OR_I32:
 155   case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
 156   case WebAssembly::ATOMIC_RMW8_U_OR_I64:
 157   case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
 158   case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
 159   case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
 160   case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
 161   case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
 162   case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
 163   case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
 164   case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
 165   case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
 166   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
 167   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
 168   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
 169   case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
 170     return 0;
 171   case WebAssembly::LOAD16_S_I32:
 172   case WebAssembly::LOAD16_S_I32_S:
 173   case WebAssembly::LOAD16_U_I32:
 174   case WebAssembly::LOAD16_U_I32_S:
 175   case WebAssembly::LOAD16_S_I64:
 176   case WebAssembly::LOAD16_S_I64_S:
 177   case WebAssembly::LOAD16_U_I64:
 178   case WebAssembly::LOAD16_U_I64_S:
 179   case WebAssembly::ATOMIC_LOAD16_U_I32:
 180   case WebAssembly::ATOMIC_LOAD16_U_I32_S:
 181   case WebAssembly::ATOMIC_LOAD16_U_I64:
 182   case WebAssembly::ATOMIC_LOAD16_U_I64_S:
 183   case WebAssembly::STORE16_I32:
 184   case WebAssembly::STORE16_I32_S:
 185   case WebAssembly::STORE16_I64:
 186   case WebAssembly::STORE16_I64_S:
 187   case WebAssembly::ATOMIC_STORE16_I32:
 188   case WebAssembly::ATOMIC_STORE16_I32_S:
 189   case WebAssembly::ATOMIC_STORE16_I64:
 190   case WebAssembly::ATOMIC_STORE16_I64_S:
 191   case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
 192   case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
 193   case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
 194   case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
 195   case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
 196   case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
 197   case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
 198   case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
 199   case WebAssembly::ATOMIC_RMW16_U_AND_I32:
 200   case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
 201   case WebAssembly::ATOMIC_RMW16_U_AND_I64:
 202   case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
 203   case WebAssembly::ATOMIC_RMW16_U_OR_I32:
 204   case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
 205   case WebAssembly::ATOMIC_RMW16_U_OR_I64:
 206   case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
 207   case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
 208   case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
 209   case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
 210   case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
 211   case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
 212   case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
 213   case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
 214   case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
 215   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
 216   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
 217   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
 218   case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
 219     return 1;
 220   case WebAssembly::LOAD_I32:
 221   case WebAssembly::LOAD_I32_S:
 222   case WebAssembly::LOAD_F32:
 223   case WebAssembly::LOAD_F32_S:
 224   case WebAssembly::STORE_I32:
 225   case WebAssembly::STORE_I32_S:
 226   case WebAssembly::STORE_F32:
 227   case WebAssembly::STORE_F32_S:
 228   case WebAssembly::LOAD32_S_I64:
 229   case WebAssembly::LOAD32_S_I64_S:
 230   case WebAssembly::LOAD32_U_I64:
 231   case WebAssembly::LOAD32_U_I64_S:
 232   case WebAssembly::STORE32_I64:
 233   case WebAssembly::STORE32_I64_S:
 234   case WebAssembly::ATOMIC_LOAD_I32:
 235   case WebAssembly::ATOMIC_LOAD_I32_S:
 236   case WebAssembly::ATOMIC_LOAD32_U_I64:
 237   case WebAssembly::ATOMIC_LOAD32_U_I64_S:
 238   case WebAssembly::ATOMIC_STORE_I32:
 239   case WebAssembly::ATOMIC_STORE_I32_S:
 240   case WebAssembly::ATOMIC_STORE32_I64:
 241   case WebAssembly::ATOMIC_STORE32_I64_S:
 242   case WebAssembly::ATOMIC_RMW_ADD_I32:
 243   case WebAssembly::ATOMIC_RMW_ADD_I32_S:
 244   case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
 245   case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
 246   case WebAssembly::ATOMIC_RMW_SUB_I32:
 247   case WebAssembly::ATOMIC_RMW_SUB_I32_S:
 248   case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
 249   case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
 250   case WebAssembly::ATOMIC_RMW_AND_I32:
 251   case WebAssembly::ATOMIC_RMW_AND_I32_S:
 252   case WebAssembly::ATOMIC_RMW32_U_AND_I64:
 253   case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
 254   case WebAssembly::ATOMIC_RMW_OR_I32:
 255   case WebAssembly::ATOMIC_RMW_OR_I32_S:
 256   case WebAssembly::ATOMIC_RMW32_U_OR_I64:
 257   case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
 258   case WebAssembly::ATOMIC_RMW_XOR_I32:
 259   case WebAssembly::ATOMIC_RMW_XOR_I32_S:
 260   case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
 261   case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
 262   case WebAssembly::ATOMIC_RMW_XCHG_I32:
 263   case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
 264   case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
 265   case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
 266   case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
 267   case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
 268   case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
 269   case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
 270   case WebAssembly::ATOMIC_NOTIFY:
 271   case WebAssembly::ATOMIC_NOTIFY_S:
 272   case WebAssembly::ATOMIC_WAIT_I32:
 273   case WebAssembly::ATOMIC_WAIT_I32_S:
 274     return 2;
 275   case WebAssembly::LOAD_I64:
 276   case WebAssembly::LOAD_I64_S:
 277   case WebAssembly::LOAD_F64:
 278   case WebAssembly::LOAD_F64_S:
 279   case WebAssembly::STORE_I64:
 280   case WebAssembly::STORE_I64_S:
 281   case WebAssembly::STORE_F64:
 282   case WebAssembly::STORE_F64_S:
 283   case WebAssembly::ATOMIC_LOAD_I64:
 284   case WebAssembly::ATOMIC_LOAD_I64_S:
 285   case WebAssembly::ATOMIC_STORE_I64:
 286   case WebAssembly::ATOMIC_STORE_I64_S:
 287   case WebAssembly::ATOMIC_RMW_ADD_I64:
 288   case WebAssembly::ATOMIC_RMW_ADD_I64_S:
 289   case WebAssembly::ATOMIC_RMW_SUB_I64:
 290   case WebAssembly::ATOMIC_RMW_SUB_I64_S:
 291   case WebAssembly::ATOMIC_RMW_AND_I64:
 292   case WebAssembly::ATOMIC_RMW_AND_I64_S:
 293   case WebAssembly::ATOMIC_RMW_OR_I64:
 294   case WebAssembly::ATOMIC_RMW_OR_I64_S:
 295   case WebAssembly::ATOMIC_RMW_XOR_I64:
 296   case WebAssembly::ATOMIC_RMW_XOR_I64_S:
 297   case WebAssembly::ATOMIC_RMW_XCHG_I64:
 298   case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
 299   case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
 300   case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
 301   case WebAssembly::ATOMIC_WAIT_I64:
 302   case WebAssembly::ATOMIC_WAIT_I64_S:
 303     return 3;
 304   case WebAssembly::LOAD_v16i8:
 305   case WebAssembly::LOAD_v16i8_S:
 306   case WebAssembly::LOAD_v8i16:
 307   case WebAssembly::LOAD_v8i16_S:
 308   case WebAssembly::LOAD_v4i32:
 309   case WebAssembly::LOAD_v4i32_S:
 310   case WebAssembly::LOAD_v2i64:
 311   case WebAssembly::LOAD_v2i64_S:
 312   case WebAssembly::LOAD_v4f32:
 313   case WebAssembly::LOAD_v4f32_S:
 314   case WebAssembly::LOAD_v2f64:
 315   case WebAssembly::LOAD_v2f64_S:
 316   case WebAssembly::STORE_v16i8:
 317   case WebAssembly::STORE_v16i8_S:
 318   case WebAssembly::STORE_v8i16:
 319   case WebAssembly::STORE_v8i16_S:
 320   case WebAssembly::STORE_v4i32:
 321   case WebAssembly::STORE_v4i32_S:
 322   case WebAssembly::STORE_v2i64:
 323   case WebAssembly::STORE_v2i64_S:
 324   case WebAssembly::STORE_v4f32:
 325   case WebAssembly::STORE_v4f32_S:
 326   case WebAssembly::STORE_v2f64:
 327   case WebAssembly::STORE_v2f64_S:
 328     return 4;
 329   default:
 330     llvm_unreachable("Only loads and stores have p2align values");
 331   }
 332 }
 333
 334 /// The operand number of the load or store address in load/store instructions.
 335 static const unsigned LoadAddressOperandNo = 3;
 336 static const unsigned StoreAddressOperandNo = 2;
 337
 338 /// The operand number of the load or store p2align in load/store instructions.
 339 static const unsigned LoadP2AlignOperandNo = 1;
 340 static const unsigned StoreP2AlignOperandNo = 0;
 341
 342 /// This is used to indicate block signatures.
 343 enum class ExprType : unsigned {
 344   Void = 0x40,
 345   I32 = 0x7F,
 346   I64 = 0x7E,
 347   F32 = 0x7D,
 348   F64 = 0x7C,
 349   V128 = 0x7B,
 350   ExceptRef = 0x68,
 351   Invalid = 0x00
 352 };
 353
 354 /// Instruction opcodes emitted via means other than CodeGen.
 355 static const unsigned Nop = 0x01;
 356 static const unsigned End = 0x0b;
 357
 358 wasm::ValType toValType(const MVT &Ty);
 359
 360 } // end namespace WebAssembly
 361 } // end namespace llvm
 362
 363 #endif