lib/Target/X86/MCTargetDesc/X86BaseInfo.h

   1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains small standalone helper functions and enum definitions for
  10 // the X86 target useful for the compiler back-end and the MC libraries.
  11 // As such, it deliberately does not include references to LLVM core
  12 // code gen types, passes, etc..
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
  17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
  18
  19 #include "X86MCTargetDesc.h"
  20 #include "llvm/MC/MCInstrDesc.h"
  21 #include "llvm/Support/DataTypes.h"
  22 #include "llvm/Support/ErrorHandling.h"
  23
  24 namespace llvm {
  25
  26 namespace X86 {
  27   // Enums for memory operand decoding.  Each memory operand is represented with
  28   // a 5 operand sequence in the form:
  29   //   [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
  30   // These enums help decode this.
  31   enum {
  32     AddrBaseReg = 0,
  33     AddrScaleAmt = 1,
  34     AddrIndexReg = 2,
  35     AddrDisp = 3,
  36
  37     /// AddrSegmentReg - The operand # of the segment in the memory operand.
  38     AddrSegmentReg = 4,
  39
  40     /// AddrNumOperands - Total number of operands in a memory reference.
  41     AddrNumOperands = 5
  42   };
  43
  44   /// AVX512 static rounding constants.  These need to match the values in
  45   /// avx512fintrin.h.
  46   enum STATIC_ROUNDING {
  47     TO_NEAREST_INT = 0,
  48     TO_NEG_INF = 1,
  49     TO_POS_INF = 2,
  50     TO_ZERO = 3,
  51     CUR_DIRECTION = 4
  52   };
  53
  54   /// The constants to describe instr prefixes if there are
  55   enum IPREFIXES {
  56     IP_NO_PREFIX = 0,
  57     IP_HAS_OP_SIZE = 1,
  58     IP_HAS_AD_SIZE = 2,
  59     IP_HAS_REPEAT_NE = 4,
  60     IP_HAS_REPEAT = 8,
  61     IP_HAS_LOCK = 16,
  62     IP_HAS_NOTRACK = 32
  63   };
  64 } // end namespace X86;
  65
  66 /// X86II - This namespace holds all of the target specific flags that
  67 /// instruction info tracks.
  68 ///
  69 namespace X86II {
  70   /// Target Operand Flag enum.
  71   enum TOF {
  72     //===------------------------------------------------------------------===//
  73     // X86 Specific MachineOperand flags.
  74
  75     MO_NO_FLAG,
  76
  77     /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
  78     /// relocation of:
  79     ///    SYMBOL_LABEL + [. - PICBASELABEL]
  80     MO_GOT_ABSOLUTE_ADDRESS,
  81
  82     /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
  83     /// immediate should get the value of the symbol minus the PIC base label:
  84     ///    SYMBOL_LABEL - PICBASELABEL
  85     MO_PIC_BASE_OFFSET,
  86
  87     /// MO_GOT - On a symbol operand this indicates that the immediate is the
  88     /// offset to the GOT entry for the symbol name from the base of the GOT.
  89     ///
  90     /// See the X86-64 ELF ABI supplement for more details.
  91     ///    SYMBOL_LABEL @GOT
  92     MO_GOT,
  93
  94     /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
  95     /// the offset to the location of the symbol name from the base of the GOT.
  96     ///
  97     /// See the X86-64 ELF ABI supplement for more details.
  98     ///    SYMBOL_LABEL @GOTOFF
  99     MO_GOTOFF,
 100
 101     /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
 102     /// offset to the GOT entry for the symbol name from the current code
 103     /// location.
 104     ///
 105     /// See the X86-64 ELF ABI supplement for more details.
 106     ///    SYMBOL_LABEL @GOTPCREL
 107     MO_GOTPCREL,
 108
 109     /// MO_PLT - On a symbol operand this indicates that the immediate is
 110     /// offset to the PLT entry of symbol name from the current code location.
 111     ///
 112     /// See the X86-64 ELF ABI supplement for more details.
 113     ///    SYMBOL_LABEL @PLT
 114     MO_PLT,
 115
 116     /// MO_TLSGD - On a symbol operand this indicates that the immediate is
 117     /// the offset of the GOT entry with the TLS index structure that contains
 118     /// the module number and variable offset for the symbol. Used in the
 119     /// general dynamic TLS access model.
 120     ///
 121     /// See 'ELF Handling for Thread-Local Storage' for more details.
 122     ///    SYMBOL_LABEL @TLSGD
 123     MO_TLSGD,
 124
 125     /// MO_TLSLD - On a symbol operand this indicates that the immediate is
 126     /// the offset of the GOT entry with the TLS index for the module that
 127     /// contains the symbol. When this index is passed to a call to
 128     /// __tls_get_addr, the function will return the base address of the TLS
 129     /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
 130     ///
 131     /// See 'ELF Handling for Thread-Local Storage' for more details.
 132     ///    SYMBOL_LABEL @TLSLD
 133     MO_TLSLD,
 134
 135     /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
 136     /// the offset of the GOT entry with the TLS index for the module that
 137     /// contains the symbol. When this index is passed to a call to
 138     /// ___tls_get_addr, the function will return the base address of the TLS
 139     /// block for the symbol. Used in the IA32 local dynamic TLS access model.
 140     ///
 141     /// See 'ELF Handling for Thread-Local Storage' for more details.
 142     ///    SYMBOL_LABEL @TLSLDM
 143     MO_TLSLDM,
 144
 145     /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
 146     /// the offset of the GOT entry with the thread-pointer offset for the
 147     /// symbol. Used in the x86-64 initial exec TLS access model.
 148     ///
 149     /// See 'ELF Handling for Thread-Local Storage' for more details.
 150     ///    SYMBOL_LABEL @GOTTPOFF
 151     MO_GOTTPOFF,
 152
 153     /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
 154     /// the absolute address of the GOT entry with the negative thread-pointer
 155     /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
 156     /// model.
 157     ///
 158     /// See 'ELF Handling for Thread-Local Storage' for more details.
 159     ///    SYMBOL_LABEL @INDNTPOFF
 160     MO_INDNTPOFF,
 161
 162     /// MO_TPOFF - On a symbol operand this indicates that the immediate is
 163     /// the thread-pointer offset for the symbol. Used in the x86-64 local
 164     /// exec TLS access model.
 165     ///
 166     /// See 'ELF Handling for Thread-Local Storage' for more details.
 167     ///    SYMBOL_LABEL @TPOFF
 168     MO_TPOFF,
 169
 170     /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
 171     /// the offset of the GOT entry with the TLS offset of the symbol. Used
 172     /// in the local dynamic TLS access model.
 173     ///
 174     /// See 'ELF Handling for Thread-Local Storage' for more details.
 175     ///    SYMBOL_LABEL @DTPOFF
 176     MO_DTPOFF,
 177
 178     /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
 179     /// the negative thread-pointer offset for the symbol. Used in the IA32
 180     /// local exec TLS access model.
 181     ///
 182     /// See 'ELF Handling for Thread-Local Storage' for more details.
 183     ///    SYMBOL_LABEL @NTPOFF
 184     MO_NTPOFF,
 185
 186     /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
 187     /// the offset of the GOT entry with the negative thread-pointer offset for
 188     /// the symbol. Used in the PIC IA32 initial exec TLS access model.
 189     ///
 190     /// See 'ELF Handling for Thread-Local Storage' for more details.
 191     ///    SYMBOL_LABEL @GOTNTPOFF
 192     MO_GOTNTPOFF,
 193
 194     /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
 195     /// reference is actually to the "__imp_FOO" symbol.  This is used for
 196     /// dllimport linkage on windows.
 197     MO_DLLIMPORT,
 198
 199     /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
 200     /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
 201     /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 202     MO_DARWIN_NONLAZY,
 203
 204     /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
 205     /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
 206     /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 207     MO_DARWIN_NONLAZY_PIC_BASE,
 208
 209     /// MO_TLVP - On a symbol operand this indicates that the immediate is
 210     /// some TLS offset.
 211     ///
 212     /// This is the TLS offset for the Darwin TLS mechanism.
 213     MO_TLVP,
 214
 215     /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
 216     /// is some TLS offset from the picbase.
 217     ///
 218     /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
 219     MO_TLVP_PIC_BASE,
 220
 221     /// MO_SECREL - On a symbol operand this indicates that the immediate is
 222     /// the offset from beginning of section.
 223     ///
 224     /// This is the TLS offset for the COFF/Windows TLS mechanism.
 225     MO_SECREL,
 226
 227     /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
 228     /// to be an absolute symbol in range [0,128), so we can use the @ABS8
 229     /// symbol modifier.
 230     MO_ABS8,
 231
 232     /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
 233     /// reference is actually to the ".refptr.FOO" symbol.  This is used for
 234     /// stub symbols on windows.
 235     MO_COFFSTUB,
 236   };
 237
 238   enum : uint64_t {
 239     //===------------------------------------------------------------------===//
 240     // Instruction encodings.  These are the standard/most common forms for X86
 241     // instructions.
 242     //
 243
 244     // PseudoFrm - This represents an instruction that is a pseudo instruction
 245     // or one that has not been implemented yet.  It is illegal to code generate
 246     // it, but tolerated for intermediate implementation stages.
 247     Pseudo         = 0,
 248
 249     /// Raw - This form is for instructions that don't have any operands, so
 250     /// they are just a fixed opcode value, like 'leave'.
 251     RawFrm         = 1,
 252
 253     /// AddRegFrm - This form is used for instructions like 'push r32' that have
 254     /// their one register operand added to their opcode.
 255     AddRegFrm      = 2,
 256
 257     /// RawFrmMemOffs - This form is for instructions that store an absolute
 258     /// memory offset as an immediate with a possible segment override.
 259     RawFrmMemOffs  = 3,
 260
 261     /// RawFrmSrc - This form is for instructions that use the source index
 262     /// register SI/ESI/RSI with a possible segment override.
 263     RawFrmSrc      = 4,
 264
 265     /// RawFrmDst - This form is for instructions that use the destination index
 266     /// register DI/EDI/RDI.
 267     RawFrmDst      = 5,
 268
 269     /// RawFrmDstSrc - This form is for instructions that use the source index
 270     /// register SI/ESI/RSI with a possible segment override, and also the
 271     /// destination index register DI/EDI/RDI.
 272     RawFrmDstSrc   = 6,
 273
 274     /// RawFrmImm8 - This is used for the ENTER instruction, which has two
 275     /// immediates, the first of which is a 16-bit immediate (specified by
 276     /// the imm encoding) and the second is a 8-bit fixed value.
 277     RawFrmImm8 = 7,
 278
 279     /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
 280     /// immediates, the first of which is a 16 or 32-bit immediate (specified by
 281     /// the imm encoding) and the second is a 16-bit fixed value.  In the AMD
 282     /// manual, this operand is described as pntr16:32 and pntr16:16
 283     RawFrmImm16 = 8,
 284
 285     /// MRM[0-7][rm] - These forms are used to represent instructions that use
 286     /// a Mod/RM byte, and use the middle field to hold extended opcode
 287     /// information.  In the intel manual these are represented as /0, /1, ...
 288     ///
 289
 290     /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
 291     /// to specify a destination, which in this case is memory.
 292     ///
 293     MRMDestMem     = 32,
 294
 295     /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
 296     /// to specify a source, which in this case is memory.
 297     ///
 298     MRMSrcMem      = 33,
 299
 300     /// MRMSrcMem4VOp3 - This form is used for instructions that encode
 301     /// operand 3 with VEX.VVVV and load from memory.
 302     ///
 303     MRMSrcMem4VOp3 = 34,
 304
 305     /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
 306     /// byte to specify the fourth source, which in this case is memory.
 307     ///
 308     MRMSrcMemOp4   = 35,
 309
 310     /// MRMXm - This form is used for instructions that use the Mod/RM byte
 311     /// to specify a memory source, but doesn't use the middle field.
 312     ///
 313     MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
 314
 315     // Next, instructions that operate on a memory r/m operand...
 316     MRM0m = 40,  MRM1m = 41,  MRM2m = 42,  MRM3m = 43, // Format /0 /1 /2 /3
 317     MRM4m = 44,  MRM5m = 45,  MRM6m = 46,  MRM7m = 47, // Format /4 /5 /6 /7
 318
 319     /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
 320     /// to specify a destination, which in this case is a register.
 321     ///
 322     MRMDestReg     = 48,
 323
 324     /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
 325     /// to specify a source, which in this case is a register.
 326     ///
 327     MRMSrcReg      = 49,
 328
 329     /// MRMSrcReg4VOp3 - This form is used for instructions that encode
 330     /// operand 3 with VEX.VVVV and do not load from memory.
 331     ///
 332     MRMSrcReg4VOp3 = 50,
 333
 334     /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
 335     /// byte to specify the fourth source, which in this case is a register.
 336     ///
 337     MRMSrcRegOp4   = 51,
 338
 339     /// MRMXr - This form is used for instructions that use the Mod/RM byte
 340     /// to specify a register source, but doesn't use the middle field.
 341     ///
 342     MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
 343
 344     // Instructions that operate on a register r/m operand...
 345     MRM0r = 56,  MRM1r = 57,  MRM2r = 58,  MRM3r = 59, // Format /0 /1 /2 /3
 346     MRM4r = 60,  MRM5r = 61,  MRM6r = 62,  MRM7r = 63, // Format /4 /5 /6 /7
 347
 348     /// MRM_XX - A mod/rm byte of exactly 0xXX.
 349     MRM_C0 = 64,  MRM_C1 = 65,  MRM_C2 = 66,  MRM_C3 = 67,
 350     MRM_C4 = 68,  MRM_C5 = 69,  MRM_C6 = 70,  MRM_C7 = 71,
 351     MRM_C8 = 72,  MRM_C9 = 73,  MRM_CA = 74,  MRM_CB = 75,
 352     MRM_CC = 76,  MRM_CD = 77,  MRM_CE = 78,  MRM_CF = 79,
 353     MRM_D0 = 80,  MRM_D1 = 81,  MRM_D2 = 82,  MRM_D3 = 83,
 354     MRM_D4 = 84,  MRM_D5 = 85,  MRM_D6 = 86,  MRM_D7 = 87,
 355     MRM_D8 = 88,  MRM_D9 = 89,  MRM_DA = 90,  MRM_DB = 91,
 356     MRM_DC = 92,  MRM_DD = 93,  MRM_DE = 94,  MRM_DF = 95,
 357     MRM_E0 = 96,  MRM_E1 = 97,  MRM_E2 = 98,  MRM_E3 = 99,
 358     MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
 359     MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
 360     MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
 361     MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
 362     MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
 363     MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
 364     MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
 365
 366     FormMask       = 127,
 367
 368     //===------------------------------------------------------------------===//
 369     // Actual flags...
 370
 371     // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
 372     // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
 373     // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
 374     // prefix in 16-bit mode.
 375     OpSizeShift = 7,
 376     OpSizeMask = 0x3 << OpSizeShift,
 377
 378     OpSizeFixed  = 0 << OpSizeShift,
 379     OpSize16     = 1 << OpSizeShift,
 380     OpSize32     = 2 << OpSizeShift,
 381
 382     // AsSize - AdSizeX implies this instruction determines its need of 0x67
 383     // prefix from a normal ModRM memory operand. The other types indicate that
 384     // an operand is encoded with a specific width and a prefix is needed if
 385     // it differs from the current mode.
 386     AdSizeShift = OpSizeShift + 2,
 387     AdSizeMask  = 0x3 << AdSizeShift,
 388
 389     AdSizeX  = 0 << AdSizeShift,
 390     AdSize16 = 1 << AdSizeShift,
 391     AdSize32 = 2 << AdSizeShift,
 392     AdSize64 = 3 << AdSizeShift,
 393
 394     //===------------------------------------------------------------------===//
 395     // OpPrefix - There are several prefix bytes that are used as opcode
 396     // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
 397     // no prefix.
 398     //
 399     OpPrefixShift = AdSizeShift + 2,
 400     OpPrefixMask  = 0x3 << OpPrefixShift,
 401
 402     // PD - Prefix code for packed double precision vector floating point
 403     // operations performed in the SSE registers.
 404     PD = 1 << OpPrefixShift,
 405
 406     // XS, XD - These prefix codes are for single and double precision scalar
 407     // floating point operations performed in the SSE registers.
 408     XS = 2 << OpPrefixShift,  XD = 3 << OpPrefixShift,
 409
 410     //===------------------------------------------------------------------===//
 411     // OpMap - This field determines which opcode map this instruction
 412     // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
 413     //
 414     OpMapShift = OpPrefixShift + 2,
 415     OpMapMask  = 0x7 << OpMapShift,
 416
 417     // OB - OneByte - Set if this instruction has a one byte opcode.
 418     OB = 0 << OpMapShift,
 419
 420     // TB - TwoByte - Set if this instruction has a two byte opcode, which
 421     // starts with a 0x0F byte before the real opcode.
 422     TB = 1 << OpMapShift,
 423
 424     // T8, TA - Prefix after the 0x0F prefix.
 425     T8 = 2 << OpMapShift,  TA = 3 << OpMapShift,
 426
 427     // XOP8 - Prefix to include use of imm byte.
 428     XOP8 = 4 << OpMapShift,
 429
 430     // XOP9 - Prefix to exclude use of imm byte.
 431     XOP9 = 5 << OpMapShift,
 432
 433     // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
 434     XOPA = 6 << OpMapShift,
 435
 436     /// ThreeDNow - This indicates that the instruction uses the
 437     /// wacky 0x0F 0x0F prefix for 3DNow! instructions.  The manual documents
 438     /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
 439     /// storing a classifier in the imm8 field.  To simplify our implementation,
 440     /// we handle this by storeing the classifier in the opcode field and using
 441     /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
 442     ThreeDNow = 7 << OpMapShift,
 443
 444     //===------------------------------------------------------------------===//
 445     // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
 446     // They are used to specify GPRs and SSE registers, 64-bit operand size,
 447     // etc. We only cares about REX.W and REX.R bits and only the former is
 448     // statically determined.
 449     //
 450     REXShift    = OpMapShift + 3,
 451     REX_W       = 1 << REXShift,
 452
 453     //===------------------------------------------------------------------===//
 454     // This three-bit field describes the size of an immediate operand.  Zero is
 455     // unused so that we can tell if we forgot to set a value.
 456     ImmShift = REXShift + 1,
 457     ImmMask    = 15 << ImmShift,
 458     Imm8       = 1 << ImmShift,
 459     Imm8PCRel  = 2 << ImmShift,
 460     Imm8Reg    = 3 << ImmShift,
 461     Imm16      = 4 << ImmShift,
 462     Imm16PCRel = 5 << ImmShift,
 463     Imm32      = 6 << ImmShift,
 464     Imm32PCRel = 7 << ImmShift,
 465     Imm32S     = 8 << ImmShift,
 466     Imm64      = 9 << ImmShift,
 467
 468     //===------------------------------------------------------------------===//
 469     // FP Instruction Classification...  Zero is non-fp instruction.
 470
 471     // FPTypeMask - Mask for all of the FP types...
 472     FPTypeShift = ImmShift + 4,
 473     FPTypeMask  = 7 << FPTypeShift,
 474
 475     // NotFP - The default, set for instructions that do not use FP registers.
 476     NotFP      = 0 << FPTypeShift,
 477
 478     // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
 479     ZeroArgFP  = 1 << FPTypeShift,
 480
 481     // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
 482     OneArgFP   = 2 << FPTypeShift,
 483
 484     // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
 485     // result back to ST(0).  For example, fcos, fsqrt, etc.
 486     //
 487     OneArgFPRW = 3 << FPTypeShift,
 488
 489     // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
 490     // explicit argument, storing the result to either ST(0) or the implicit
 491     // argument.  For example: fadd, fsub, fmul, etc...
 492     TwoArgFP   = 4 << FPTypeShift,
 493
 494     // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
 495     // explicit argument, but have no destination.  Example: fucom, fucomi, ...
 496     CompareFP  = 5 << FPTypeShift,
 497
 498     // CondMovFP - "2 operand" floating point conditional move instructions.
 499     CondMovFP  = 6 << FPTypeShift,
 500
 501     // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
 502     SpecialFP  = 7 << FPTypeShift,
 503
 504     // Lock prefix
 505     LOCKShift = FPTypeShift + 3,
 506     LOCK = 1 << LOCKShift,
 507
 508     // REP prefix
 509     REPShift = LOCKShift + 1,
 510     REP = 1 << REPShift,
 511
 512     // Execution domain for SSE instructions.
 513     // 0 means normal, non-SSE instruction.
 514     SSEDomainShift = REPShift + 1,
 515
 516     // Encoding
 517     EncodingShift = SSEDomainShift + 2,
 518     EncodingMask = 0x3 << EncodingShift,
 519
 520     // VEX - encoding using 0xC4/0xC5
 521     VEX = 1 << EncodingShift,
 522
 523     /// XOP - Opcode prefix used by XOP instructions.
 524     XOP = 2 << EncodingShift,
 525
 526     // VEX_EVEX - Specifies that this instruction use EVEX form which provides
 527     // syntax support up to 32 512-bit register operands and up to 7 16-bit
 528     // mask operands as well as source operand data swizzling/memory operand
 529     // conversion, eviction hint, and rounding mode.
 530     EVEX = 3 << EncodingShift,
 531
 532     // Opcode
 533     OpcodeShift   = EncodingShift + 2,
 534
 535     /// VEX_W - Has a opcode specific functionality, but is used in the same
 536     /// way as REX_W is for regular SSE instructions.
 537     VEX_WShift  = OpcodeShift + 8,
 538     VEX_W       = 1ULL << VEX_WShift,
 539
 540     /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
 541     /// address instructions in SSE are represented as 3 address ones in AVX
 542     /// and the additional register is encoded in VEX_VVVV prefix.
 543     VEX_4VShift = VEX_WShift + 1,
 544     VEX_4V      = 1ULL << VEX_4VShift,
 545
 546     /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
 547     /// instruction uses 256-bit wide registers. This is usually auto detected
 548     /// if a VR256 register is used, but some AVX instructions also have this
 549     /// field marked when using a f256 memory references.
 550     VEX_LShift = VEX_4VShift + 1,
 551     VEX_L       = 1ULL << VEX_LShift,
 552
 553     // EVEX_K - Set if this instruction requires masking
 554     EVEX_KShift = VEX_LShift + 1,
 555     EVEX_K      = 1ULL << EVEX_KShift,
 556
 557     // EVEX_Z - Set if this instruction has EVEX.Z field set.
 558     EVEX_ZShift = EVEX_KShift + 1,
 559     EVEX_Z      = 1ULL << EVEX_ZShift,
 560
 561     // EVEX_L2 - Set if this instruction has EVEX.L' field set.
 562     EVEX_L2Shift = EVEX_ZShift + 1,
 563     EVEX_L2     = 1ULL << EVEX_L2Shift,
 564
 565     // EVEX_B - Set if this instruction has EVEX.B field set.
 566     EVEX_BShift = EVEX_L2Shift + 1,
 567     EVEX_B      = 1ULL << EVEX_BShift,
 568
 569     // The scaling factor for the AVX512's 8-bit compressed displacement.
 570     CD8_Scale_Shift = EVEX_BShift + 1,
 571     CD8_Scale_Mask = 127ULL << CD8_Scale_Shift,
 572
 573     /// Explicitly specified rounding control
 574     EVEX_RCShift = CD8_Scale_Shift + 7,
 575     EVEX_RC = 1ULL << EVEX_RCShift,
 576
 577     // NOTRACK prefix
 578     NoTrackShift = EVEX_RCShift + 1,
 579     NOTRACK = 1ULL << NoTrackShift
 580   };
 581
 582   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
 583   // specified machine instruction.
 584   //
 585   inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
 586     return TSFlags >> X86II::OpcodeShift;
 587   }
 588
 589   inline bool hasImm(uint64_t TSFlags) {
 590     return (TSFlags & X86II::ImmMask) != 0;
 591   }
 592
 593   /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
 594   /// of the specified instruction.
 595   inline unsigned getSizeOfImm(uint64_t TSFlags) {
 596     switch (TSFlags & X86II::ImmMask) {
 597     default: llvm_unreachable("Unknown immediate size");
 598     case X86II::Imm8:
 599     case X86II::Imm8PCRel:
 600     case X86II::Imm8Reg:    return 1;
 601     case X86II::Imm16:
 602     case X86II::Imm16PCRel: return 2;
 603     case X86II::Imm32:
 604     case X86II::Imm32S:
 605     case X86II::Imm32PCRel: return 4;
 606     case X86II::Imm64:      return 8;
 607     }
 608   }
 609
 610   /// isImmPCRel - Return true if the immediate of the specified instruction's
 611   /// TSFlags indicates that it is pc relative.
 612   inline unsigned isImmPCRel(uint64_t TSFlags) {
 613     switch (TSFlags & X86II::ImmMask) {
 614     default: llvm_unreachable("Unknown immediate size");
 615     case X86II::Imm8PCRel:
 616     case X86II::Imm16PCRel:
 617     case X86II::Imm32PCRel:
 618       return true;
 619     case X86II::Imm8:
 620     case X86II::Imm8Reg:
 621     case X86II::Imm16:
 622     case X86II::Imm32:
 623     case X86II::Imm32S:
 624     case X86II::Imm64:
 625       return false;
 626     }
 627   }
 628
 629   /// isImmSigned - Return true if the immediate of the specified instruction's
 630   /// TSFlags indicates that it is signed.
 631   inline unsigned isImmSigned(uint64_t TSFlags) {
 632     switch (TSFlags & X86II::ImmMask) {
 633     default: llvm_unreachable("Unknown immediate signedness");
 634     case X86II::Imm32S:
 635       return true;
 636     case X86II::Imm8:
 637     case X86II::Imm8PCRel:
 638     case X86II::Imm8Reg:
 639     case X86II::Imm16:
 640     case X86II::Imm16PCRel:
 641     case X86II::Imm32:
 642     case X86II::Imm32PCRel:
 643     case X86II::Imm64:
 644       return false;
 645     }
 646   }
 647
 648   /// getOperandBias - compute whether all of the def operands are repeated
 649   ///                  in the uses and therefore should be skipped.
 650   /// This determines the start of the unique operand list. We need to determine
 651   /// if all of the defs have a corresponding tied operand in the uses.
 652   /// Unfortunately, the tied operand information is encoded in the uses not
 653   /// the defs so we have to use some heuristics to find which operands to
 654   /// query.
 655   inline unsigned getOperandBias(const MCInstrDesc& Desc) {
 656     unsigned NumDefs = Desc.getNumDefs();
 657     unsigned NumOps = Desc.getNumOperands();
 658     switch (NumDefs) {
 659     default: llvm_unreachable("Unexpected number of defs");
 660     case 0:
 661       return 0;
 662     case 1:
 663       // Common two addr case.
 664       if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
 665         return 1;
 666       // Check for AVX-512 scatter which has a TIED_TO in the second to last
 667       // operand.
 668       if (NumOps == 8 &&
 669           Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
 670         return 1;
 671       return 0;
 672     case 2:
 673       // XCHG/XADD have two destinations and two sources.
 674       if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
 675           Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
 676         return 2;
 677       // Check for gather. AVX-512 has the second tied operand early. AVX2
 678       // has it as the last op.
 679       if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
 680           (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
 681            Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1) &&
 682           "Instruction with 2 defs isn't gather?")
 683         return 2;
 684       return 0;
 685     }
 686   }
 687
 688   /// getMemoryOperandNo - The function returns the MCInst operand # for the
 689   /// first field of the memory operand.  If the instruction doesn't have a
 690   /// memory operand, this returns -1.
 691   ///
 692   /// Note that this ignores tied operands.  If there is a tied register which
 693   /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
 694   /// counted as one operand.
 695   ///
 696   inline int getMemoryOperandNo(uint64_t TSFlags) {
 697     bool HasVEX_4V = TSFlags & X86II::VEX_4V;
 698     bool HasEVEX_K = TSFlags & X86II::EVEX_K;
 699
 700     switch (TSFlags & X86II::FormMask) {
 701     default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
 702     case X86II::Pseudo:
 703     case X86II::RawFrm:
 704     case X86II::AddRegFrm:
 705     case X86II::RawFrmImm8:
 706     case X86II::RawFrmImm16:
 707     case X86II::RawFrmMemOffs:
 708     case X86II::RawFrmSrc:
 709     case X86II::RawFrmDst:
 710     case X86II::RawFrmDstSrc:
 711       return -1;
 712     case X86II::MRMDestMem:
 713       return 0;
 714     case X86II::MRMSrcMem:
 715       // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
 716       // mask register.
 717       return 1 + HasVEX_4V + HasEVEX_K;
 718     case X86II::MRMSrcMem4VOp3:
 719       // Skip registers encoded in reg.
 720       return 1 + HasEVEX_K;
 721     case X86II::MRMSrcMemOp4:
 722       // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
 723       return 3;
 724     case X86II::MRMDestReg:
 725     case X86II::MRMSrcReg:
 726     case X86II::MRMSrcReg4VOp3:
 727     case X86II::MRMSrcRegOp4:
 728     case X86II::MRMXr:
 729     case X86II::MRM0r: case X86II::MRM1r:
 730     case X86II::MRM2r: case X86II::MRM3r:
 731     case X86II::MRM4r: case X86II::MRM5r:
 732     case X86II::MRM6r: case X86II::MRM7r:
 733       return -1;
 734     case X86II::MRMXm:
 735     case X86II::MRM0m: case X86II::MRM1m:
 736     case X86II::MRM2m: case X86II::MRM3m:
 737     case X86II::MRM4m: case X86II::MRM5m:
 738     case X86II::MRM6m: case X86II::MRM7m:
 739       // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
 740       return 0 + HasVEX_4V + HasEVEX_K;
 741     case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
 742     case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
 743     case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
 744     case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
 745     case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
 746     case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
 747     case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
 748     case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
 749     case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
 750     case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
 751     case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
 752     case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
 753     case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
 754     case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
 755     case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
 756     case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
 757     case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
 758     case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
 759     case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
 760     case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
 761     case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
 762     case X86II::MRM_FF:
 763       return -1;
 764     }
 765   }
 766
 767   /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
 768   /// higher) register?  e.g. r8, xmm8, xmm13, etc.
 769   inline bool isX86_64ExtendedReg(unsigned RegNo) {
 770     if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
 771         (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
 772         (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
 773       return true;
 774
 775     switch (RegNo) {
 776     default: break;
 777     case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
 778     case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
 779     case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
 780     case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
 781     case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
 782     case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
 783     case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
 784     case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
 785     case X86::CR8:   case X86::CR9:   case X86::CR10:  case X86::CR11:
 786     case X86::CR12:  case X86::CR13:  case X86::CR14:  case X86::CR15:
 787     case X86::DR8:   case X86::DR9:   case X86::DR10:  case X86::DR11:
 788     case X86::DR12:  case X86::DR13:  case X86::DR14:  case X86::DR15:
 789       return true;
 790     }
 791     return false;
 792   }
 793
 794   /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
 795   /// registers? e.g. zmm21, etc.
 796   static inline bool is32ExtendedReg(unsigned RegNo) {
 797     return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
 798             (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
 799             (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
 800   }
 801
 802
 803   inline bool isX86_64NonExtLowByteReg(unsigned reg) {
 804     return (reg == X86::SPL || reg == X86::BPL ||
 805             reg == X86::SIL || reg == X86::DIL);
 806   }
 807
 808   /// isKMasked - Is this a masked instruction.
 809   inline bool isKMasked(uint64_t TSFlags) {
 810     return (TSFlags & X86II::EVEX_K) != 0;
 811   }
 812
 813   /// isKMergedMasked - Is this a merge masked instruction.
 814   inline bool isKMergeMasked(uint64_t TSFlags) {
 815     return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
 816   }
 817 }
 818
 819 } // end namespace llvm;
 820
 821 #endif