lib/Target/X86/X86CallLowering.cpp

   1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// This file implements the lowering of LLVM calls to machine code calls for
  11 /// GlobalISel.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "X86CallLowering.h"
  16 #include "X86CallingConv.h"
  17 #include "X86ISelLowering.h"
  18 #include "X86InstrInfo.h"
  19 #include "X86RegisterInfo.h"
  20 #include "X86Subtarget.h"
  21 #include "llvm/ADT/ArrayRef.h"
  22 #include "llvm/ADT/SmallVector.h"
  23 #include "llvm/CodeGen/Analysis.h"
  24 #include "llvm/CodeGen/CallingConvLower.h"
  25 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
  26 #include "llvm/CodeGen/GlobalISel/Utils.h"
  27 #include "llvm/CodeGen/LowLevelType.h"
  28 #include "llvm/CodeGen/MachineBasicBlock.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/CodeGen/MachineFunction.h"
  31 #include "llvm/CodeGen/MachineInstrBuilder.h"
  32 #include "llvm/CodeGen/MachineMemOperand.h"
  33 #include "llvm/CodeGen/MachineOperand.h"
  34 #include "llvm/CodeGen/MachineRegisterInfo.h"
  35 #include "llvm/CodeGen/TargetInstrInfo.h"
  36 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  37 #include "llvm/CodeGen/ValueTypes.h"
  38 #include "llvm/IR/Attributes.h"
  39 #include "llvm/IR/DataLayout.h"
  40 #include "llvm/IR/Function.h"
  41 #include "llvm/IR/Value.h"
  42 #include "llvm/MC/MCRegisterInfo.h"
  43 #include "llvm/Support/LowLevelTypeImpl.h"
  44 #include "llvm/Support/MachineValueType.h"
  45 #include <cassert>
  46 #include <cstdint>
  47
  48 using namespace llvm;
  49
  50 X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
  51     : CallLowering(&TLI) {}
  52
  53 bool X86CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
  54                                         SmallVectorImpl<ArgInfo> &SplitArgs,
  55                                         const DataLayout &DL,
  56                                         MachineRegisterInfo &MRI,
  57                                         SplitArgTy PerformArgSplit) const {
  58   const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
  59   LLVMContext &Context = OrigArg.Ty->getContext();
  60
  61   SmallVector<EVT, 4> SplitVTs;
  62   SmallVector<uint64_t, 4> Offsets;
  63   ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
  64
  65   if (OrigArg.Ty->isVoidTy())
  66     return true;
  67
  68   EVT VT = SplitVTs[0];
  69   unsigned NumParts = TLI.getNumRegisters(Context, VT);
  70
  71   if (NumParts == 1) {
  72     // replace the original type ( pointer -> GPR ).
  73     SplitArgs.emplace_back(OrigArg.Reg, VT.getTypeForEVT(Context),
  74                            OrigArg.Flags, OrigArg.IsFixed);
  75     return true;
  76   }
  77
  78   SmallVector<unsigned, 8> SplitRegs;
  79
  80   EVT PartVT = TLI.getRegisterType(Context, VT);
  81   Type *PartTy = PartVT.getTypeForEVT(Context);
  82
  83   for (unsigned i = 0; i < NumParts; ++i) {
  84     ArgInfo Info =
  85         ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
  86                 PartTy, OrigArg.Flags};
  87     SplitArgs.push_back(Info);
  88     SplitRegs.push_back(Info.Reg);
  89   }
  90
  91   PerformArgSplit(SplitRegs);
  92   return true;
  93 }
  94
  95 namespace {
  96
  97 struct OutgoingValueHandler : public CallLowering::ValueHandler {
  98   OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
  99                        MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
 100       : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
 101         DL(MIRBuilder.getMF().getDataLayout()),
 102         STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
 103
 104   unsigned getStackAddress(uint64_t Size, int64_t Offset,
 105                            MachinePointerInfo &MPO) override {
 106     LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
 107     LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
 108     unsigned SPReg = MRI.createGenericVirtualRegister(p0);
 109     MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister());
 110
 111     unsigned OffsetReg = MRI.createGenericVirtualRegister(SType);
 112     MIRBuilder.buildConstant(OffsetReg, Offset);
 113
 114     unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
 115     MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
 116
 117     MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
 118     return AddrReg;
 119   }
 120
 121   void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
 122                         CCValAssign &VA) override {
 123     MIB.addUse(PhysReg, RegState::Implicit);
 124
 125     unsigned ExtReg;
 126     // If we are copying the value to a physical register with the
 127     // size larger than the size of the value itself - build AnyExt
 128     // to the size of the register first and only then do the copy.
 129     // The example of that would be copying from s32 to xmm0, for which
 130     // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
 131     // we expect normal extendRegister mechanism to work.
 132     unsigned PhysRegSize =
 133         MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
 134     unsigned ValSize = VA.getValVT().getSizeInBits();
 135     unsigned LocSize = VA.getLocVT().getSizeInBits();
 136     if (PhysRegSize > ValSize && LocSize == ValSize) {
 137       assert((PhysRegSize == 128 || PhysRegSize == 80)  && "We expect that to be 128 bit");
 138       auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
 139       ExtReg = MIB->getOperand(0).getReg();
 140     } else
 141       ExtReg = extendRegister(ValVReg, VA);
 142
 143     MIRBuilder.buildCopy(PhysReg, ExtReg);
 144   }
 145
 146   void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
 147                             MachinePointerInfo &MPO, CCValAssign &VA) override {
 148     unsigned ExtReg = extendRegister(ValVReg, VA);
 149     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
 150         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
 151         /* Alignment */ 1);
 152     MIRBuilder.buildStore(ExtReg, Addr, *MMO);
 153   }
 154
 155   bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
 156                  CCValAssign::LocInfo LocInfo,
 157                  const CallLowering::ArgInfo &Info, CCState &State) override {
 158     bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State);
 159     StackSize = State.getNextStackOffset();
 160
 161     static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
 162                                            X86::XMM3, X86::XMM4, X86::XMM5,
 163                                            X86::XMM6, X86::XMM7};
 164     if (!Info.IsFixed)
 165       NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
 166
 167     return Res;
 168   }
 169
 170   uint64_t getStackSize() { return StackSize; }
 171   uint64_t getNumXmmRegs() { return NumXMMRegs; }
 172
 173 protected:
 174   MachineInstrBuilder &MIB;
 175   uint64_t StackSize = 0;
 176   const DataLayout &DL;
 177   const X86Subtarget &STI;
 178   unsigned NumXMMRegs = 0;
 179 };
 180
 181 } // end anonymous namespace
 182
 183 bool X86CallLowering::lowerReturn(
 184     MachineIRBuilder &MIRBuilder, const Value *Val,
 185     ArrayRef<unsigned> VRegs) const {
 186   assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
 187          "Return value without a vreg");
 188   auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
 189
 190   if (!VRegs.empty()) {
 191     MachineFunction &MF = MIRBuilder.getMF();
 192     const Function &F = MF.getFunction();
 193     MachineRegisterInfo &MRI = MF.getRegInfo();
 194     auto &DL = MF.getDataLayout();
 195     LLVMContext &Ctx = Val->getType()->getContext();
 196     const X86TargetLowering &TLI = *getTLI<X86TargetLowering>();
 197
 198     SmallVector<EVT, 4> SplitEVTs;
 199     ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
 200     assert(VRegs.size() == SplitEVTs.size() &&
 201            "For each split Type there should be exactly one VReg.");
 202
 203     SmallVector<ArgInfo, 8> SplitArgs;
 204     for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
 205       ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
 206       setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
 207       if (!splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI,
 208                              [&](ArrayRef<unsigned> Regs) {
 209                                MIRBuilder.buildUnmerge(Regs, VRegs[i]);
 210                              }))
 211         return false;
 212     }
 213
 214     OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86);
 215     if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 216       return false;
 217   }
 218
 219   MIRBuilder.insertInstr(MIB);
 220   return true;
 221 }
 222
 223 namespace {
 224
 225 struct IncomingValueHandler : public CallLowering::ValueHandler {
 226   IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 227                        CCAssignFn *AssignFn)
 228       : ValueHandler(MIRBuilder, MRI, AssignFn),
 229         DL(MIRBuilder.getMF().getDataLayout()) {}
 230
 231   unsigned getStackAddress(uint64_t Size, int64_t Offset,
 232                            MachinePointerInfo &MPO) override {
 233     auto &MFI = MIRBuilder.getMF().getFrameInfo();
 234     int FI = MFI.CreateFixedObject(Size, Offset, true);
 235     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
 236
 237     unsigned AddrReg = MRI.createGenericVirtualRegister(
 238         LLT::pointer(0, DL.getPointerSizeInBits(0)));
 239     MIRBuilder.buildFrameIndex(AddrReg, FI);
 240     return AddrReg;
 241   }
 242
 243   void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
 244                             MachinePointerInfo &MPO, CCValAssign &VA) override {
 245     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
 246         MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
 247         1);
 248     MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
 249   }
 250
 251   void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
 252                         CCValAssign &VA) override {
 253     markPhysRegUsed(PhysReg);
 254
 255     switch (VA.getLocInfo()) {
 256     default: {
 257       // If we are copying the value from a physical register with the
 258       // size larger than the size of the value itself - build the copy
 259       // of the phys reg first and then build the truncation of that copy.
 260       // The example of that would be copying from xmm0 to s32, for which
 261       // case ValVT == LocVT == MVT::f32. If LocSize and ValSize are not equal
 262       // we expect this to be handled in SExt/ZExt/AExt case.
 263       unsigned PhysRegSize =
 264           MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
 265       unsigned ValSize = VA.getValVT().getSizeInBits();
 266       unsigned LocSize = VA.getLocVT().getSizeInBits();
 267       if (PhysRegSize > ValSize && LocSize == ValSize) {
 268         auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
 269         MIRBuilder.buildTrunc(ValVReg, Copy);
 270         return;
 271       }
 272
 273       MIRBuilder.buildCopy(ValVReg, PhysReg);
 274       break;
 275     }
 276     case CCValAssign::LocInfo::SExt:
 277     case CCValAssign::LocInfo::ZExt:
 278     case CCValAssign::LocInfo::AExt: {
 279       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
 280       MIRBuilder.buildTrunc(ValVReg, Copy);
 281       break;
 282     }
 283     }
 284   }
 285
 286   /// How the physical register gets marked varies between formal
 287   /// parameters (it's a basic-block live-in), and a call instruction
 288   /// (it's an implicit-def of the BL).
 289   virtual void markPhysRegUsed(unsigned PhysReg) = 0;
 290
 291 protected:
 292   const DataLayout &DL;
 293 };
 294
 295 struct FormalArgHandler : public IncomingValueHandler {
 296   FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 297                    CCAssignFn *AssignFn)
 298       : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
 299
 300   void markPhysRegUsed(unsigned PhysReg) override {
 301     MIRBuilder.getMBB().addLiveIn(PhysReg);
 302   }
 303 };
 304
 305 struct CallReturnHandler : public IncomingValueHandler {
 306   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
 307                     CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
 308       : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
 309
 310   void markPhysRegUsed(unsigned PhysReg) override {
 311     MIB.addDef(PhysReg, RegState::Implicit);
 312   }
 313
 314 protected:
 315   MachineInstrBuilder &MIB;
 316 };
 317
 318 } // end anonymous namespace
 319
 320 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
 321                                            const Function &F,
 322                                            ArrayRef<unsigned> VRegs) const {
 323   if (F.arg_empty())
 324     return true;
 325
 326   // TODO: handle variadic function
 327   if (F.isVarArg())
 328     return false;
 329
 330   MachineFunction &MF = MIRBuilder.getMF();
 331   MachineRegisterInfo &MRI = MF.getRegInfo();
 332   auto DL = MF.getDataLayout();
 333
 334   SmallVector<ArgInfo, 8> SplitArgs;
 335   unsigned Idx = 0;
 336   for (auto &Arg : F.args()) {
 337
 338     // TODO: handle not simple cases.
 339     if (Arg.hasAttribute(Attribute::ByVal) ||
 340         Arg.hasAttribute(Attribute::InReg) ||
 341         Arg.hasAttribute(Attribute::StructRet) ||
 342         Arg.hasAttribute(Attribute::SwiftSelf) ||
 343         Arg.hasAttribute(Attribute::SwiftError) ||
 344         Arg.hasAttribute(Attribute::Nest))
 345       return false;
 346
 347     ArgInfo OrigArg(VRegs[Idx], Arg.getType());
 348     setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
 349     if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
 350                            [&](ArrayRef<unsigned> Regs) {
 351                              MIRBuilder.buildMerge(VRegs[Idx], Regs);
 352                            }))
 353       return false;
 354     Idx++;
 355   }
 356
 357   MachineBasicBlock &MBB = MIRBuilder.getMBB();
 358   if (!MBB.empty())
 359     MIRBuilder.setInstr(*MBB.begin());
 360
 361   FormalArgHandler Handler(MIRBuilder, MRI, CC_X86);
 362   if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 363     return false;
 364
 365   // Move back to the end of the basic block.
 366   MIRBuilder.setMBB(MBB);
 367
 368   return true;
 369 }
 370
 371 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
 372                                 CallingConv::ID CallConv,
 373                                 const MachineOperand &Callee,
 374                                 const ArgInfo &OrigRet,
 375                                 ArrayRef<ArgInfo> OrigArgs) const {
 376   MachineFunction &MF = MIRBuilder.getMF();
 377   const Function &F = MF.getFunction();
 378   MachineRegisterInfo &MRI = MF.getRegInfo();
 379   auto &DL = F.getParent()->getDataLayout();
 380   const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
 381   const TargetInstrInfo &TII = *STI.getInstrInfo();
 382   auto TRI = STI.getRegisterInfo();
 383
 384   // Handle only Linux C, X86_64_SysV calling conventions for now.
 385   if (!STI.isTargetLinux() ||
 386       !(CallConv == CallingConv::C || CallConv == CallingConv::X86_64_SysV))
 387     return false;
 388
 389   unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
 390   auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
 391
 392   // Create a temporarily-floating call instruction so we can add the implicit
 393   // uses of arg registers.
 394   bool Is64Bit = STI.is64Bit();
 395   unsigned CallOpc = Callee.isReg()
 396                          ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
 397                          : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
 398
 399   auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc).add(Callee).addRegMask(
 400       TRI->getCallPreservedMask(MF, CallConv));
 401
 402   SmallVector<ArgInfo, 8> SplitArgs;
 403   for (const auto &OrigArg : OrigArgs) {
 404
 405     // TODO: handle not simple cases.
 406     if (OrigArg.Flags.isByVal())
 407       return false;
 408
 409     if (!splitToValueTypes(OrigArg, SplitArgs, DL, MRI,
 410                            [&](ArrayRef<unsigned> Regs) {
 411                              MIRBuilder.buildUnmerge(Regs, OrigArg.Reg);
 412                            }))
 413       return false;
 414   }
 415   // Do the actual argument marshalling.
 416   OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, CC_X86);
 417   if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 418     return false;
 419
 420   bool IsFixed = OrigArgs.empty() ? true : OrigArgs.back().IsFixed;
 421   if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(CallConv)) {
 422     // From AMD64 ABI document:
 423     // For calls that may call functions that use varargs or stdargs
 424     // (prototype-less calls or calls to functions containing ellipsis (...) in
 425     // the declaration) %al is used as hidden argument to specify the number
 426     // of SSE registers used. The contents of %al do not need to match exactly
 427     // the number of registers, but must be an ubound on the number of SSE
 428     // registers used and is in the range 0 - 8 inclusive.
 429
 430     MIRBuilder.buildInstr(X86::MOV8ri)
 431         .addDef(X86::AL)
 432         .addImm(Handler.getNumXmmRegs());
 433     MIB.addUse(X86::AL, RegState::Implicit);
 434   }
 435
 436   // Now we can add the actual call instruction to the correct basic block.
 437   MIRBuilder.insertInstr(MIB);
 438
 439   // If Callee is a reg, since it is used by a target specific
 440   // instruction, it must have a register class matching the
 441   // constraint of that instruction.
 442   if (Callee.isReg())
 443     MIB->getOperand(0).setReg(constrainOperandRegClass(
 444         MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
 445         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Callee, 0));
 446
 447   // Finally we can copy the returned value back into its virtual-register. In
 448   // symmetry with the arguments, the physical register must be an
 449   // implicit-define of the call instruction.
 450
 451   if (OrigRet.Reg) {
 452     SplitArgs.clear();
 453     SmallVector<unsigned, 8> NewRegs;
 454
 455     if (!splitToValueTypes(OrigRet, SplitArgs, DL, MRI,
 456                            [&](ArrayRef<unsigned> Regs) {
 457                              NewRegs.assign(Regs.begin(), Regs.end());
 458                            }))
 459       return false;
 460
 461     CallReturnHandler Handler(MIRBuilder, MRI, RetCC_X86, MIB);
 462     if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
 463       return false;
 464
 465     if (!NewRegs.empty())
 466       MIRBuilder.buildMerge(OrigRet.Reg, NewRegs);
 467   }
 468
 469   CallSeqStart.addImm(Handler.getStackSize())
 470       .addImm(0 /* see getFrameTotalSize */)
 471       .addImm(0 /* see getFrameAdjustment */);
 472
 473   unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
 474   MIRBuilder.buildInstr(AdjStackUp)
 475       .addImm(Handler.getStackSize())
 476       .addImm(0 /* NumBytesForCalleeToPop */);
 477
 478   return true;
 479 }