lib/Target/X86/X86InstrFragmentsSIMD.td

   1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file provides pattern fragments useful for SIMD instructions.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // MMX specific DAG Nodes.
  15 //===----------------------------------------------------------------------===//
  16
  17 // Low word of MMX to GPR.
  18 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
  19                             [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
  20 // GPR to low word of MMX.
  21 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
  22                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
  23
  24 //===----------------------------------------------------------------------===//
  25 // MMX Pattern Fragments
  26 //===----------------------------------------------------------------------===//
  27
  28 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
  29
  30 //===----------------------------------------------------------------------===//
  31 // SSE specific DAG Nodes.
  32 //===----------------------------------------------------------------------===//
  33
  34 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
  35                                        SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  36                                        SDTCisVT<3, i8>]>;
  37
  38 def X86fmin    : SDNode<"X86ISD::FMIN",      SDTFPBinOp>;
  39 def X86fmax    : SDNode<"X86ISD::FMAX",      SDTFPBinOp>;
  40 def X86fmins   : SDNode<"X86ISD::FMINS",     SDTFPBinOp>;
  41 def X86fmaxs   : SDNode<"X86ISD::FMAXS",     SDTFPBinOp>;
  42
  43 // Commutative and Associative FMIN and FMAX.
  44 def X86fminc    : SDNode<"X86ISD::FMINC", SDTFPBinOp,
  45     [SDNPCommutative, SDNPAssociative]>;
  46 def X86fmaxc    : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
  47     [SDNPCommutative, SDNPAssociative]>;
  48
  49 def X86fand    : SDNode<"X86ISD::FAND",      SDTFPBinOp,
  50                         [SDNPCommutative, SDNPAssociative]>;
  51 def X86for     : SDNode<"X86ISD::FOR",       SDTFPBinOp,
  52                         [SDNPCommutative, SDNPAssociative]>;
  53 def X86fxor    : SDNode<"X86ISD::FXOR",      SDTFPBinOp,
  54                         [SDNPCommutative, SDNPAssociative]>;
  55 def X86fandn   : SDNode<"X86ISD::FANDN",     SDTFPBinOp>;
  56 def X86frsqrt  : SDNode<"X86ISD::FRSQRT",    SDTFPUnaryOp>;
  57 def X86frcp    : SDNode<"X86ISD::FRCP",      SDTFPUnaryOp>;
  58 def X86fhadd   : SDNode<"X86ISD::FHADD",     SDTFPBinOp>;
  59 def X86fhsub   : SDNode<"X86ISD::FHSUB",     SDTFPBinOp>;
  60 def X86hadd    : SDNode<"X86ISD::HADD",      SDTIntBinOp>;
  61 def X86hsub    : SDNode<"X86ISD::HSUB",      SDTIntBinOp>;
  62 def X86comi    : SDNode<"X86ISD::COMI",      SDTX86CmpTest>;
  63 def X86ucomi   : SDNode<"X86ISD::UCOMI",     SDTX86CmpTest>;
  64 def X86cmps    : SDNode<"X86ISD::FSETCC",     SDTX86Cmps>;
  65 def X86pshufb  : SDNode<"X86ISD::PSHUFB",
  66                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i8>, SDTCisSameAs<0,1>,
  67                                       SDTCisSameAs<0,2>]>>;
  68 def X86psadbw  : SDNode<"X86ISD::PSADBW",
  69                  SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
  70                                       SDTCVecEltisVT<1, i8>,
  71                                       SDTCisSameSizeAs<0,1>,
  72                                       SDTCisSameAs<1,2>]>, [SDNPCommutative]>;
  73 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
  74                   SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
  75                                        SDTCVecEltisVT<1, i8>,
  76                                        SDTCisSameSizeAs<0,1>,
  77                                        SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>>;
  78 def X86andnp   : SDNode<"X86ISD::ANDNP",
  79                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
  80                                       SDTCisSameAs<0,2>]>>;
  81 def X86multishift   : SDNode<"X86ISD::MULTISHIFT",
  82                  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
  83                                       SDTCisSameAs<1,2>]>>;
  84 def X86pextrb  : SDNode<"X86ISD::PEXTRB",
  85                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v16i8>,
  86                                       SDTCisPtrTy<2>]>>;
  87 def X86pextrw  : SDNode<"X86ISD::PEXTRW",
  88                  SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVT<1, v8i16>,
  89                                       SDTCisPtrTy<2>]>>;
  90 def X86pinsrb  : SDNode<"X86ISD::PINSRB",
  91                  SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
  92                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  93 def X86pinsrw  : SDNode<"X86ISD::PINSRW",
  94                  SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
  95                                       SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
  96 def X86insertps : SDNode<"X86ISD::INSERTPS",
  97                  SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
  98                                       SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
  99 def X86vzmovl  : SDNode<"X86ISD::VZEXT_MOVL",
 100                  SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
 101
 102 def X86vzload  : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
 103                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 104
 105 def SDTVtrunc    : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 106                                         SDTCisInt<0>, SDTCisInt<1>,
 107                                         SDTCisOpSmallerThanOp<0, 1>]>;
 108 def SDTVmtrunc   : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 109                                         SDTCisInt<0>, SDTCisInt<1>,
 110                                         SDTCisOpSmallerThanOp<0, 1>,
 111                                         SDTCisSameAs<0, 2>,
 112                                         SDTCVecEltisVT<3, i1>,
 113                                         SDTCisSameNumEltsAs<1, 3>]>;
 114
 115 def X86vtrunc    : SDNode<"X86ISD::VTRUNC",   SDTVtrunc>;
 116 def X86vtruncs   : SDNode<"X86ISD::VTRUNCS",  SDTVtrunc>;
 117 def X86vtruncus  : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
 118 def X86vmtrunc   : SDNode<"X86ISD::VMTRUNC",   SDTVmtrunc>;
 119 def X86vmtruncs  : SDNode<"X86ISD::VMTRUNCS",  SDTVmtrunc>;
 120 def X86vmtruncus : SDNode<"X86ISD::VMTRUNCUS", SDTVmtrunc>;
 121
 122 def X86vfpext  : SDNode<"X86ISD::VFPEXT",
 123                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f64>,
 124                                              SDTCVecEltisVT<1, f32>,
 125                                              SDTCisSameSizeAs<0, 1>]>>;
 126 def X86vfpround: SDNode<"X86ISD::VFPROUND",
 127                         SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 128                                              SDTCVecEltisVT<1, f64>,
 129                                              SDTCisOpSmallerThanOp<0, 1>]>>;
 130
 131 def X86froundRnd: SDNode<"X86ISD::VFPROUNDS_RND",
 132                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 133                                              SDTCisSameAs<0, 1>,
 134                                              SDTCVecEltisVT<2, f64>,
 135                                              SDTCisSameSizeAs<0, 2>,
 136                                              SDTCisVT<3, i32>]>>;
 137
 138 def X86fpextRnd  : SDNode<"X86ISD::VFPEXTS_RND",
 139                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f64>,
 140                                              SDTCisSameAs<0, 1>,
 141                                              SDTCVecEltisVT<2, f32>,
 142                                              SDTCisSameSizeAs<0, 2>,
 143                                              SDTCisVT<3, i32>]>>;
 144
 145 def X86vmfpround: SDNode<"X86ISD::VMFPROUND",
 146                          SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
 147                                               SDTCVecEltisVT<1, f64>,
 148                                               SDTCisSameSizeAs<0, 1>,
 149                                               SDTCisSameAs<0, 2>,
 150                                               SDTCVecEltisVT<3, i1>,
 151                                               SDTCisSameNumEltsAs<1, 3>]>>;
 152
 153 def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 154                                         SDTCisVT<2, i8>, SDTCisInt<0>]>;
 155
 156 def X86vshldq  : SDNode<"X86ISD::VSHLDQ",    X86vshiftimm>;
 157 def X86vshrdq  : SDNode<"X86ISD::VSRLDQ",    X86vshiftimm>;
 158 def X86cmpp    : SDNode<"X86ISD::CMPP",      SDTX86VFCMP>;
 159 def X86pcmpeq  : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
 160 def X86pcmpgt  : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
 161
 162 def X86CmpMaskCC :
 163       SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
 164                        SDTCisVec<1>, SDTCisSameAs<2, 1>,
 165                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
 166 def X86CmpMaskCCRound :
 167       SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
 168                        SDTCisVec<1>, SDTCisFP<1>, SDTCisSameAs<2, 1>,
 169                        SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
 170                        SDTCisVT<4, i32>]>;
 171 def X86CmpMaskCCScalar :
 172       SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
 173                            SDTCisVT<3, i8>]>;
 174
 175 def X86CmpMaskCCScalarRound :
 176       SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
 177                            SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
 178
 179 def X86cmpm     : SDNode<"X86ISD::CMPM",     X86CmpMaskCC>;
 180 // Hack to make CMPM commutable in tablegen patterns for load folding.
 181 def X86cmpm_c   : SDNode<"X86ISD::CMPM",     X86CmpMaskCC, [SDNPCommutative]>;
 182 def X86cmpmRnd  : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
 183 def X86cmpms    : SDNode<"X86ISD::FSETCCM",   X86CmpMaskCCScalar>;
 184 def X86cmpmsRnd : SDNode<"X86ISD::FSETCCM_RND",   X86CmpMaskCCScalarRound>;
 185
 186 def X86phminpos: SDNode<"X86ISD::PHMINPOS",
 187                  SDTypeProfile<1, 1, [SDTCisVT<0, v8i16>, SDTCisVT<1, v8i16>]>>;
 188
 189 def X86vshiftuniform : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 190                                             SDTCisVec<2>, SDTCisInt<0>,
 191                                             SDTCisInt<2>]>;
 192
 193 def X86vshl    : SDNode<"X86ISD::VSHL", X86vshiftuniform>;
 194 def X86vsrl    : SDNode<"X86ISD::VSRL", X86vshiftuniform>;
 195 def X86vsra    : SDNode<"X86ISD::VSRA", X86vshiftuniform>;
 196
 197 def X86vshiftvariable : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 198                                              SDTCisSameAs<0,2>, SDTCisInt<0>]>;
 199
 200 def X86vshlv   : SDNode<"X86ISD::VSHLV", X86vshiftvariable>;
 201 def X86vsrlv   : SDNode<"X86ISD::VSRLV", X86vshiftvariable>;
 202 def X86vsrav   : SDNode<"X86ISD::VSRAV", X86vshiftvariable>;
 203
 204 def X86vshli   : SDNode<"X86ISD::VSHLI", X86vshiftimm>;
 205 def X86vsrli   : SDNode<"X86ISD::VSRLI", X86vshiftimm>;
 206 def X86vsrai   : SDNode<"X86ISD::VSRAI", X86vshiftimm>;
 207
 208 def X86kshiftl : SDNode<"X86ISD::KSHIFTL",
 209                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 210                                              SDTCisSameAs<0, 1>,
 211                                              SDTCisVT<2, i8>]>>;
 212 def X86kshiftr : SDNode<"X86ISD::KSHIFTR",
 213                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 214                                              SDTCisSameAs<0, 1>,
 215                                              SDTCisVT<2, i8>]>>;
 216
 217 def X86kadd : SDNode<"X86ISD::KADD", SDTIntBinOp, [SDNPCommutative]>;
 218
 219 def X86vrotli  : SDNode<"X86ISD::VROTLI", X86vshiftimm>;
 220 def X86vrotri  : SDNode<"X86ISD::VROTRI", X86vshiftimm>;
 221
 222 def X86vpshl   : SDNode<"X86ISD::VPSHL", X86vshiftvariable>;
 223 def X86vpsha   : SDNode<"X86ISD::VPSHA", X86vshiftvariable>;
 224
 225 def X86vpcom   : SDNode<"X86ISD::VPCOM",
 226                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 227                                              SDTCisSameAs<0,2>,
 228                                              SDTCisVT<3, i8>, SDTCisInt<0>]>>;
 229 def X86vpcomu  : SDNode<"X86ISD::VPCOMU",
 230                         SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 231                                              SDTCisSameAs<0,2>,
 232                                              SDTCisVT<3, i8>, SDTCisInt<0>]>>;
 233 def X86vpermil2 : SDNode<"X86ISD::VPERMIL2",
 234                         SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 235                                              SDTCisSameAs<0,2>,
 236                                              SDTCisFP<0>, SDTCisInt<3>,
 237                                              SDTCisSameNumEltsAs<0, 3>,
 238                                              SDTCisSameSizeAs<0,3>,
 239                                              SDTCisVT<4, i8>]>>;
 240 def X86vpperm : SDNode<"X86ISD::VPPERM",
 241                         SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
 242                                              SDTCisSameAs<0,2>, SDTCisSameAs<0, 3>]>>;
 243
 244 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
 245                                           SDTCisVec<1>,
 246                                           SDTCisSameAs<2, 1>]>;
 247
 248 def X86mulhrs  : SDNode<"X86ISD::MULHRS", SDTIntBinOp, [SDNPCommutative]>;
 249 def X86avg     : SDNode<"X86ISD::AVG" , SDTIntBinOp, [SDNPCommutative]>;
 250 def X86ptest   : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
 251 def X86testp   : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
 252 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
 253 def X86ktest   : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
 254
 255 def X86movmsk : SDNode<"X86ISD::MOVMSK",
 256                         SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>>;
 257
 258 def X86selects : SDNode<"X86ISD::SELECTS",
 259                         SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
 260                                              SDTCisSameAs<0, 2>,
 261                                              SDTCisSameAs<2, 3>]>>;
 262
 263 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
 264                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 265                                              SDTCisSameAs<0,1>,
 266                                              SDTCisSameAs<1,2>]>,
 267                                              [SDNPCommutative]>;
 268 def X86pmuldq  : SDNode<"X86ISD::PMULDQ",
 269                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i64>,
 270                                              SDTCisSameAs<0,1>,
 271                                              SDTCisSameAs<1,2>]>,
 272                                              [SDNPCommutative]>;
 273
 274 def X86extrqi : SDNode<"X86ISD::EXTRQI",
 275                   SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 276                                        SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
 277 def X86insertqi : SDNode<"X86ISD::INSERTQI",
 278                     SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
 279                                          SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
 280                                          SDTCisVT<4, i8>]>>;
 281
 282 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
 283 // translated into one of the target nodes below during lowering.
 284 // Note: this is a work in progress...
 285 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
 286 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 287                                 SDTCisSameAs<0,2>]>;
 288 def SDTShuff2OpFP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>,
 289                                          SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>;
 290
 291 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 292                                         SDTCisFP<0>, SDTCisInt<2>,
 293                                         SDTCisSameNumEltsAs<0,2>,
 294                                         SDTCisSameSizeAs<0,2>]>;
 295 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
 296                                  SDTCisSameAs<0,1>, SDTCisVT<2, i8>]>;
 297 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 298                                  SDTCisSameAs<0,2>, SDTCisVT<3, i8>]>;
 299 def SDTFPBinOpImm: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
 300                                         SDTCisSameAs<0,1>,
 301                                         SDTCisSameAs<0,2>,
 302                                         SDTCisVT<3, i32>]>;
 303 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisVec<0>,
 304                                              SDTCisSameAs<0,1>,
 305                                              SDTCisSameAs<0,2>,
 306                                              SDTCisVT<3, i32>,
 307                                              SDTCisVT<4, i32>]>;
 308 def SDTFPTernaryOpImmRound: SDTypeProfile<1, 5, [SDTCisFP<0>, SDTCisSameAs<0,1>,
 309                                                  SDTCisSameAs<0,2>,
 310                                                  SDTCisInt<3>,
 311                                                  SDTCisSameSizeAs<0, 3>,
 312                                                  SDTCisSameNumEltsAs<0, 3>,
 313                                                  SDTCisVT<4, i32>,
 314                                                  SDTCisVT<5, i32>]>;
 315 def SDTFPUnaryOpImm: SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisVec<0>,
 316                                           SDTCisSameAs<0,1>,
 317                                           SDTCisVT<2, i32>]>;
 318 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisVec<0>,
 319                                                SDTCisSameAs<0,1>,
 320                                                SDTCisVT<2, i32>,
 321                                                SDTCisVT<3, i32>]>;
 322
 323 def SDTVBroadcast  : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
 324 def SDTVBroadcastm : SDTypeProfile<1, 1, [SDTCisVec<0>,
 325                                           SDTCisInt<0>, SDTCisInt<1>]>;
 326
 327 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 328                              SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
 329
 330 def SDTTernlog  : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisVec<0>,
 331                                        SDTCisSameAs<0,1>, SDTCisSameAs<0,2>,
 332                                        SDTCisSameAs<0,3>, SDTCisVT<4, i8>]>;
 333
 334 def SDTFPBinOpRound : SDTypeProfile<1, 3, [      // fadd_round, fmul_round, etc.
 335   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisVT<3, i32>]>;
 336
 337 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [      // fsqrt_round, fgetexp_round, etc.
 338   SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisVT<2, i32>]>;
 339
 340 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
 341                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>,
 342                            SDTCisFP<0>, SDTCisVT<4, i32>]>;
 343
 344 def X86PAlignr : SDNode<"X86ISD::PALIGNR",
 345                         SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>,
 346                                              SDTCisSameAs<0,1>,
 347                                              SDTCisSameAs<0,2>,
 348                                              SDTCisVT<3, i8>]>>;
 349 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
 350
 351 def X86VShld   : SDNode<"X86ISD::VSHLD", SDTShuff3OpI>;
 352 def X86VShrd   : SDNode<"X86ISD::VSHRD", SDTShuff3OpI>;
 353 def X86VShldv  : SDNode<"X86ISD::VSHLDV",
 354                         SDTypeProfile<1, 3, [SDTCisVec<0>,
 355                                              SDTCisSameAs<0,1>,
 356                                              SDTCisSameAs<0,2>,
 357                                              SDTCisSameAs<0,3>]>>;
 358 def X86VShrdv  : SDNode<"X86ISD::VSHRDV",
 359                         SDTypeProfile<1, 3, [SDTCisVec<0>,
 360                                              SDTCisSameAs<0,1>,
 361                                              SDTCisSameAs<0,2>,
 362                                              SDTCisSameAs<0,3>]>>;
 363
 364 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
 365
 366 def X86PShufd  : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
 367 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
 368 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
 369
 370 def X86Shufp   : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
 371 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
 372
 373 def X86Movddup  : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
 374 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
 375 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
 376
 377 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2OpFP>;
 378 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2OpFP>;
 379
 380 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2OpFP>;
 381 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2OpFP>;
 382
 383 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>,
 384                                    SDTCisVec<1>, SDTCisInt<1>,
 385                                    SDTCisSameSizeAs<0,1>,
 386                                    SDTCisSameAs<1,2>,
 387                                    SDTCisOpSmallerThanOp<0, 1>]>;
 388 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
 389 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
 390
 391 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
 392 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
 393
 394 def X86vpmaddubsw  : SDNode<"X86ISD::VPMADDUBSW",
 395                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 396                                                  SDTCVecEltisVT<1, i8>,
 397                                                  SDTCisSameSizeAs<0,1>,
 398                                                  SDTCisSameAs<1,2>]>>;
 399 def X86vpmaddwd    : SDNode<"X86ISD::VPMADDWD",
 400                             SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i32>,
 401                                                  SDTCVecEltisVT<1, i16>,
 402                                                  SDTCisSameSizeAs<0,1>,
 403                                                  SDTCisSameAs<1,2>]>,
 404                             [SDNPCommutative]>;
 405
 406 def X86VPermilpv  : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
 407 def X86VPermilpi  : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
 408 def X86VPermv     : SDNode<"X86ISD::VPERMV",
 409                            SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<1>,
 410                                                 SDTCisSameNumEltsAs<0,1>,
 411                                                 SDTCisSameSizeAs<0,1>,
 412                                                 SDTCisSameAs<0,2>]>>;
 413 def X86VPermi     : SDNode<"X86ISD::VPERMI",    SDTShuff2OpI>;
 414 def X86VPermt2     : SDNode<"X86ISD::VPERMV3",
 415                     SDTypeProfile<1, 3, [SDTCisVec<0>,
 416                                          SDTCisSameAs<0,1>, SDTCisInt<2>,
 417                                          SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>,
 418                                          SDTCisSameSizeAs<0,2>,
 419                                          SDTCisSameAs<0,3>]>, []>;
 420
 421 def X86vpternlog  : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
 422
 423 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
 424
 425 def X86VFixupimm   : SDNode<"X86ISD::VFIXUPIMM", SDTFPTernaryOpImmRound>;
 426 def X86VFixupimmScalar   : SDNode<"X86ISD::VFIXUPIMMS", SDTFPTernaryOpImmRound>;
 427 def X86VRange      : SDNode<"X86ISD::VRANGE",        SDTFPBinOpImm>;
 428 def X86VRangeRnd   : SDNode<"X86ISD::VRANGE_RND",    SDTFPBinOpImmRound>;
 429 def X86VReduce     : SDNode<"X86ISD::VREDUCE",       SDTFPUnaryOpImm>;
 430 def X86VReduceRnd  : SDNode<"X86ISD::VREDUCE_RND",   SDTFPUnaryOpImmRound>;
 431 def X86VRndScale   : SDNode<"X86ISD::VRNDSCALE",     SDTFPUnaryOpImm>;
 432 def X86VRndScaleRnd: SDNode<"X86ISD::VRNDSCALE_RND", SDTFPUnaryOpImmRound>;
 433 def X86VGetMant    : SDNode<"X86ISD::VGETMANT",      SDTFPUnaryOpImm>;
 434 def X86VGetMantRnd : SDNode<"X86ISD::VGETMANT_RND",  SDTFPUnaryOpImmRound>;
 435 def X86Vfpclass    : SDNode<"X86ISD::VFPCLASS",
 436                        SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i1>,
 437                                             SDTCisFP<1>,
 438                                             SDTCisSameNumEltsAs<0,1>,
 439                                             SDTCisVT<2, i32>]>, []>;
 440 def X86Vfpclasss   : SDNode<"X86ISD::VFPCLASSS",
 441                        SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
 442                                             SDTCisFP<1>, SDTCisVT<2, i32>]>,[]>;
 443
 444 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
 445                     SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 446                                          SDTCisSubVecOfVec<1, 0>]>, []>;
 447
 448 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
 449 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
 450
 451 def X86Blendi    : SDNode<"X86ISD::BLENDI",   SDTBlend>;
 452 def X86Blendv    : SDNode<"X86ISD::BLENDV",
 453                      SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<1>,
 454                                           SDTCisSameAs<0, 2>,
 455                                           SDTCisSameAs<2, 3>,
 456                                           SDTCisSameNumEltsAs<0, 1>,
 457                                           SDTCisSameSizeAs<0, 1>]>>;
 458
 459 def X86Addsub    : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
 460
 461 def X86faddRnd   : SDNode<"X86ISD::FADD_RND",  SDTFPBinOpRound>;
 462 def X86faddRnds  : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
 463 def X86fsubRnd   : SDNode<"X86ISD::FSUB_RND",  SDTFPBinOpRound>;
 464 def X86fsubRnds  : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>;
 465 def X86fmulRnd   : SDNode<"X86ISD::FMUL_RND",  SDTFPBinOpRound>;
 466 def X86fmulRnds  : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>;
 467 def X86fdivRnd   : SDNode<"X86ISD::FDIV_RND",  SDTFPBinOpRound>;
 468 def X86fdivRnds  : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>;
 469 def X86fmaxRnd   : SDNode<"X86ISD::FMAX_RND",  SDTFPBinOpRound>;
 470 def X86fmaxRnds  : SDNode<"X86ISD::FMAXS_RND", SDTFPBinOpRound>;
 471 def X86fminRnd   : SDNode<"X86ISD::FMIN_RND",  SDTFPBinOpRound>;
 472 def X86fminRnds  : SDNode<"X86ISD::FMINS_RND", SDTFPBinOpRound>;
 473 def X86scalef    : SDNode<"X86ISD::SCALEF",         SDTFPBinOpRound>;
 474 def X86scalefs   : SDNode<"X86ISD::SCALEFS",        SDTFPBinOpRound>;
 475 def X86fsqrtRnd     : SDNode<"X86ISD::FSQRT_RND",   SDTFPUnaryOpRound>;
 476 def X86fsqrtRnds    : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
 477 def X86fgetexpRnd   : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
 478 def X86fgetexpRnds  : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>;
 479
 480 def X86Fmadd     : SDNode<"ISD::FMA",          SDTFPTernaryOp, [SDNPCommutative]>;
 481 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFPTernaryOp, [SDNPCommutative]>;
 482 def X86Fmsub     : SDNode<"X86ISD::FMSUB",     SDTFPTernaryOp, [SDNPCommutative]>;
 483 def X86Fnmsub    : SDNode<"X86ISD::FNMSUB",    SDTFPTernaryOp, [SDNPCommutative]>;
 484 def X86Fmaddsub  : SDNode<"X86ISD::FMADDSUB",  SDTFPTernaryOp, [SDNPCommutative]>;
 485 def X86Fmsubadd  : SDNode<"X86ISD::FMSUBADD",  SDTFPTernaryOp, [SDNPCommutative]>;
 486
 487 def X86FmaddRnd     : SDNode<"X86ISD::FMADD_RND",     SDTFmaRound, [SDNPCommutative]>;
 488 def X86FnmaddRnd    : SDNode<"X86ISD::FNMADD_RND",    SDTFmaRound, [SDNPCommutative]>;
 489 def X86FmsubRnd     : SDNode<"X86ISD::FMSUB_RND",     SDTFmaRound, [SDNPCommutative]>;
 490 def X86FnmsubRnd    : SDNode<"X86ISD::FNMSUB_RND",    SDTFmaRound, [SDNPCommutative]>;
 491 def X86FmaddsubRnd  : SDNode<"X86ISD::FMADDSUB_RND",  SDTFmaRound, [SDNPCommutative]>;
 492 def X86FmsubaddRnd  : SDNode<"X86ISD::FMSUBADD_RND",  SDTFmaRound, [SDNPCommutative]>;
 493
 494 def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
 495                            SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 496 def x86vpmadd52l     : SDNode<"X86ISD::VPMADD52L",     SDTIFma, [SDNPCommutative]>;
 497 def x86vpmadd52h     : SDNode<"X86ISD::VPMADD52H",     SDTIFma, [SDNPCommutative]>;
 498
 499 def X86rsqrt14   : SDNode<"X86ISD::RSQRT14",  SDTFPUnaryOp>;
 500 def X86rcp14     : SDNode<"X86ISD::RCP14",    SDTFPUnaryOp>;
 501
 502 // VNNI
 503 def SDTVnni : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
 504                                    SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
 505 def X86Vpdpbusd  : SDNode<"X86ISD::VPDPBUSD", SDTVnni>;
 506 def X86Vpdpbusds : SDNode<"X86ISD::VPDPBUSDS", SDTVnni>;
 507 def X86Vpdpwssd  : SDNode<"X86ISD::VPDPWSSD", SDTVnni>;
 508 def X86Vpdpwssds : SDNode<"X86ISD::VPDPWSSDS", SDTVnni>;
 509
 510 def X86rsqrt28   : SDNode<"X86ISD::RSQRT28",  SDTFPUnaryOpRound>;
 511 def X86rcp28     : SDNode<"X86ISD::RCP28",    SDTFPUnaryOpRound>;
 512 def X86exp2      : SDNode<"X86ISD::EXP2",     SDTFPUnaryOpRound>;
 513
 514 def X86rsqrt14s  : SDNode<"X86ISD::RSQRT14S",   SDTFPBinOp>;
 515 def X86rcp14s    : SDNode<"X86ISD::RCP14S",     SDTFPBinOp>;
 516 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28S",   SDTFPBinOpRound>;
 517 def X86rcp28s    : SDNode<"X86ISD::RCP28S",     SDTFPBinOpRound>;
 518 def X86Ranges    : SDNode<"X86ISD::VRANGES",    SDTFPBinOpImm>;
 519 def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImm>;
 520 def X86Reduces   : SDNode<"X86ISD::VREDUCES",   SDTFPBinOpImm>;
 521 def X86GetMants  : SDNode<"X86ISD::VGETMANTS",  SDTFPBinOpImm>;
 522 def X86RangesRnd    : SDNode<"X86ISD::VRANGES_RND",    SDTFPBinOpImmRound>;
 523 def X86RndScalesRnd : SDNode<"X86ISD::VRNDSCALES_RND", SDTFPBinOpImmRound>;
 524 def X86ReducesRnd   : SDNode<"X86ISD::VREDUCES_RND",   SDTFPBinOpImmRound>;
 525 def X86GetMantsRnd  : SDNode<"X86ISD::VGETMANTS_RND",  SDTFPBinOpImmRound>;
 526
 527 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
 528                               [SDTCisSameAs<0, 1>, SDTCisVec<1>,
 529                                SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
 530                                SDTCisSameNumEltsAs<0, 3>]>, []>;
 531 def X86expand  : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
 532                               [SDTCisSameAs<0, 1>, SDTCisVec<1>,
 533                                SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>,
 534                                SDTCisSameNumEltsAs<0, 3>]>, []>;
 535
 536 // vpshufbitqmb
 537 def X86Vpshufbitqmb : SDNode<"X86ISD::VPSHUFBITQMB",
 538                              SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 539                                                   SDTCisSameAs<1,2>,
 540                                                   SDTCVecEltisVT<0,i1>,
 541                                                   SDTCisSameNumEltsAs<0,1>]>>;
 542
 543 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
 544                                           SDTCisSameAs<0,1>, SDTCisInt<2>,
 545                                           SDTCisVT<3, i32>]>;
 546
 547 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 548                                         SDTCisInt<0>, SDTCisFP<1>]>;
 549 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 550                                            SDTCisInt<0>, SDTCisFP<1>,
 551                                            SDTCisVT<2, i32>]>;
 552 def SDTSFloatToInt: SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisFP<1>,
 553                                          SDTCisVec<1>]>;
 554 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
 555                                             SDTCisVec<1>, SDTCisVT<2, i32>]>;
 556
 557 def SDTVintToFP: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
 558                                       SDTCisFP<0>, SDTCisInt<1>]>;
 559 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
 560                                            SDTCisFP<0>, SDTCisInt<1>,
 561                                            SDTCisVT<2, i32>]>;
 562
 563 // Scalar
 564 def X86SintToFpRnd  : SDNode<"X86ISD::SCALAR_SINT_TO_FP_RND",  SDTintToFPRound>;
 565 def X86UintToFpRnd  : SDNode<"X86ISD::SCALAR_UINT_TO_FP_RND",  SDTintToFPRound>;
 566
 567 def X86cvtts2Int  : SDNode<"X86ISD::CVTTS2SI",  SDTSFloatToInt>;
 568 def X86cvtts2UInt : SDNode<"X86ISD::CVTTS2UI",  SDTSFloatToInt>;
 569 def X86cvtts2IntRnd  : SDNode<"X86ISD::CVTTS2SI_RND",  SDTSFloatToIntRnd>;
 570 def X86cvtts2UIntRnd : SDNode<"X86ISD::CVTTS2UI_RND",  SDTSFloatToIntRnd>;
 571
 572 def X86cvts2si  : SDNode<"X86ISD::CVTS2SI", SDTSFloatToInt>;
 573 def X86cvts2usi : SDNode<"X86ISD::CVTS2UI", SDTSFloatToInt>;
 574 def X86cvts2siRnd  : SDNode<"X86ISD::CVTS2SI_RND", SDTSFloatToIntRnd>;
 575 def X86cvts2usiRnd : SDNode<"X86ISD::CVTS2UI_RND", SDTSFloatToIntRnd>;
 576
 577 // Vector with rounding mode
 578
 579 // cvtt fp-to-int staff
 580 def X86cvttp2siRnd    : SDNode<"X86ISD::CVTTP2SI_RND", SDTFloatToIntRnd>;
 581 def X86cvttp2uiRnd    : SDNode<"X86ISD::CVTTP2UI_RND", SDTFloatToIntRnd>;
 582
 583 def X86VSintToFpRnd   : SDNode<"X86ISD::SINT_TO_FP_RND",  SDTVintToFPRound>;
 584 def X86VUintToFpRnd   : SDNode<"X86ISD::UINT_TO_FP_RND",  SDTVintToFPRound>;
 585
 586 // cvt fp-to-int staff
 587 def X86cvtp2IntRnd      : SDNode<"X86ISD::CVTP2SI_RND",  SDTFloatToIntRnd>;
 588 def X86cvtp2UIntRnd     : SDNode<"X86ISD::CVTP2UI_RND",  SDTFloatToIntRnd>;
 589
 590 // Vector without rounding mode
 591
 592 // cvtt fp-to-int staff
 593 def X86cvttp2si      : SDNode<"X86ISD::CVTTP2SI",  SDTFloatToInt>;
 594 def X86cvttp2ui      : SDNode<"X86ISD::CVTTP2UI",  SDTFloatToInt>;
 595
 596 def X86VSintToFP      : SDNode<"X86ISD::CVTSI2P",  SDTVintToFP>;
 597 def X86VUintToFP      : SDNode<"X86ISD::CVTUI2P",  SDTVintToFP>;
 598
 599 // cvt int-to-fp staff
 600 def X86cvtp2Int      : SDNode<"X86ISD::CVTP2SI",  SDTFloatToInt>;
 601 def X86cvtp2UInt     : SDNode<"X86ISD::CVTP2UI",  SDTFloatToInt>;
 602
 603
 604 // Masked versions of above
 605 def SDTMVintToFP: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 606                                        SDTCisFP<0>, SDTCisInt<1>,
 607                                        SDTCisSameSizeAs<0, 1>,
 608                                        SDTCisSameAs<0, 2>,
 609                                        SDTCVecEltisVT<3, i1>,
 610                                        SDTCisSameNumEltsAs<1, 3>]>;
 611 def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 612                                          SDTCisInt<0>, SDTCisFP<1>,
 613                                          SDTCisSameSizeAs<0, 1>,
 614                                          SDTCisSameAs<0, 2>,
 615                                          SDTCVecEltisVT<3, i1>,
 616                                          SDTCisSameNumEltsAs<1, 3>]>;
 617
 618 def X86VMSintToFP    : SDNode<"X86ISD::MCVTSI2P",  SDTMVintToFP>;
 619 def X86VMUintToFP    : SDNode<"X86ISD::MCVTUI2P",  SDTMVintToFP>;
 620
 621 def X86mcvtp2Int     : SDNode<"X86ISD::MCVTP2SI",  SDTMFloatToInt>;
 622 def X86mcvtp2UInt    : SDNode<"X86ISD::MCVTP2UI",  SDTMFloatToInt>;
 623 def X86mcvttp2si     : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>;
 624 def X86mcvttp2ui     : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>;
 625
 626
 627 def X86cvtph2ps     : SDNode<"X86ISD::CVTPH2PS",
 628                               SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
 629                                                    SDTCVecEltisVT<1, i16>]> >;
 630
 631 def X86cvtph2psRnd  : SDNode<"X86ISD::CVTPH2PS_RND",
 632                               SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 633                                                    SDTCVecEltisVT<1, i16>,
 634                                                    SDTCisVT<2, i32>]> >;
 635
 636 def X86cvtps2ph   : SDNode<"X86ISD::CVTPS2PH",
 637                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>,
 638                                              SDTCVecEltisVT<1, f32>,
 639                                              SDTCisVT<2, i32>]> >;
 640 def X86mcvtps2ph   : SDNode<"X86ISD::MCVTPS2PH",
 641                         SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>,
 642                                              SDTCVecEltisVT<1, f32>,
 643                                              SDTCisVT<2, i32>,
 644                                              SDTCisSameAs<0, 3>,
 645                                              SDTCVecEltisVT<4, i1>,
 646                                              SDTCisSameNumEltsAs<1, 4>]> >;
 647 def X86vfpextRnd  : SDNode<"X86ISD::VFPEXT_RND",
 648                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f64>,
 649                                              SDTCVecEltisVT<1, f32>,
 650                                              SDTCisOpSmallerThanOp<1, 0>,
 651                                              SDTCisVT<2, i32>]>>;
 652 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
 653                         SDTypeProfile<1, 2, [SDTCVecEltisVT<0, f32>,
 654                                              SDTCVecEltisVT<1, f64>,
 655                                              SDTCisOpSmallerThanOp<0, 1>,
 656                                              SDTCisVT<2, i32>]>>;
 657
 658 // galois field arithmetic
 659 def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>;
 660 def X86GF2P8affineqb    : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>;
 661 def X86GF2P8mulb        : SDNode<"X86ISD::GF2P8MULB", SDTIntBinOp>;
 662
 663 //===----------------------------------------------------------------------===//
 664 // SSE Complex Patterns
 665 //===----------------------------------------------------------------------===//
 666
 667 // These are 'extloads' from a scalar to the low element of a vector, zeroing
 668 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 669 // forms.
 670 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
 671                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 672                                    SDNPWantRoot, SDNPWantParent]>;
 673 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
 674                                   [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
 675                                    SDNPWantRoot, SDNPWantParent]>;
 676
 677 def ssmem : Operand<v4f32> {
 678   let PrintMethod = "printf32mem";
 679   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 680   let ParserMatchClass = X86Mem32AsmOperand;
 681   let OperandType = "OPERAND_MEMORY";
 682 }
 683 def sdmem : Operand<v2f64> {
 684   let PrintMethod = "printf64mem";
 685   let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG);
 686   let ParserMatchClass = X86Mem64AsmOperand;
 687   let OperandType = "OPERAND_MEMORY";
 688 }
 689
 690 //===----------------------------------------------------------------------===//
 691 // SSE pattern fragments
 692 //===----------------------------------------------------------------------===//
 693
 694 // 128-bit load pattern fragments
 695 def loadv4f32    : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
 696 def loadv2f64    : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
 697 def loadv2i64    : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
 698 def loadv4i32    : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
 699 def loadv8i16    : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
 700 def loadv16i8    : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
 701
 702 // 256-bit load pattern fragments
 703 def loadv8f32    : PatFrag<(ops node:$ptr), (v8f32  (load node:$ptr))>;
 704 def loadv4f64    : PatFrag<(ops node:$ptr), (v4f64  (load node:$ptr))>;
 705 def loadv4i64    : PatFrag<(ops node:$ptr), (v4i64  (load node:$ptr))>;
 706 def loadv8i32    : PatFrag<(ops node:$ptr), (v8i32  (load node:$ptr))>;
 707 def loadv16i16   : PatFrag<(ops node:$ptr), (v16i16 (load node:$ptr))>;
 708 def loadv32i8    : PatFrag<(ops node:$ptr), (v32i8  (load node:$ptr))>;
 709
 710 // 512-bit load pattern fragments
 711 def loadv16f32   : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
 712 def loadv8f64    : PatFrag<(ops node:$ptr), (v8f64  (load node:$ptr))>;
 713 def loadv8i64    : PatFrag<(ops node:$ptr), (v8i64  (load node:$ptr))>;
 714 def loadv16i32   : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
 715 def loadv32i16   : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
 716 def loadv64i8    : PatFrag<(ops node:$ptr), (v64i8  (load node:$ptr))>;
 717
 718 // 128-/256-/512-bit extload pattern fragments
 719 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
 720 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
 721 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
 722
 723 // Like 'store', but always requires vector size alignment.
 724 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
 725                            (store node:$val, node:$ptr), [{
 726   auto *St = cast<StoreSDNode>(N);
 727   return St->getAlignment() >= St->getMemoryVT().getStoreSize();
 728 }]>;
 729
 730 // Like 'load', but always requires vector size alignment.
 731 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 732   auto *Ld = cast<LoadSDNode>(N);
 733   return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
 734 }]>;
 735
 736 // 128-bit aligned load pattern fragments
 737 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 738 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
 739                                (v4f32 (alignedload node:$ptr))>;
 740 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
 741                                (v2f64 (alignedload node:$ptr))>;
 742 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
 743                                (v2i64 (alignedload node:$ptr))>;
 744 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
 745                                (v4i32 (alignedload node:$ptr))>;
 746 def alignedloadv8i16 : PatFrag<(ops node:$ptr),
 747                                (v8i16 (alignedload node:$ptr))>;
 748 def alignedloadv16i8 : PatFrag<(ops node:$ptr),
 749                                (v16i8 (alignedload node:$ptr))>;
 750
 751 // 256-bit aligned load pattern fragments
 752 // NOTE: all 256-bit integer vector loads are promoted to v4i64
 753 def alignedloadv8f32  : PatFrag<(ops node:$ptr),
 754                                 (v8f32  (alignedload node:$ptr))>;
 755 def alignedloadv4f64  : PatFrag<(ops node:$ptr),
 756                                 (v4f64  (alignedload node:$ptr))>;
 757 def alignedloadv4i64  : PatFrag<(ops node:$ptr),
 758                                 (v4i64  (alignedload node:$ptr))>;
 759 def alignedloadv8i32  : PatFrag<(ops node:$ptr),
 760                                 (v8i32  (alignedload node:$ptr))>;
 761 def alignedloadv16i16 : PatFrag<(ops node:$ptr),
 762                                 (v16i16 (alignedload node:$ptr))>;
 763 def alignedloadv32i8  : PatFrag<(ops node:$ptr),
 764                                 (v32i8  (alignedload node:$ptr))>;
 765
 766 // 512-bit aligned load pattern fragments
 767 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
 768                                 (v16f32 (alignedload node:$ptr))>;
 769 def alignedloadv8f64  : PatFrag<(ops node:$ptr),
 770                                 (v8f64  (alignedload node:$ptr))>;
 771 def alignedloadv8i64  : PatFrag<(ops node:$ptr),
 772                                 (v8i64  (alignedload node:$ptr))>;
 773 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
 774                                 (v16i32 (alignedload node:$ptr))>;
 775 def alignedloadv32i16 : PatFrag<(ops node:$ptr),
 776                                 (v32i16 (alignedload node:$ptr))>;
 777 def alignedloadv64i8  : PatFrag<(ops node:$ptr),
 778                                 (v64i8  (alignedload node:$ptr))>;
 779
 780 // Like 'load', but uses special alignment checks suitable for use in
 781 // memory operands in most SSE instructions, which are required to
 782 // be naturally aligned on some targets but not on others.  If the subtarget
 783 // allows unaligned accesses, match any load, though this may require
 784 // setting a feature bit in the processor (on startup, for example).
 785 // Opteron 10h and later implement such a feature.
 786 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
 787   auto *Ld = cast<LoadSDNode>(N);
 788   return Subtarget->hasSSEUnalignedMem() ||
 789          Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
 790 }]>;
 791
 792 // 128-bit memop pattern fragments
 793 // NOTE: all 128-bit integer vector loads are promoted to v2i64
 794 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
 795 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
 796 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
 797 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
 798 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
 799 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
 800
 801 def X86masked_gather : SDNode<"X86ISD::MGATHER",
 802                               SDTypeProfile<2, 3, [SDTCisVec<0>,
 803                                                    SDTCisVec<1>, SDTCisInt<1>,
 804                                                    SDTCisSameAs<0, 2>,
 805                                                    SDTCisSameAs<1, 3>,
 806                                                    SDTCisPtrTy<4>]>,
 807                              [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 808
 809 def X86masked_scatter : SDNode<"X86ISD::MSCATTER",
 810                               SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
 811                                                    SDTCisSameAs<0, 2>,
 812                                                    SDTCVecEltisVT<0, i1>,
 813                                                    SDTCisPtrTy<3>]>,
 814                              [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 815
 816 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 817   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 818   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 819   return Mgt->getIndex().getValueType() == MVT::v4i32;
 820 }]>;
 821
 822 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 823   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 824   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 825   return Mgt->getIndex().getValueType() == MVT::v8i32;
 826 }]>;
 827
 828 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 829   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 830   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 831   return Mgt->getIndex().getValueType() == MVT::v2i64;
 832 }]>;
 833 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 834   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 835   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 836   return Mgt->getIndex().getValueType() == MVT::v4i64;
 837 }]>;
 838 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 839   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 840   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 841   return Mgt->getIndex().getValueType() == MVT::v8i64;
 842 }]>;
 843 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 844   (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
 845   X86MaskedGatherSDNode *Mgt = cast<X86MaskedGatherSDNode>(N);
 846   return Mgt->getIndex().getValueType() == MVT::v16i32;
 847 }]>;
 848
 849 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 850   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 851   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 852   return Sc->getIndex().getValueType() == MVT::v2i64;
 853 }]>;
 854
 855 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 856   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 857   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 858   return Sc->getIndex().getValueType() == MVT::v4i32;
 859 }]>;
 860
 861 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 862   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 863   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 864   return Sc->getIndex().getValueType() == MVT::v4i64;
 865 }]>;
 866
 867 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 868   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 869   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 870   return Sc->getIndex().getValueType() == MVT::v8i32;
 871 }]>;
 872
 873 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 874   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 875   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 876   return Sc->getIndex().getValueType() == MVT::v8i64;
 877 }]>;
 878 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 879   (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
 880   X86MaskedScatterSDNode *Sc = cast<X86MaskedScatterSDNode>(N);
 881   return Sc->getIndex().getValueType() == MVT::v16i32;
 882 }]>;
 883
 884 // 128-bit bitconvert pattern fragments
 885 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
 886 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
 887 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
 888 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
 889 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
 890 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
 891
 892 // 256-bit bitconvert pattern fragments
 893 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
 894 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
 895 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
 896 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
 897 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
 898 def bc_v4f64 : PatFrag<(ops node:$in), (v4f64 (bitconvert node:$in))>;
 899
 900 // 512-bit bitconvert pattern fragments
 901 def bc_v64i8 : PatFrag<(ops node:$in), (v64i8 (bitconvert node:$in))>;
 902 def bc_v32i16 : PatFrag<(ops node:$in), (v32i16 (bitconvert node:$in))>;
 903 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
 904 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
 905 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
 906 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
 907
 908 def vzmovl_v2i64 : PatFrag<(ops node:$src),
 909                            (bitconvert (v2i64 (X86vzmovl
 910                              (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
 911 def vzmovl_v4i32 : PatFrag<(ops node:$src),
 912                            (bitconvert (v4i32 (X86vzmovl
 913                              (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
 914
 915 def vzload_v2i64 : PatFrag<(ops node:$src),
 916                            (bitconvert (v2i64 (X86vzload node:$src)))>;
 917
 918
 919 def fp32imm0 : PatLeaf<(f32 fpimm), [{
 920   return N->isExactlyValue(+0.0);
 921 }]>;
 922
 923 def fp64imm0 : PatLeaf<(f64 fpimm), [{
 924   return N->isExactlyValue(+0.0);
 925 }]>;
 926
 927 def I8Imm : SDNodeXForm<imm, [{
 928   // Transformation function: get the low 8 bits.
 929   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 930 }]>;
 931
 932 def FROUND_NO_EXC : PatLeaf<(i32 8)>;
 933 def FROUND_CURRENT : PatLeaf<(i32 4)>;
 934
 935 // BYTE_imm - Transform bit immediates into byte immediates.
 936 def BYTE_imm  : SDNodeXForm<imm, [{
 937   // Transformation function: imm >> 3
 938   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 939 }]>;
 940
 941 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
 942 // to VEXTRACTF128/VEXTRACTI128 imm.
 943 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
 944   return getExtractVEXTRACTImmediate(N, 128, SDLoc(N));
 945 }]>;
 946
 947 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
 948 // VINSERTF128/VINSERTI128 imm.
 949 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
 950   return getInsertVINSERTImmediate(N, 128, SDLoc(N));
 951 }]>;
 952
 953 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
 954 // to VEXTRACTF64x4 imm.
 955 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
 956   return getExtractVEXTRACTImmediate(N, 256, SDLoc(N));
 957 }]>;
 958
 959 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
 960 // VINSERTF64x4 imm.
 961 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
 962   return getInsertVINSERTImmediate(N, 256, SDLoc(N));
 963 }]>;
 964
 965 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
 966                                    (extract_subvector node:$bigvec,
 967                                                       node:$index), [{}],
 968                                   EXTRACT_get_vextract128_imm>;
 969
 970 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 971                                       node:$index),
 972                                  (insert_subvector node:$bigvec, node:$smallvec,
 973                                                    node:$index), [{}],
 974                                 INSERT_get_vinsert128_imm>;
 975
 976 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
 977                                    (extract_subvector node:$bigvec,
 978                                                       node:$index), [{}],
 979                                   EXTRACT_get_vextract256_imm>;
 980
 981 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
 982                                       node:$index),
 983                                  (insert_subvector node:$bigvec, node:$smallvec,
 984                                                    node:$index), [{}],
 985                                 INSERT_get_vinsert256_imm>;
 986
 987 def X86mload : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 988                          (masked_load node:$src1, node:$src2, node:$src3), [{
 989   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
 990     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
 991 }]>;
 992
 993 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 994                          (X86mload node:$src1, node:$src2, node:$src3), [{
 995   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 16;
 996 }]>;
 997
 998 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
 999                          (X86mload node:$src1, node:$src2, node:$src3), [{
1000   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 32;
1001 }]>;
1002
1003 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1004                          (X86mload node:$src1, node:$src2, node:$src3), [{
1005   return cast<MaskedLoadSDNode>(N)->getAlignment() >= 64;
1006 }]>;
1007
1008 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1009                          (masked_load node:$src1, node:$src2, node:$src3), [{
1010   return !cast<MaskedLoadSDNode>(N)->isExpandingLoad() &&
1011     cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
1012 }]>;
1013
1014 def X86mExpandingLoad : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1015                          (masked_load node:$src1, node:$src2, node:$src3), [{
1016   return cast<MaskedLoadSDNode>(N)->isExpandingLoad();
1017 }]>;
1018
1019 // Masked store fragments.
1020 // X86mstore can't be implemented in core DAG files because some targets
1021 // do not support vector types (llvm-tblgen will fail).
1022 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1023                         (masked_store node:$src1, node:$src2, node:$src3), [{
1024   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1025          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1026 }]>;
1027
1028 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1029                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1030   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 16;
1031 }]>;
1032
1033 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1034                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1035   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 32;
1036 }]>;
1037
1038 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1039                          (X86mstore node:$src1, node:$src2, node:$src3), [{
1040   return cast<MaskedStoreSDNode>(N)->getAlignment() >= 64;
1041 }]>;
1042
1043 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1044                          (masked_store node:$src1, node:$src2, node:$src3), [{
1045   return (!cast<MaskedStoreSDNode>(N)->isTruncatingStore()) &&
1046          (!cast<MaskedStoreSDNode>(N)->isCompressingStore());
1047 }]>;
1048
1049 def X86mCompressingStore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1050                              (masked_store node:$src1, node:$src2, node:$src3), [{
1051     return cast<MaskedStoreSDNode>(N)->isCompressingStore();
1052 }]>;
1053
1054 // masked truncstore fragments
1055 // X86mtruncstore can't be implemented in core DAG files because some targets
1056 // doesn't support vector type ( llvm-tblgen will fail)
1057 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1058                              (masked_store node:$src1, node:$src2, node:$src3), [{
1059     return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
1060 }]>;
1061 def masked_truncstorevi8 :
1062   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1063           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1064   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1065 }]>;
1066 def masked_truncstorevi16 :
1067   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1068           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1069   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1070 }]>;
1071 def masked_truncstorevi32 :
1072   PatFrag<(ops node:$src1, node:$src2, node:$src3),
1073           (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
1074   return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1075 }]>;
1076
1077 def X86TruncSStore : SDNode<"X86ISD::VTRUNCSTORES",  SDTStore,
1078                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1079
1080 def X86TruncUSStore : SDNode<"X86ISD::VTRUNCSTOREUS",  SDTStore,
1081                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1082
1083 def X86MTruncSStore : SDNode<"X86ISD::VMTRUNCSTORES",  SDTMaskedStore,
1084                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1085
1086 def X86MTruncUSStore : SDNode<"X86ISD::VMTRUNCSTOREUS",  SDTMaskedStore,
1087                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
1088
1089 def truncstore_s_vi8 : PatFrag<(ops node:$val, node:$ptr),
1090                                (X86TruncSStore node:$val, node:$ptr), [{
1091   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1092 }]>;
1093
1094 def truncstore_us_vi8 : PatFrag<(ops node:$val, node:$ptr),
1095                                (X86TruncUSStore node:$val, node:$ptr), [{
1096   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1097 }]>;
1098
1099 def truncstore_s_vi16 : PatFrag<(ops node:$val, node:$ptr),
1100                                (X86TruncSStore node:$val, node:$ptr), [{
1101   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1102 }]>;
1103
1104 def truncstore_us_vi16 : PatFrag<(ops node:$val, node:$ptr),
1105                                (X86TruncUSStore node:$val, node:$ptr), [{
1106   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1107 }]>;
1108
1109 def truncstore_s_vi32 : PatFrag<(ops node:$val, node:$ptr),
1110                                (X86TruncSStore node:$val, node:$ptr), [{
1111   return cast<TruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1112 }]>;
1113
1114 def truncstore_us_vi32 : PatFrag<(ops node:$val, node:$ptr),
1115                                (X86TruncUSStore node:$val, node:$ptr), [{
1116   return cast<TruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1117 }]>;
1118
1119 def masked_truncstore_s_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1120                      (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1121   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1122 }]>;
1123
1124 def masked_truncstore_us_vi8 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1125                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1126   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
1127 }]>;
1128
1129 def masked_truncstore_s_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1130                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1131   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1132 }]>;
1133
1134 def masked_truncstore_us_vi16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1135                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1136   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
1137 }]>;
1138
1139 def masked_truncstore_s_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1140                                (X86MTruncSStore node:$src1, node:$src2, node:$src3), [{
1141   return cast<MaskedTruncSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1142 }]>;
1143
1144 def masked_truncstore_us_vi32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
1145                                (X86MTruncUSStore node:$src1, node:$src2, node:$src3), [{
1146   return cast<MaskedTruncUSStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
1147 }]>;