lib/Target/X86/X86MacroFusion.cpp

   1 //===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file This file contains the X86 implementation of the DAG scheduling
  10 /// mutation to pair instructions back to back.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86MacroFusion.h"
  15 #include "X86Subtarget.h"
  16 #include "llvm/CodeGen/MacroFusion.h"
  17 #include "llvm/CodeGen/TargetInstrInfo.h"
  18
  19 using namespace llvm;
  20
  21 /// Check if the instr pair, FirstMI and SecondMI, should be fused
  22 /// together. Given SecondMI, when FirstMI is unspecified, then check if
  23 /// SecondMI may be part of a fused pair at all.
  24 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
  25                                    const TargetSubtargetInfo &TSI,
  26                                    const MachineInstr *FirstMI,
  27                                    const MachineInstr &SecondMI) {
  28   const X86Subtarget &ST = static_cast<const X86Subtarget&>(TSI);
  29   // Check if this processor supports macro-fusion.
  30   if (!ST.hasMacroFusion())
  31     return false;
  32
  33   enum {
  34     FuseTest,
  35     FuseCmp,
  36     FuseInc
  37   } FuseKind;
  38
  39   unsigned FirstOpcode = FirstMI
  40                          ? FirstMI->getOpcode()
  41                          : static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
  42   unsigned SecondOpcode = SecondMI.getOpcode();
  43
  44   switch (SecondOpcode) {
  45   default:
  46     return false;
  47   case X86::JE_1:
  48   case X86::JNE_1:
  49   case X86::JL_1:
  50   case X86::JLE_1:
  51   case X86::JG_1:
  52   case X86::JGE_1:
  53     FuseKind = FuseInc;
  54     break;
  55   case X86::JB_1:
  56   case X86::JBE_1:
  57   case X86::JA_1:
  58   case X86::JAE_1:
  59     FuseKind = FuseCmp;
  60     break;
  61   case X86::JS_1:
  62   case X86::JNS_1:
  63   case X86::JP_1:
  64   case X86::JNP_1:
  65   case X86::JO_1:
  66   case X86::JNO_1:
  67     FuseKind = FuseTest;
  68     break;
  69   }
  70
  71   switch (FirstOpcode) {
  72   default:
  73     return false;
  74   case X86::TEST8rr:
  75   case X86::TEST16rr:
  76   case X86::TEST32rr:
  77   case X86::TEST64rr:
  78   case X86::TEST8ri:
  79   case X86::TEST16ri:
  80   case X86::TEST32ri:
  81   case X86::TEST64ri32:
  82   case X86::TEST8mr:
  83   case X86::TEST16mr:
  84   case X86::TEST32mr:
  85   case X86::TEST64mr:
  86   case X86::AND16ri:
  87   case X86::AND16ri8:
  88   case X86::AND16rm:
  89   case X86::AND16rr:
  90   case X86::AND32ri:
  91   case X86::AND32ri8:
  92   case X86::AND32rm:
  93   case X86::AND32rr:
  94   case X86::AND64ri32:
  95   case X86::AND64ri8:
  96   case X86::AND64rm:
  97   case X86::AND64rr:
  98   case X86::AND8ri:
  99   case X86::AND8rm:
 100   case X86::AND8rr:
 101     return true;
 102   case X86::CMP16ri:
 103   case X86::CMP16ri8:
 104   case X86::CMP16rm:
 105   case X86::CMP16rr:
 106   case X86::CMP16mr:
 107   case X86::CMP32ri:
 108   case X86::CMP32ri8:
 109   case X86::CMP32rm:
 110   case X86::CMP32rr:
 111   case X86::CMP32mr:
 112   case X86::CMP64ri32:
 113   case X86::CMP64ri8:
 114   case X86::CMP64rm:
 115   case X86::CMP64rr:
 116   case X86::CMP64mr:
 117   case X86::CMP8ri:
 118   case X86::CMP8rm:
 119   case X86::CMP8rr:
 120   case X86::CMP8mr:
 121   case X86::ADD16ri:
 122   case X86::ADD16ri8:
 123   case X86::ADD16ri8_DB:
 124   case X86::ADD16ri_DB:
 125   case X86::ADD16rm:
 126   case X86::ADD16rr:
 127   case X86::ADD16rr_DB:
 128   case X86::ADD32ri:
 129   case X86::ADD32ri8:
 130   case X86::ADD32ri8_DB:
 131   case X86::ADD32ri_DB:
 132   case X86::ADD32rm:
 133   case X86::ADD32rr:
 134   case X86::ADD32rr_DB:
 135   case X86::ADD64ri32:
 136   case X86::ADD64ri32_DB:
 137   case X86::ADD64ri8:
 138   case X86::ADD64ri8_DB:
 139   case X86::ADD64rm:
 140   case X86::ADD64rr:
 141   case X86::ADD64rr_DB:
 142   case X86::ADD8ri:
 143   case X86::ADD8rm:
 144   case X86::ADD8rr:
 145   case X86::SUB16ri:
 146   case X86::SUB16ri8:
 147   case X86::SUB16rm:
 148   case X86::SUB16rr:
 149   case X86::SUB32ri:
 150   case X86::SUB32ri8:
 151   case X86::SUB32rm:
 152   case X86::SUB32rr:
 153   case X86::SUB64ri32:
 154   case X86::SUB64ri8:
 155   case X86::SUB64rm:
 156   case X86::SUB64rr:
 157   case X86::SUB8ri:
 158   case X86::SUB8rm:
 159   case X86::SUB8rr:
 160     return FuseKind == FuseCmp || FuseKind == FuseInc;
 161   case X86::INC16r:
 162   case X86::INC32r:
 163   case X86::INC64r:
 164   case X86::INC8r:
 165   case X86::DEC16r:
 166   case X86::DEC32r:
 167   case X86::DEC64r:
 168   case X86::DEC8r:
 169     return FuseKind == FuseInc;
 170   case X86::INSTRUCTION_LIST_END:
 171     return true;
 172   }
 173 }
 174
 175 namespace llvm {
 176
 177 std::unique_ptr<ScheduleDAGMutation>
 178 createX86MacroFusionDAGMutation () {
 179   return createBranchMacroFusionDAGMutation(shouldScheduleAdjacent);
 180 }
 181
 182 } // end namespace llvm