lib/Target/X86/X86SchedBroadwell.td

   1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Broadwell to support instruction
  10 // scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def BroadwellModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and BW can decode 4
  16   // instructions per cycle.
  17   let IssueWidth = 4;
  18   let MicroOpBufferSize = 192; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 16;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = BroadwellModel in {
  31
  32 // Broadwell can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def BWPort0 : ProcResource<1>;
  41 def BWPort1 : ProcResource<1>;
  42 def BWPort2 : ProcResource<1>;
  43 def BWPort3 : ProcResource<1>;
  44 def BWPort4 : ProcResource<1>;
  45 def BWPort5 : ProcResource<1>;
  46 def BWPort6 : ProcResource<1>;
  47 def BWPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def BWPort01  : ProcResGroup<[BWPort0, BWPort1]>;
  51 def BWPort23  : ProcResGroup<[BWPort2, BWPort3]>;
  52 def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
  53 def BWPort04  : ProcResGroup<[BWPort0, BWPort4]>;
  54 def BWPort05  : ProcResGroup<[BWPort0, BWPort5]>;
  55 def BWPort06  : ProcResGroup<[BWPort0, BWPort6]>;
  56 def BWPort15  : ProcResGroup<[BWPort1, BWPort5]>;
  57 def BWPort16  : ProcResGroup<[BWPort1, BWPort6]>;
  58 def BWPort56  : ProcResGroup<[BWPort5, BWPort6]>;
  59 def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
  60 def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
  61 def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
  62
  63 // 60 Entry Unified Scheduler
  64 def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
  65                               BWPort5, BWPort6, BWPort7]> {
  66   let BufferSize=60;
  67 }
  68
  69 // Integer division issued on port 0.
  70 def BWDivider : ProcResource<1>;
  71 // FP division and sqrt on port 0.
  72 def BWFPDivider : ProcResource<1>;
  73
  74 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available
  79 // until 5/5/6 cycles after the memory operand.
  80 def : ReadAdvance<ReadAfterVecLd, 5>;
  81 def : ReadAdvance<ReadAfterVecXLd, 5>;
  82 def : ReadAdvance<ReadAfterVecYLd, 6>;
  83
  84 def : ReadAdvance<ReadInt2Fpu, 0>;
  85
  86 // Many SchedWrites are defined in pairs with and without a folded load.
  87 // Instructions with folded loads are usually micro-fused, so they only appear
  88 // as two micro-ops when queued in the reservation station.
  89 // This multiclass defines the resource usage for variants with and without
  90 // folded loads.
  91 multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
  92                           list<ProcResourceKind> ExePorts,
  93                           int Lat, list<int> Res = [1], int UOps = 1,
  94                           int LoadLat = 5> {
  95   // Register variant is using a single cycle on ExePort.
  96   def : WriteRes<SchedRW, ExePorts> {
  97     let Latency = Lat;
  98     let ResourceCycles = Res;
  99     let NumMicroOps = UOps;
 100   }
 101
 102   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 103   // the latency (default = 5).
 104   def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
 105     let Latency = !add(Lat, LoadLat);
 106     let ResourceCycles = !listconcat([1], Res);
 107     let NumMicroOps = !add(UOps, 1);
 108   }
 109 }
 110
 111 // A folded store needs a cycle on port 4 for the store data, and an extra port
 112 // 2/3/7 cycle to recompute the address.
 113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
 114
 115 // Arithmetic.
 116 defm : BWWriteResPair<WriteALU,    [BWPort0156], 1>; // Simple integer ALU op.
 117 defm : BWWriteResPair<WriteADC,    [BWPort06], 1>; // Integer ALU + flags op.
 118
 119 // Integer multiplication.
 120 defm : BWWriteResPair<WriteIMul8,     [BWPort1],   3>;
 121 defm : BWWriteResPair<WriteIMul16,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>;
 122 defm : X86WriteRes<WriteIMul16Imm,    [BWPort1,BWPort0156], 4, [1,1], 2>;
 123 defm : X86WriteRes<WriteIMul16ImmLd,  [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>;
 124 defm : BWWriteResPair<WriteIMul16Reg, [BWPort1],   3>;
 125 defm : BWWriteResPair<WriteIMul32,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
 126 defm : BWWriteResPair<WriteIMul32Imm, [BWPort1],   3>;
 127 defm : BWWriteResPair<WriteIMul32Reg, [BWPort1],   3>;
 128 defm : BWWriteResPair<WriteIMul64,    [BWPort1,BWPort5], 4, [1,1], 2>;
 129 defm : BWWriteResPair<WriteIMul64Imm, [BWPort1],   3>;
 130 defm : BWWriteResPair<WriteIMul64Reg, [BWPort1],   3>;
 131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 132
 133 // TODO: Why isn't the BWDivider used consistently?
 134 defm : X86WriteRes<WriteDiv8,      [BWPort0, BWDivider], 25, [1, 10], 1>;
 135 defm : X86WriteRes<WriteDiv16,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 136 defm : X86WriteRes<WriteDiv32,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 137 defm : X86WriteRes<WriteDiv64,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 138 defm : X86WriteRes<WriteDiv8Ld,    [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 139 defm : X86WriteRes<WriteDiv16Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 140 defm : X86WriteRes<WriteDiv32Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 141 defm : X86WriteRes<WriteDiv64Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 142
 143 defm : X86WriteRes<WriteIDiv8,     [BWPort0, BWDivider], 25, [1,10], 1>;
 144 defm : X86WriteRes<WriteIDiv16,    [BWPort0, BWDivider], 25, [1,10], 1>;
 145 defm : X86WriteRes<WriteIDiv32,    [BWPort0, BWDivider], 25, [1,10], 1>;
 146 defm : X86WriteRes<WriteIDiv64,    [BWPort0, BWDivider], 25, [1,10], 1>;
 147 defm : X86WriteRes<WriteIDiv8Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 148 defm : X86WriteRes<WriteIDiv16Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 149 defm : X86WriteRes<WriteIDiv32Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 150 defm : X86WriteRes<WriteIDiv64Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 151
 152 defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>;
 153 defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>;
 154 defm : X86WriteRes<WriteBSWAP32,   [BWPort15], 1, [1], 1>;
 155 defm : X86WriteRes<WriteBSWAP64,   [BWPort06, BWPort15], 2, [1, 1], 2>;
 156 defm : X86WriteRes<WriteXCHG,      [BWPort0156], 2, [3], 3>;
 157
 158 defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 159
 160 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
 161
 162 defm : BWWriteResPair<WriteCMOV,  [BWPort06], 1>; // Conditional move.
 163 defm : BWWriteResPair<WriteCMOV2, [BWPort06,BWPort0156], 2, [1,1], 2>; // // Conditional (CF + ZF flag) move.
 164 defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move.
 165
 166 def  : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
 167 def  : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
 168   let Latency = 2;
 169   let NumMicroOps = 3;
 170 }
 171
 172 defm : X86WriteRes<WriteLAHFSAHF,        [BWPort06], 1, [1], 1>;
 173 defm : X86WriteRes<WriteBitTest,         [BWPort06], 1, [1], 1>; // Bit Test instrs
 174 defm : X86WriteRes<WriteBitTestImmLd,    [BWPort06,BWPort23], 6, [1,1], 2>;
 175 defm : X86WriteRes<WriteBitTestRegLd,    [BWPort0156,BWPort23], 6, [1,1], 2>;
 176 defm : X86WriteRes<WriteBitTestSet,      [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
 177 defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>;
 178 defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>;
 179
 180 // Bit counts.
 181 defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
 182 defm : BWWriteResPair<WriteBSR, [BWPort1], 3>;
 183 defm : BWWriteResPair<WriteLZCNT,          [BWPort1], 3>;
 184 defm : BWWriteResPair<WriteTZCNT,          [BWPort1], 3>;
 185 defm : BWWriteResPair<WritePOPCNT,         [BWPort1], 3>;
 186
 187 // Integer shifts and rotates.
 188 defm : BWWriteResPair<WriteShift,    [BWPort06],  1>;
 189 defm : BWWriteResPair<WriteShiftCL,  [BWPort06,BWPort0156],  3, [2,1], 3>;
 190 defm : BWWriteResPair<WriteRotate,   [BWPort06],  2, [2], 2>;
 191 defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156],  3, [2,1], 3>;
 192
 193 // SHLD/SHRD.
 194 defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;
 195 defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>;
 196 defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>;
 197 defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>;
 198
 199 // BMI1 BEXTR/BLS, BMI2 BZHI
 200 defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
 201 defm : BWWriteResPair<WriteBLS,   [BWPort15], 1>;
 202 defm : BWWriteResPair<WriteBZHI,  [BWPort15], 1>;
 203
 204 // Loads, stores, and moves, not folded with other operations.
 205 defm : X86WriteRes<WriteLoad,    [BWPort23], 5, [1], 1>;
 206 defm : X86WriteRes<WriteStore,   [BWPort237, BWPort4], 1, [1,1], 1>;
 207 defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>;
 208 defm : X86WriteRes<WriteMove,    [BWPort0156], 1, [1], 1>;
 209
 210 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 211 // These can often bypass execution ports completely.
 212 def : WriteRes<WriteZero,  []>;
 213
 214 // Treat misc copies as a move.
 215 def : InstRW<[WriteMove], (instrs COPY)>;
 216
 217 // Branches don't produce values, so they have no latency, but they still
 218 // consume resources. Indirect branches can fold loads.
 219 defm : BWWriteResPair<WriteJump,  [BWPort06],   1>;
 220
 221 // Floating point. This covers both scalar and vector operations.
 222 defm : X86WriteRes<WriteFLD0,          [BWPort01], 1, [1], 1>;
 223 defm : X86WriteRes<WriteFLD1,          [BWPort01], 1, [2], 2>;
 224 defm : X86WriteRes<WriteFLDC,          [BWPort01], 1, [2], 2>;
 225 defm : X86WriteRes<WriteFLoad,         [BWPort23], 5, [1], 1>;
 226 defm : X86WriteRes<WriteFLoadX,        [BWPort23], 5, [1], 1>;
 227 defm : X86WriteRes<WriteFLoadY,        [BWPort23], 6, [1], 1>;
 228 defm : X86WriteRes<WriteFMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 229 defm : X86WriteRes<WriteFMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 230 defm : X86WriteRes<WriteFStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 231 defm : X86WriteRes<WriteFStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 232 defm : X86WriteRes<WriteFStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 233 defm : X86WriteRes<WriteFStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 234 defm : X86WriteRes<WriteFStoreNTX,     [BWPort237,BWPort4], 1, [1,1], 2>;
 235 defm : X86WriteRes<WriteFStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 236 defm : X86WriteRes<WriteFMaskedStore,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 237 defm : X86WriteRes<WriteFMaskedStoreY, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 238 defm : X86WriteRes<WriteFMove,         [BWPort5], 1, [1], 1>;
 239 defm : X86WriteRes<WriteFMoveX,        [BWPort5], 1, [1], 1>;
 240 defm : X86WriteRes<WriteFMoveY,        [BWPort5], 1, [1], 1>;
 241
 242 defm : BWWriteResPair<WriteFAdd,    [BWPort1],  3, [1], 1, 5>; // Floating point add/sub.
 243 defm : BWWriteResPair<WriteFAddX,   [BWPort1],  3, [1], 1, 5>; // Floating point add/sub (XMM).
 244 defm : BWWriteResPair<WriteFAddY,   [BWPort1],  3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
 245 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 246 defm : BWWriteResPair<WriteFAdd64,  [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub.
 247 defm : BWWriteResPair<WriteFAdd64X, [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub (XMM).
 248 defm : BWWriteResPair<WriteFAdd64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
 249 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 250
 251 defm : BWWriteResPair<WriteFCmp,    [BWPort1],  3, [1], 1, 5>; // Floating point compare.
 252 defm : BWWriteResPair<WriteFCmpX,   [BWPort1],  3, [1], 1, 5>; // Floating point compare (XMM).
 253 defm : BWWriteResPair<WriteFCmpY,   [BWPort1],  3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
 254 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 255 defm : BWWriteResPair<WriteFCmp64,  [BWPort1],  3, [1], 1, 5>; // Floating point double compare.
 256 defm : BWWriteResPair<WriteFCmp64X, [BWPort1],  3, [1], 1, 5>; // Floating point double compare (XMM).
 257 defm : BWWriteResPair<WriteFCmp64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
 258 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 259
 260 defm : BWWriteResPair<WriteFCom,    [BWPort1],  3>; // Floating point compare to flags.
 261
 262 defm : BWWriteResPair<WriteFMul,    [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
 263 defm : BWWriteResPair<WriteFMulX,   [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
 264 defm : BWWriteResPair<WriteFMulY,   [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
 265 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 266 defm : BWWriteResPair<WriteFMul64,  [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication.
 267 defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
 268 defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
 269 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 270
 271 //defm : BWWriteResPair<WriteFDiv,     [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 272 defm : BWWriteResPair<WriteFDivX,    [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
 273 defm : BWWriteResPair<WriteFDivY,    [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
 274 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 275 //defm : BWWriteResPair<WriteFDiv64,   [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division.
 276 defm : BWWriteResPair<WriteFDiv64X,  [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
 277 defm : BWWriteResPair<WriteFDiv64Y,  [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
 278 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 279
 280 defm : X86WriteRes<WriteFSqrt,       [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root.
 281 defm : X86WriteRes<WriteFSqrtLd,     [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>;
 282 defm : BWWriteResPair<WriteFSqrtX,   [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM).
 283 defm : BWWriteResPair<WriteFSqrtY,   [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
 284 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 285 defm : X86WriteRes<WriteFSqrt64,     [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root.
 286 defm : X86WriteRes<WriteFSqrt64Ld,   [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>;
 287 defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM).
 288 defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
 289 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 290 defm : BWWriteResPair<WriteFSqrt80,  [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root.
 291
 292 defm : BWWriteResPair<WriteFRcp,   [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate.
 293 defm : BWWriteResPair<WriteFRcpX,  [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate (XMM).
 294 defm : BWWriteResPair<WriteFRcpY,  [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM).
 295 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 296
 297 defm : BWWriteResPair<WriteFRsqrt, [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate.
 298 defm : BWWriteResPair<WriteFRsqrtX,[BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM).
 299 defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM).
 300 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 301
 302 defm : BWWriteResPair<WriteFMA,    [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add.
 303 defm : BWWriteResPair<WriteFMAX,   [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
 304 defm : BWWriteResPair<WriteFMAY,   [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM).
 305 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 306 defm : BWWriteResPair<WriteDPPD,   [BWPort0,BWPort1,BWPort5],  9, [1,1,1], 3, 5>; // Floating point double dot product.
 307 defm : BWWriteResPair<WriteDPPS,   [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product.
 308 defm : BWWriteResPair<WriteDPPSY,  [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM).
 309 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 310 defm : BWWriteResPair<WriteFSign,     [BWPort5], 1>; // Floating point fabs/fchs.
 311 defm : X86WriteRes<WriteFRnd,            [BWPort23],  6, [1],   1>; // Floating point rounding.
 312 defm : X86WriteRes<WriteFRndY,           [BWPort23],  6, [1],   1>; // Floating point rounding (YMM/ZMM).
 313 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 314 defm : X86WriteRes<WriteFRndLd,  [BWPort1,BWPort23], 11, [2,1], 3>;
 315 defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>;
 316 defm : BWWriteResPair<WriteFLogic,    [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals.
 317 defm : BWWriteResPair<WriteFLogicY,   [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM).
 318 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 319 defm : BWWriteResPair<WriteFTest,     [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions.
 320 defm : BWWriteResPair<WriteFTestY,    [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM).
 321 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 322 defm : BWWriteResPair<WriteFShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles.
 323 defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM).
 324 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 325 defm : BWWriteResPair<WriteFVarShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles.
 326 defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 327 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 328 defm : BWWriteResPair<WriteFBlend,  [BWPort015], 1, [1], 1, 5>; // Floating point vector blends.
 329 defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends.
 330 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 331 defm : BWWriteResPair<WriteFVarBlend,  [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends.
 332 defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends.
 333 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 334
 335 // FMA Scheduling helper class.
 336 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 337
 338 // Vector integer operations.
 339 defm : X86WriteRes<WriteVecLoad,         [BWPort23], 5, [1], 1>;
 340 defm : X86WriteRes<WriteVecLoadX,        [BWPort23], 5, [1], 1>;
 341 defm : X86WriteRes<WriteVecLoadY,        [BWPort23], 6, [1], 1>;
 342 defm : X86WriteRes<WriteVecLoadNT,       [BWPort23], 5, [1], 1>;
 343 defm : X86WriteRes<WriteVecLoadNTY,      [BWPort23], 6, [1], 1>;
 344 defm : X86WriteRes<WriteVecMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 345 defm : X86WriteRes<WriteVecMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 346 defm : X86WriteRes<WriteVecStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 347 defm : X86WriteRes<WriteVecStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 348 defm : X86WriteRes<WriteVecStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 349 defm : X86WriteRes<WriteVecStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 351 defm : X86WriteRes<WriteVecMaskedStore,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 352 defm : X86WriteRes<WriteVecMaskedStoreY, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 353 defm : X86WriteRes<WriteVecMove,         [BWPort015], 1, [1], 1>;
 354 defm : X86WriteRes<WriteVecMoveX,        [BWPort015], 1, [1], 1>;
 355 defm : X86WriteRes<WriteVecMoveY,        [BWPort015], 1, [1], 1>;
 356 defm : X86WriteRes<WriteVecMoveToGpr,    [BWPort0], 1, [1], 1>;
 357 defm : X86WriteRes<WriteVecMoveFromGpr,  [BWPort5], 1, [1], 1>;
 358
 359 defm : X86WriteRes<WriteEMMS,            [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>;
 360
 361 defm : BWWriteResPair<WriteVecALU,   [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 362 defm : BWWriteResPair<WriteVecALUX,  [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 363 defm : BWWriteResPair<WriteVecALUY,  [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM).
 364 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 365 defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 366 defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 367 defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM).
 368 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 369 defm : BWWriteResPair<WriteVecTest,  [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions.
 370 defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM).
 371 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 372 defm : BWWriteResPair<WriteVecIMul,  [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 373 defm : BWWriteResPair<WriteVecIMulX, [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 374 defm : BWWriteResPair<WriteVecIMulY, [BWPort0],  5, [1], 1, 6>; // Vector integer multiply.
 375 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 376 defm : BWWriteResPair<WritePMULLD,   [BWPort0], 10, [2], 2, 5>; // Vector PMULLD.
 377 defm : BWWriteResPair<WritePMULLDY,  [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM).
 378 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 379 defm : BWWriteResPair<WriteShuffle,  [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 380 defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 381 defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM).
 382 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 383 defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 384 defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 385 defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM).
 386 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 387 defm : BWWriteResPair<WriteBlend,  [BWPort5], 1, [1], 1, 5>; // Vector blends.
 388 defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM).
 389 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 390 defm : BWWriteResPair<WriteVarBlend,  [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
 391 defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
 392 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 393 defm : BWWriteResPair<WriteMPSAD,  [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
 394 defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD.
 395 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 396 defm : BWWriteResPair<WritePSADBW,   [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 397 defm : BWWriteResPair<WritePSADBWX,  [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 398 defm : BWWriteResPair<WritePSADBWY,  [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM).
 399 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 400 defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
 401
 402 // Vector integer shifts.
 403 defm : BWWriteResPair<WriteVecShift,     [BWPort0], 1, [1], 1, 5>;
 404 defm : BWWriteResPair<WriteVecShiftX,    [BWPort0,BWPort5],  2, [1,1], 2, 5>;
 405 defm : X86WriteRes<WriteVecShiftY,       [BWPort0,BWPort5],  4, [1,1], 2>;
 406 defm : X86WriteRes<WriteVecShiftYLd,     [BWPort0,BWPort23], 7, [1,1], 2>;
 407 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 408
 409 defm : BWWriteResPair<WriteVecShiftImm,  [BWPort0],  1, [1], 1, 5>;
 410 defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0],  1, [1], 1, 5>; // Vector integer immediate shifts (XMM).
 411 defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0],  1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM).
 412 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 413 defm : BWWriteResPair<WriteVarVecShift,  [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts.
 414 defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM).
 415 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 416
 417 // Vector insert/extract operations.
 418 def : WriteRes<WriteVecInsert, [BWPort5]> {
 419   let Latency = 2;
 420   let NumMicroOps = 2;
 421   let ResourceCycles = [2];
 422 }
 423 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
 424   let Latency = 6;
 425   let NumMicroOps = 2;
 426 }
 427
 428 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
 429   let Latency = 2;
 430   let NumMicroOps = 2;
 431 }
 432 def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
 433   let Latency = 2;
 434   let NumMicroOps = 3;
 435 }
 436
 437 // Conversion between integer and float.
 438 defm : BWWriteResPair<WriteCvtSS2I,   [BWPort1], 3>;
 439 defm : BWWriteResPair<WriteCvtPS2I,   [BWPort1], 3>;
 440 defm : BWWriteResPair<WriteCvtPS2IY,  [BWPort1], 3>;
 441 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 442 defm : BWWriteResPair<WriteCvtSD2I,   [BWPort1], 3>;
 443 defm : BWWriteResPair<WriteCvtPD2I,   [BWPort1], 3>;
 444 defm : BWWriteResPair<WriteCvtPD2IY,  [BWPort1], 3>;
 445 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 446
 447 defm : BWWriteResPair<WriteCvtI2SS,   [BWPort1], 4>;
 448 defm : BWWriteResPair<WriteCvtI2PS,   [BWPort1], 4>;
 449 defm : BWWriteResPair<WriteCvtI2PSY,  [BWPort1], 4>;
 450 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 451 defm : BWWriteResPair<WriteCvtI2SD,   [BWPort1], 4>;
 452 defm : BWWriteResPair<WriteCvtI2PD,   [BWPort1], 4>;
 453 defm : BWWriteResPair<WriteCvtI2PDY,  [BWPort1], 4>;
 454 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 455
 456 defm : BWWriteResPair<WriteCvtSS2SD,  [BWPort1], 3>;
 457 defm : BWWriteResPair<WriteCvtPS2PD,  [BWPort1], 3>;
 458 defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>;
 459 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 460 defm : BWWriteResPair<WriteCvtSD2SS,  [BWPort1], 3>;
 461 defm : BWWriteResPair<WriteCvtPD2PS,  [BWPort1], 3>;
 462 defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>;
 463 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 464
 465 defm : X86WriteRes<WriteCvtPH2PS,     [BWPort0,BWPort5], 2, [1,1], 2>;
 466 defm : X86WriteRes<WriteCvtPH2PSY,    [BWPort0,BWPort5], 2, [1,1], 2>;
 467 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 468 defm : X86WriteRes<WriteCvtPH2PSLd,  [BWPort0,BWPort23], 6, [1,1], 2>;
 469 defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>;
 470 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 471
 472 defm : X86WriteRes<WriteCvtPS2PH,    [BWPort1,BWPort5], 4, [1,1], 2>;
 473 defm : X86WriteRes<WriteCvtPS2PHY,   [BWPort1,BWPort5], 6, [1,1], 2>;
 474 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 475 defm : X86WriteRes<WriteCvtPS2PHSt,  [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>;
 476 defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>;
 477 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 478
 479 // Strings instructions.
 480
 481 // Packed Compare Implicit Length Strings, Return Mask
 482 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
 483   let Latency = 11;
 484   let NumMicroOps = 3;
 485   let ResourceCycles = [3];
 486 }
 487 def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
 488   let Latency = 16;
 489   let NumMicroOps = 4;
 490   let ResourceCycles = [3,1];
 491 }
 492
 493 // Packed Compare Explicit Length Strings, Return Mask
 494 def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
 495   let Latency = 19;
 496   let NumMicroOps = 9;
 497   let ResourceCycles = [4,3,1,1];
 498 }
 499 def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
 500   let Latency = 24;
 501   let NumMicroOps = 10;
 502   let ResourceCycles = [4,3,1,1,1];
 503 }
 504
 505 // Packed Compare Implicit Length Strings, Return Index
 506 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
 507   let Latency = 11;
 508   let NumMicroOps = 3;
 509   let ResourceCycles = [3];
 510 }
 511 def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
 512   let Latency = 16;
 513   let NumMicroOps = 4;
 514   let ResourceCycles = [3,1];
 515 }
 516
 517 // Packed Compare Explicit Length Strings, Return Index
 518 def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
 519   let Latency = 18;
 520   let NumMicroOps = 8;
 521   let ResourceCycles = [4,3,1];
 522 }
 523 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
 524   let Latency = 23;
 525   let NumMicroOps = 9;
 526   let ResourceCycles = [4,3,1,1];
 527 }
 528
 529 // MOVMSK Instructions.
 530 def : WriteRes<WriteFMOVMSK,    [BWPort0]> { let Latency = 3; }
 531 def : WriteRes<WriteVecMOVMSK,  [BWPort0]> { let Latency = 3; }
 532 def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; }
 533 def : WriteRes<WriteMMXMOVMSK,  [BWPort0]> { let Latency = 1; }
 534
 535 // AES instructions.
 536 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
 537   let Latency = 7;
 538   let NumMicroOps = 1;
 539   let ResourceCycles = [1];
 540 }
 541 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
 542   let Latency = 12;
 543   let NumMicroOps = 2;
 544   let ResourceCycles = [1,1];
 545 }
 546
 547 def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
 548   let Latency = 14;
 549   let NumMicroOps = 2;
 550   let ResourceCycles = [2];
 551 }
 552 def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
 553   let Latency = 19;
 554   let NumMicroOps = 3;
 555   let ResourceCycles = [2,1];
 556 }
 557
 558 def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
 559   let Latency = 29;
 560   let NumMicroOps = 11;
 561   let ResourceCycles = [2,7,2];
 562 }
 563 def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
 564   let Latency = 33;
 565   let NumMicroOps = 11;
 566   let ResourceCycles = [2,7,1,1];
 567 }
 568
 569 // Carry-less multiplication instructions.
 570 defm : BWWriteResPair<WriteCLMul,  [BWPort0], 5>;
 571
 572 // Catch-all for expensive system instructions.
 573 def : WriteRes<WriteSystem,     [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 574
 575 // AVX2.
 576 defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles.
 577 defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles.
 578 defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector shuffles.
 579 defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector variable shuffles.
 580
 581 // Old microcoded instructions that nobody use.
 582 def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 583
 584 // Fence instructions.
 585 def : WriteRes<WriteFence,  [BWPort23, BWPort4]>;
 586
 587 // Load/store MXCSR.
 588 def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 589 def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 590
 591 // Nop, not very useful expect it provides a model for nops!
 592 def : WriteRes<WriteNop, []>;
 593
 594 ////////////////////////////////////////////////////////////////////////////////
 595 // Horizontal add/sub  instructions.
 596 ////////////////////////////////////////////////////////////////////////////////
 597
 598 defm : BWWriteResPair<WriteFHAdd,   [BWPort1,BWPort5], 5, [1,2], 3, 5>;
 599 defm : BWWriteResPair<WriteFHAddY,  [BWPort1,BWPort5], 5, [1,2], 3, 6>;
 600 defm : BWWriteResPair<WritePHAdd,  [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 601 defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 602 defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
 603
 604 // Remaining instrs.
 605
 606 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
 607   let Latency = 1;
 608   let NumMicroOps = 1;
 609   let ResourceCycles = [1];
 610 }
 611 def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
 612                                            "VPSRLVQ(Y?)rr")>;
 613
 614 def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
 615   let Latency = 1;
 616   let NumMicroOps = 1;
 617   let ResourceCycles = [1];
 618 }
 619 def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
 620                                            "UCOM_F(P?)r")>;
 621
 622 def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
 623   let Latency = 1;
 624   let NumMicroOps = 1;
 625   let ResourceCycles = [1];
 626 }
 627 def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
 628
 629 def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
 630   let Latency = 1;
 631   let NumMicroOps = 1;
 632   let ResourceCycles = [1];
 633 }
 634 def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 635
 636 def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
 637   let Latency = 1;
 638   let NumMicroOps = 1;
 639   let ResourceCycles = [1];
 640 }
 641 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
 642
 643 def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
 644   let Latency = 1;
 645   let NumMicroOps = 1;
 646   let ResourceCycles = [1];
 647 }
 648 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
 649
 650 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
 651   let Latency = 1;
 652   let NumMicroOps = 1;
 653   let ResourceCycles = [1];
 654 }
 655 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
 656
 657 def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
 658   let Latency = 1;
 659   let NumMicroOps = 1;
 660   let ResourceCycles = [1];
 661 }
 662 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
 663
 664 def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
 665   let Latency = 1;
 666   let NumMicroOps = 1;
 667   let ResourceCycles = [1];
 668 }
 669 def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
 670                                         SIDT64m,
 671                                         SMSW16m,
 672                                         STRm,
 673                                         SYSCALL)>;
 674
 675 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
 676   let Latency = 1;
 677   let NumMicroOps = 2;
 678   let ResourceCycles = [1,1];
 679 }
 680 def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
 681 def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
 682
 683 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
 684   let Latency = 2;
 685   let NumMicroOps = 2;
 686   let ResourceCycles = [2];
 687 }
 688 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
 689
 690 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
 691   let Latency = 2;
 692   let NumMicroOps = 2;
 693   let ResourceCycles = [2];
 694 }
 695 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
 696                                          MFENCE,
 697                                          WAIT,
 698                                          XGETBV)>;
 699
 700 def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
 701   let Latency = 2;
 702   let NumMicroOps = 2;
 703   let ResourceCycles = [1,1];
 704 }
 705 def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr",
 706                                             "(V?)CVTSS2SDrr")>;
 707
 708 def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
 709   let Latency = 2;
 710   let NumMicroOps = 2;
 711   let ResourceCycles = [1,1];
 712 }
 713 def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
 714
 715 def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
 716   let Latency = 2;
 717   let NumMicroOps = 2;
 718   let ResourceCycles = [1,1];
 719 }
 720 def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
 721
 722 def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
 723   let Latency = 2;
 724   let NumMicroOps = 2;
 725   let ResourceCycles = [1,1];
 726 }
 727 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
 728
 729 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
 730   let Latency = 2;
 731   let NumMicroOps = 2;
 732   let ResourceCycles = [1,1];
 733 }
 734 def: InstRW<[BWWriteResGroup20], (instrs CWD,
 735                                          JCXZ, JECXZ, JRCXZ,
 736                                          ADC8i8, SBB8i8)>;
 737 def: InstRW<[BWWriteResGroup20], (instregex "ADC8ri",
 738                                             "SBB8ri",
 739                                             "SET(A|BE)r")>;
 740
 741 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
 742   let Latency = 2;
 743   let NumMicroOps = 3;
 744   let ResourceCycles = [1,1,1];
 745 }
 746 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
 747
 748 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
 749   let Latency = 2;
 750   let NumMicroOps = 3;
 751   let ResourceCycles = [1,1,1];
 752 }
 753 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
 754
 755 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 756   let Latency = 2;
 757   let NumMicroOps = 3;
 758   let ResourceCycles = [1,1,1];
 759 }
 760 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 761                                          STOSB, STOSL, STOSQ, STOSW)>;
 762 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
 763
 764 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
 765   let Latency = 3;
 766   let NumMicroOps = 1;
 767   let ResourceCycles = [1];
 768 }
 769 def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>;
 770 def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr",
 771                                             "(V?)CVTDQ2PS(Y?)rr")>;
 772
 773 def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
 774   let Latency = 3;
 775   let NumMicroOps = 1;
 776   let ResourceCycles = [1];
 777 }
 778 def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
 779                                          VPBROADCASTWrr)>;
 780
 781 def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
 782   let Latency = 3;
 783   let NumMicroOps = 3;
 784   let ResourceCycles = [2,1];
 785 }
 786 def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr,
 787                                          MMX_PACKSSWBirr,
 788                                          MMX_PACKUSWBirr)>;
 789
 790 def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
 791   let Latency = 3;
 792   let NumMicroOps = 3;
 793   let ResourceCycles = [1,2];
 794 }
 795 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
 796
 797 def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
 798   let Latency = 3;
 799   let NumMicroOps = 3;
 800   let ResourceCycles = [1,2];
 801 }
 802 def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)",
 803                                             "RCR(8|16|32|64)r(1|i)")>;
 804
 805 def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
 806   let Latency = 3;
 807   let NumMicroOps = 4;
 808   let ResourceCycles = [1,1,1,1];
 809 }
 810 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
 811
 812 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
 813   let Latency = 3;
 814   let NumMicroOps = 4;
 815   let ResourceCycles = [1,1,1,1];
 816 }
 817 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
 818 def: InstRW<[BWWriteResGroup38], (instregex "SET(A|BE)m")>;
 819
 820 def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
 821   let Latency = 4;
 822   let NumMicroOps = 2;
 823   let ResourceCycles = [1,1];
 824 }
 825 def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
 826                                             "(V?)CVT(T?)SD2SIrr",
 827                                             "(V?)CVT(T?)SS2SI64rr",
 828                                             "(V?)CVT(T?)SS2SIrr")>;
 829
 830 def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
 831   let Latency = 4;
 832   let NumMicroOps = 2;
 833   let ResourceCycles = [1,1];
 834 }
 835 def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>;
 836
 837 def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
 838   let Latency = 4;
 839   let NumMicroOps = 2;
 840   let ResourceCycles = [1,1];
 841 }
 842 def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
 843
 844 def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
 845   let Latency = 4;
 846   let NumMicroOps = 2;
 847   let ResourceCycles = [1,1];
 848 }
 849 def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>;
 850 def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr",
 851                                             "MMX_CVT(T?)PS2PIirr",
 852                                             "(V?)CVTDQ2PDrr",
 853                                             "(V?)CVTPD2PSrr",
 854                                             "(V?)CVTSD2SSrr",
 855                                             "(V?)CVTSI642SDrr",
 856                                             "(V?)CVTSI2SDrr",
 857                                             "(V?)CVTSI2SSrr",
 858                                             "(V?)CVT(T?)PD2DQrr")>;
 859
 860 def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
 861   let Latency = 4;
 862   let NumMicroOps = 3;
 863   let ResourceCycles = [1,1,1];
 864 }
 865 def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
 866
 867 def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
 868   let Latency = 4;
 869   let NumMicroOps = 3;
 870   let ResourceCycles = [1,1,1];
 871 }
 872 def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
 873                                             "IST_F(16|32)m")>;
 874
 875 def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
 876   let Latency = 4;
 877   let NumMicroOps = 4;
 878   let ResourceCycles = [4];
 879 }
 880 def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
 881
 882 def BWWriteResGroup46 : SchedWriteRes<[]> {
 883   let Latency = 0;
 884   let NumMicroOps = 4;
 885   let ResourceCycles = [];
 886 }
 887 def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
 888
 889 def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
 890   let Latency = 5;
 891   let NumMicroOps = 1;
 892   let ResourceCycles = [1];
 893 }
 894 def: InstRW<[BWWriteResGroup47], (instregex "(V?)PCMPGTQ(Y?)rr",
 895                                             "MUL_(FPrST0|FST0r|FrST0)")>;
 896
 897 def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
 898   let Latency = 5;
 899   let NumMicroOps = 1;
 900   let ResourceCycles = [1];
 901 }
 902 def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)",
 903                                             "MOVZX(16|32|64)rm(8|16)")>;
 904 def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
 905                                          VMOVDDUPrm, MOVDDUPrm,
 906                                          VMOVSHDUPrm, MOVSHDUPrm,
 907                                          VMOVSLDUPrm, MOVSLDUPrm,
 908                                          VPBROADCASTDrm,
 909                                          VPBROADCASTQrm)>;
 910
 911 def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
 912   let Latency = 5;
 913   let NumMicroOps = 3;
 914   let ResourceCycles = [1,2];
 915 }
 916 def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
 917
 918 def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
 919   let Latency = 5;
 920   let NumMicroOps = 3;
 921   let ResourceCycles = [1,1,1];
 922 }
 923 def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
 924
 925 def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
 926   let Latency = 5;
 927   let NumMicroOps = 5;
 928   let ResourceCycles = [1,4];
 929 }
 930 def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
 931
 932 def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
 933   let Latency = 5;
 934   let NumMicroOps = 5;
 935   let ResourceCycles = [1,4];
 936 }
 937 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
 938
 939 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 940   let Latency = 5;
 941   let NumMicroOps = 6;
 942   let ResourceCycles = [1,1,4];
 943 }
 944 def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
 945
 946 def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
 947   let Latency = 6;
 948   let NumMicroOps = 1;
 949   let ResourceCycles = [1];
 950 }
 951 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
 952 def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
 953                                          VBROADCASTI128,
 954                                          VBROADCASTSDYrm,
 955                                          VBROADCASTSSYrm,
 956                                          VMOVDDUPYrm,
 957                                          VMOVSHDUPYrm,
 958                                          VMOVSLDUPYrm,
 959                                          VPBROADCASTDYrm,
 960                                          VPBROADCASTQYrm)>;
 961
 962 def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
 963   let Latency = 6;
 964   let NumMicroOps = 2;
 965   let ResourceCycles = [1,1];
 966 }
 967 def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm,
 968                                          CVTSS2SDrm, VCVTSS2SDrm,
 969                                          VPSLLVQrm,
 970                                          VPSRLVQrm)>;
 971
 972 def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
 973   let Latency = 6;
 974   let NumMicroOps = 2;
 975   let ResourceCycles = [1,1];
 976 }
 977 def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr,
 978                                          VCVTPD2PSYrr,
 979                                          VCVTPD2DQYrr,
 980                                          VCVTTPD2DQYrr)>;
 981
 982 def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
 983   let Latency = 6;
 984   let NumMicroOps = 2;
 985   let ResourceCycles = [1,1];
 986 }
 987 def: InstRW<[BWWriteResGroup62], (instrs FARJMP64)>;
 988 def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
 989
 990 def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
 991   let Latency = 6;
 992   let NumMicroOps = 2;
 993   let ResourceCycles = [1,1];
 994 }
 995 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
 996                                             "MOVBE(16|32|64)rm")>;
 997
 998 def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
 999   let Latency = 6;
1000   let NumMicroOps = 2;
1001   let ResourceCycles = [1,1];
1002 }
1003 def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
1004                                          VINSERTI128rm,
1005                                          VPBLENDDrmi)>;
1006
1007 def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1008   let Latency = 6;
1009   let NumMicroOps = 2;
1010   let ResourceCycles = [1,1];
1011 }
1012 def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
1013 def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
1014
1015 def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1016   let Latency = 6;
1017   let NumMicroOps = 4;
1018   let ResourceCycles = [1,1,1,1];
1019 }
1020 def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1021
1022 def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1023   let Latency = 6;
1024   let NumMicroOps = 4;
1025   let ResourceCycles = [1,1,1,1];
1026 }
1027 def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
1028                                             "SHL(8|16|32|64)m(1|i)",
1029                                             "SHR(8|16|32|64)m(1|i)")>;
1030
1031 def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1032   let Latency = 6;
1033   let NumMicroOps = 4;
1034   let ResourceCycles = [1,1,1,1];
1035 }
1036 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1037                                             "PUSH(16|32|64)rmm")>;
1038
1039 def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1040   let Latency = 6;
1041   let NumMicroOps = 6;
1042   let ResourceCycles = [1,5];
1043 }
1044 def: InstRW<[BWWriteResGroup71], (instrs STD)>;
1045
1046 def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1047   let Latency = 7;
1048   let NumMicroOps = 2;
1049   let ResourceCycles = [1,1];
1050 }
1051 def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
1052                                          VPSRLVQYrm)>;
1053
1054 def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1055   let Latency = 7;
1056   let NumMicroOps = 2;
1057   let ResourceCycles = [1,1];
1058 }
1059 def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
1060
1061 def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1062   let Latency = 7;
1063   let NumMicroOps = 2;
1064   let ResourceCycles = [1,1];
1065 }
1066 def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>;
1067
1068 def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1069   let Latency = 7;
1070   let NumMicroOps = 3;
1071   let ResourceCycles = [2,1];
1072 }
1073 def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm,
1074                                          MMX_PACKSSWBirm,
1075                                          MMX_PACKUSWBirm)>;
1076
1077 def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1078   let Latency = 7;
1079   let NumMicroOps = 3;
1080   let ResourceCycles = [1,2];
1081 }
1082 def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1083                                          SCASB, SCASL, SCASQ, SCASW)>;
1084
1085 def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1086   let Latency = 7;
1087   let NumMicroOps = 3;
1088   let ResourceCycles = [1,1,1];
1089 }
1090 def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
1091
1092 def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1093   let Latency = 7;
1094   let NumMicroOps = 3;
1095   let ResourceCycles = [1,1,1];
1096 }
1097 def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>;
1098
1099 def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1100   let Latency = 7;
1101   let NumMicroOps = 5;
1102   let ResourceCycles = [1,1,1,2];
1103 }
1104 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
1105                                             "ROR(8|16|32|64)m(1|i)")>;
1106
1107 def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1108   let Latency = 7;
1109   let NumMicroOps = 5;
1110   let ResourceCycles = [1,1,1,2];
1111 }
1112 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
1113
1114 def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1115   let Latency = 7;
1116   let NumMicroOps = 5;
1117   let ResourceCycles = [1,1,1,1,1];
1118 }
1119 def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;
1120 def: InstRW<[BWWriteResGroup89], (instrs FARCALL64)>;
1121
1122 def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1123   let Latency = 7;
1124   let NumMicroOps = 7;
1125   let ResourceCycles = [2,2,1,2];
1126 }
1127 def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
1128
1129 def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1130   let Latency = 8;
1131   let NumMicroOps = 2;
1132   let ResourceCycles = [1,1];
1133 }
1134 def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm,
1135                                          CVTDQ2PSrm,
1136                                          VCVTDQ2PSrm)>;
1137 def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
1138
1139 def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1140   let Latency = 8;
1141   let NumMicroOps = 2;
1142   let ResourceCycles = [1,1];
1143 }
1144 def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
1145                                          VPMOVSXBQYrm,
1146                                          VPMOVSXBWYrm,
1147                                          VPMOVSXDQYrm,
1148                                          VPMOVSXWDYrm,
1149                                          VPMOVSXWQYrm,
1150                                          VPMOVZXWDYrm)>;
1151
1152 def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1153   let Latency = 8;
1154   let NumMicroOps = 5;
1155   let ResourceCycles = [1,1,1,2];
1156 }
1157 def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
1158                                             "RCR(8|16|32|64)m(1|i)")>;
1159
1160 def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1161   let Latency = 8;
1162   let NumMicroOps = 6;
1163   let ResourceCycles = [1,1,1,3];
1164 }
1165 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
1166
1167 def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1168   let Latency = 8;
1169   let NumMicroOps = 6;
1170   let ResourceCycles = [1,1,1,2,1];
1171 }
1172 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
1173 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
1174                                              "ROR(8|16|32|64)mCL",
1175                                              "SAR(8|16|32|64)mCL",
1176                                              "SHL(8|16|32|64)mCL",
1177                                              "SHR(8|16|32|64)mCL")>;
1178
1179 def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1180   let Latency = 9;
1181   let NumMicroOps = 2;
1182   let ResourceCycles = [1,1];
1183 }
1184 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1185                                              "ILD_F(16|32|64)m")>;
1186 def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm,
1187                                           VCVTTPS2DQYrm)>;
1188
1189 def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1190   let Latency = 9;
1191   let NumMicroOps = 3;
1192   let ResourceCycles = [1,1,1];
1193 }
1194 def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
1195                                              "(V?)CVT(T?)SD2SI64rm",
1196                                              "(V?)CVT(T?)SD2SIrm",
1197                                              "VCVTTSS2SI64rm",
1198                                              "(V?)CVTTSS2SIrm")>;
1199
1200 def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1201   let Latency = 9;
1202   let NumMicroOps = 3;
1203   let ResourceCycles = [1,1,1];
1204 }
1205 def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>;
1206
1207 def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1208   let Latency = 9;
1209   let NumMicroOps = 3;
1210   let ResourceCycles = [1,1,1];
1211 }
1212 def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm,
1213                                           CVTPD2DQrm,
1214                                           CVTTPD2DQrm,
1215                                           MMX_CVTPI2PDirm)>;
1216 def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm",
1217                                              "(V?)CVTDQ2PDrm",
1218                                              "(V?)CVTSD2SSrm")>;
1219
1220 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
1221   let Latency = 9;
1222   let NumMicroOps = 3;
1223   let ResourceCycles = [1,1,1];
1224 }
1225 def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
1226                                              "VPBROADCASTW(Y?)rm")>;
1227
1228 def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1229   let Latency = 9;
1230   let NumMicroOps = 5;
1231   let ResourceCycles = [1,1,3];
1232 }
1233 def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
1234
1235 def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1236   let Latency = 9;
1237   let NumMicroOps = 5;
1238   let ResourceCycles = [1,2,1,1];
1239 }
1240 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1241                                              "LSL(16|32|64)rm")>;
1242
1243 def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
1244   let Latency = 10;
1245   let NumMicroOps = 2;
1246   let ResourceCycles = [1,1];
1247 }
1248 def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
1249
1250 def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
1251   let Latency = 10;
1252   let NumMicroOps = 3;
1253   let ResourceCycles = [2,1];
1254 }
1255 def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
1256
1257 def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1258   let Latency = 10;
1259   let NumMicroOps = 4;
1260   let ResourceCycles = [1,1,1,1];
1261 }
1262 def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1263
1264 def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1265   let Latency = 11;
1266   let NumMicroOps = 1;
1267   let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
1268 }
1269 def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
1270
1271 def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
1272   let Latency = 11;
1273   let NumMicroOps = 2;
1274   let ResourceCycles = [1,1];
1275 }
1276 def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
1277 def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
1278
1279 def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1280   let Latency = 11;
1281   let NumMicroOps = 3;
1282   let ResourceCycles = [1,1,1];
1283 }
1284 def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>;
1285
1286 def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1287   let Latency = 11;
1288   let NumMicroOps = 7;
1289   let ResourceCycles = [2,2,3];
1290 }
1291 def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
1292                                              "RCR(16|32|64)rCL")>;
1293
1294 def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1295   let Latency = 11;
1296   let NumMicroOps = 9;
1297   let ResourceCycles = [1,4,1,3];
1298 }
1299 def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>;
1300
1301 def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
1302   let Latency = 11;
1303   let NumMicroOps = 11;
1304   let ResourceCycles = [2,9];
1305 }
1306 def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
1307 def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
1308
1309 def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
1310   let Latency = 12;
1311   let NumMicroOps = 3;
1312   let ResourceCycles = [2,1];
1313 }
1314 def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1315
1316 def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1317   let Latency = 14;
1318   let NumMicroOps = 1;
1319   let ResourceCycles = [1,4];
1320 }
1321 def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
1322
1323 def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1324   let Latency = 14;
1325   let NumMicroOps = 3;
1326   let ResourceCycles = [1,1,1];
1327 }
1328 def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
1329
1330 def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1331   let Latency = 14;
1332   let NumMicroOps = 8;
1333   let ResourceCycles = [2,2,1,3];
1334 }
1335 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
1336
1337 def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1338   let Latency = 14;
1339   let NumMicroOps = 10;
1340   let ResourceCycles = [2,3,1,4];
1341 }
1342 def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>;
1343
1344 def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
1345   let Latency = 14;
1346   let NumMicroOps = 12;
1347   let ResourceCycles = [2,1,4,5];
1348 }
1349 def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
1350
1351 def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
1352   let Latency = 15;
1353   let NumMicroOps = 1;
1354   let ResourceCycles = [1];
1355 }
1356 def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1357
1358 def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1359   let Latency = 15;
1360   let NumMicroOps = 10;
1361   let ResourceCycles = [1,1,1,4,1,2];
1362 }
1363 def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
1364
1365 def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1366   let Latency = 16;
1367   let NumMicroOps = 2;
1368   let ResourceCycles = [1,1,5];
1369 }
1370 def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
1371
1372 def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1373   let Latency = 16;
1374   let NumMicroOps = 14;
1375   let ResourceCycles = [1,1,1,4,2,5];
1376 }
1377 def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
1378
1379 def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> {
1380   let Latency = 8;
1381   let NumMicroOps = 20;
1382   let ResourceCycles = [1,1];
1383 }
1384 def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
1385
1386 def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
1387   let Latency = 18;
1388   let NumMicroOps = 8;
1389   let ResourceCycles = [1,1,1,5];
1390 }
1391 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
1392 def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
1393
1394 def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1395   let Latency = 18;
1396   let NumMicroOps = 11;
1397   let ResourceCycles = [2,1,1,3,1,3];
1398 }
1399 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
1400
1401 def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1402   let Latency = 19;
1403   let NumMicroOps = 2;
1404   let ResourceCycles = [1,1,8];
1405 }
1406 def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
1407
1408 def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
1409   let Latency = 20;
1410   let NumMicroOps = 1;
1411   let ResourceCycles = [1];
1412 }
1413 def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1414
1415 def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1416   let Latency = 20;
1417   let NumMicroOps = 8;
1418   let ResourceCycles = [1,1,1,1,1,1,2];
1419 }
1420 def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
1421
1422 def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
1423   let Latency = 21;
1424   let NumMicroOps = 2;
1425   let ResourceCycles = [1,1];
1426 }
1427 def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
1428
1429 def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1430   let Latency = 21;
1431   let NumMicroOps = 19;
1432   let ResourceCycles = [2,1,4,1,1,4,6];
1433 }
1434 def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
1435
1436 def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1437   let Latency = 22;
1438   let NumMicroOps = 18;
1439   let ResourceCycles = [1,1,16];
1440 }
1441 def: InstRW<[BWWriteResGroup172], (instrs POPF64)>;
1442
1443 def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1444   let Latency = 23;
1445   let NumMicroOps = 19;
1446   let ResourceCycles = [3,1,15];
1447 }
1448 def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
1449
1450 def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1451   let Latency = 24;
1452   let NumMicroOps = 3;
1453   let ResourceCycles = [1,1,1];
1454 }
1455 def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
1456
1457 def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
1458   let Latency = 26;
1459   let NumMicroOps = 2;
1460   let ResourceCycles = [1,1];
1461 }
1462 def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
1463
1464 def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1465   let Latency = 29;
1466   let NumMicroOps = 3;
1467   let ResourceCycles = [1,1,1];
1468 }
1469 def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
1470
1471 def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1472   let Latency = 22;
1473   let NumMicroOps = 7;
1474   let ResourceCycles = [1,3,2,1];
1475 }
1476 def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
1477
1478 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1479   let Latency = 23;
1480   let NumMicroOps = 9;
1481   let ResourceCycles = [1,3,4,1];
1482 }
1483 def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
1484
1485 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1486   let Latency = 24;
1487   let NumMicroOps = 9;
1488   let ResourceCycles = [1,5,2,1];
1489 }
1490 def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
1491
1492 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1493   let Latency = 25;
1494   let NumMicroOps = 7;
1495   let ResourceCycles = [1,3,2,1];
1496 }
1497 def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
1498                                             VGATHERDPSrm)>;
1499
1500 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1501   let Latency = 26;
1502   let NumMicroOps = 9;
1503   let ResourceCycles = [1,5,2,1];
1504 }
1505 def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
1506
1507 def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1508   let Latency = 26;
1509   let NumMicroOps = 14;
1510   let ResourceCycles = [1,4,8,1];
1511 }
1512 def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
1513
1514 def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1515   let Latency = 27;
1516   let NumMicroOps = 9;
1517   let ResourceCycles = [1,5,2,1];
1518 }
1519 def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
1520
1521 def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1522   let Latency = 29;
1523   let NumMicroOps = 27;
1524   let ResourceCycles = [1,5,1,1,19];
1525 }
1526 def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
1527
1528 def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1529   let Latency = 30;
1530   let NumMicroOps = 28;
1531   let ResourceCycles = [1,6,1,1,19];
1532 }
1533 def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
1534 def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1535
1536 def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
1537   let Latency = 34;
1538   let NumMicroOps = 23;
1539   let ResourceCycles = [1,5,3,4,10];
1540 }
1541 def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
1542                                              "IN(8|16|32)rr")>;
1543
1544 def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1545   let Latency = 35;
1546   let NumMicroOps = 23;
1547   let ResourceCycles = [1,5,2,1,4,10];
1548 }
1549 def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
1550                                              "OUT(8|16|32)rr")>;
1551
1552 def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
1553   let Latency = 42;
1554   let NumMicroOps = 22;
1555   let ResourceCycles = [2,20];
1556 }
1557 def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
1558
1559 def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
1560   let Latency = 60;
1561   let NumMicroOps = 64;
1562   let ResourceCycles = [2,2,8,1,10,2,39];
1563 }
1564 def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
1565
1566 def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1567   let Latency = 63;
1568   let NumMicroOps = 88;
1569   let ResourceCycles = [4,4,31,1,2,1,45];
1570 }
1571 def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
1572
1573 def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1574   let Latency = 63;
1575   let NumMicroOps = 90;
1576   let ResourceCycles = [4,2,33,1,2,1,47];
1577 }
1578 def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
1579
1580 def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
1581   let Latency = 75;
1582   let NumMicroOps = 15;
1583   let ResourceCycles = [6,3,6];
1584 }
1585 def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
1586
1587 def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
1588   let Latency = 115;
1589   let NumMicroOps = 100;
1590   let ResourceCycles = [9,9,11,8,1,11,21,30];
1591 }
1592 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
1593
1594 def: InstRW<[WriteZero], (instrs CLC)>;
1595
1596 } // SchedModel