lib/Target/X86/X86SchedSkylakeClient.td

   1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Skylake Client to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def SkylakeClientModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and SKylake can
  16   // decode 6 instructions per cycle.
  17   let IssueWidth = 6;
  18   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 14;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = SkylakeClientModel in {
  31
  32 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def SKLPort0 : ProcResource<1>;
  41 def SKLPort1 : ProcResource<1>;
  42 def SKLPort2 : ProcResource<1>;
  43 def SKLPort3 : ProcResource<1>;
  44 def SKLPort4 : ProcResource<1>;
  45 def SKLPort5 : ProcResource<1>;
  46 def SKLPort6 : ProcResource<1>;
  47 def SKLPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
  51 def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
  52 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
  53 def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
  54 def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
  55 def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
  56 def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
  57 def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
  58 def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
  59 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
  60 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
  61 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
  62
  63 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
  64 // FP division and sqrt on port 0.
  65 def SKLFPDivider : ProcResource<1>;
  66
  67 // 60 Entry Unified Scheduler
  68 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
  69                               SKLPort5, SKLPort6, SKLPort7]> {
  70   let BufferSize=60;
  71 }
  72
  73 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  74 // cycles after the memory operand.
  75 def : ReadAdvance<ReadAfterLd, 5>;
  76
  77 // Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
  78 // until 5/6/7 cycles after the memory operand.
  79 def : ReadAdvance<ReadAfterVecLd, 5>;
  80 def : ReadAdvance<ReadAfterVecXLd, 6>;
  81 def : ReadAdvance<ReadAfterVecYLd, 7>;
  82
  83 def : ReadAdvance<ReadInt2Fpu, 0>;
  84
  85 // Many SchedWrites are defined in pairs with and without a folded load.
  86 // Instructions with folded loads are usually micro-fused, so they only appear
  87 // as two micro-ops when queued in the reservation station.
  88 // This multiclass defines the resource usage for variants with and without
  89 // folded loads.
  90 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
  91                           list<ProcResourceKind> ExePorts,
  92                           int Lat, list<int> Res = [1], int UOps = 1,
  93                           int LoadLat = 5> {
  94   // Register variant is using a single cycle on ExePort.
  95   def : WriteRes<SchedRW, ExePorts> {
  96     let Latency = Lat;
  97     let ResourceCycles = Res;
  98     let NumMicroOps = UOps;
  99   }
 100
 101   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 102   // the latency (default = 5).
 103   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
 104     let Latency = !add(Lat, LoadLat);
 105     let ResourceCycles = !listconcat([1], Res);
 106     let NumMicroOps = !add(UOps, 1);
 107   }
 108 }
 109
 110 // A folded store needs a cycle on port 4 for the store data, and an extra port
 111 // 2/3/7 cycle to recompute the address.
 112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
 113
 114 // Arithmetic.
 115 defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
 116 defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
 117
 118 // Integer multiplication.
 119 defm : SKLWriteResPair<WriteIMul8,     [SKLPort1],   3>;
 120 defm : SKLWriteResPair<WriteIMul16,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;
 121 defm : X86WriteRes<WriteIMul16Imm,     [SKLPort1,SKLPort0156], 4, [1,1], 2>;
 122 defm : X86WriteRes<WriteIMul16ImmLd,   [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
 123 defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1],   3>;
 124 defm : SKLWriteResPair<WriteIMul32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
 125 defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1],   3>;
 126 defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1],   3>;
 127 defm : SKLWriteResPair<WriteIMul64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
 128 defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1],   3>;
 129 defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1],   3>;
 130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 131
 132 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 133 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
 134 defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
 135 defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;
 136 defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
 137
 138 // TODO: Why isn't the SKLDivider used?
 139 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0,SKLDivider], 25, [1,10], 1, 4>;
 140 defm : X86WriteRes<WriteDiv16,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 141 defm : X86WriteRes<WriteDiv32,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 142 defm : X86WriteRes<WriteDiv64,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
 143 defm : X86WriteRes<WriteDiv16Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 144 defm : X86WriteRes<WriteDiv32Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 145 defm : X86WriteRes<WriteDiv64Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
 146
 147 defm : X86WriteRes<WriteIDiv8,    [SKLPort0,SKLDivider], 25, [1,10], 1>;
 148 defm : X86WriteRes<WriteIDiv16,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 149 defm : X86WriteRes<WriteIDiv32,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 150 defm : X86WriteRes<WriteIDiv64,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
 151 defm : X86WriteRes<WriteIDiv8Ld,  [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 152 defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 153 defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 154 defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
 155
 156 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 157
 158 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 159
 160 defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
 161 defm : SKLWriteResPair<WriteCMOV2, [SKLPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
 162 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
 163 def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
 164 def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
 165   let Latency = 2;
 166   let NumMicroOps = 3;
 167 }
 168
 169 defm : X86WriteRes<WriteLAHFSAHF,        [SKLPort06], 1, [1], 1>;
 170 defm : X86WriteRes<WriteBitTest,         [SKLPort06], 1, [1], 1>;
 171 defm : X86WriteRes<WriteBitTestImmLd,    [SKLPort06,SKLPort23], 6, [1,1], 2>;
 172 defm : X86WriteRes<WriteBitTestRegLd,    [SKLPort0156,SKLPort23], 6, [1,1], 2>;
 173 defm : X86WriteRes<WriteBitTestSet,      [SKLPort06], 1, [1], 1>;
 174 defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>;
 175 defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;
 176
 177 // Bit counts.
 178 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
 179 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
 180 defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
 181 defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
 182 defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
 183
 184 // Integer shifts and rotates.
 185 defm : SKLWriteResPair<WriteShift,    [SKLPort06],  1>;
 186 defm : SKLWriteResPair<WriteShiftCL,  [SKLPort06],  3, [3], 3>;
 187 defm : SKLWriteResPair<WriteRotate,   [SKLPort06],  2, [2], 2>;
 188 defm : SKLWriteResPair<WriteRotateCL, [SKLPort06],  3, [3], 3>;
 189
 190 // SHLD/SHRD.
 191 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
 192 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
 193 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
 194 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
 195
 196 // BMI1 BEXTR/BLS, BMI2 BZHI
 197 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
 198 defm : SKLWriteResPair<WriteBLS,   [SKLPort15], 1>;
 199 defm : SKLWriteResPair<WriteBZHI,  [SKLPort15], 1>;
 200
 201 // Loads, stores, and moves, not folded with other operations.
 202 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
 203 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
 204 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
 205 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
 206
 207 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 208 // These can often bypass execution ports completely.
 209 def : WriteRes<WriteZero,  []>;
 210
 211 // Branches don't produce values, so they have no latency, but they still
 212 // consume resources. Indirect branches can fold loads.
 213 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
 214
 215 // Floating point. This covers both scalar and vector operations.
 216 defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
 217 defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
 218 defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
 219 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
 220 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
 221 defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
 222 defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 223 defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 224 defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 225 defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 226 defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 227 defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 228 defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 229 defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 230 defm : X86WriteRes<WriteFMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 231 defm : X86WriteRes<WriteFMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 232 defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
 233 defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
 234 defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
 235 defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
 236
 237 defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
 238 defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
 239 defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
 240 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 241 defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 242 defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
 243 defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
 244 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 245
 246 defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
 247 defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
 248 defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
 249 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 250 defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
 251 defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
 252 defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
 253 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 254
 255 defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags.
 256
 257 defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
 258 defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
 259 defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
 260 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 261 defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 262 defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
 263 defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
 264 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 265
 266 defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 267 //defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
 268 defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
 269 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 270 //defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division.
 271 //defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>;
 272 //defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>;
 273 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 274
 275 defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 276 defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
 277 defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
 278 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 279 defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 280 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
 281 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
 282 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 283 defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
 284
 285 defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
 286 defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
 287 defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
 288 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 289
 290 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 291 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
 292 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
 293 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 294
 295 defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
 296 defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
 297 defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
 298 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 299 defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
 300 defm : SKLWriteResPair<WriteDPPS,   [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
 301 defm : SKLWriteResPair<WriteDPPSY,  [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
 302 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 303 defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
 304 defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
 305 defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
 306 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 307 defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 308 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
 309 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 310 defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 311 defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
 312 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 313 defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 314 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
 315 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 316 defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 317 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 318 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 319 defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
 320 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
 321 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 322 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 323 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
 324 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 325
 326 // FMA Scheduling helper class.
 327 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 328
 329 // Vector integer operations.
 330 defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
 331 defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
 332 defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
 333 defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23], 6, [1], 1>;
 334 defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23], 7, [1], 1>;
 335 defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 336 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 337 defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 338 defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 339 defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 340 defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 341 defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 342 defm : X86WriteRes<WriteVecMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 343 defm : X86WriteRes<WriteVecMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 344 defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
 345 defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
 346 defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
 347 defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
 348 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
 349
 350 defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 351 defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
 352 defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
 353 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 354 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 355 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
 356 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
 357 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 358 defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 359 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
 360 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 361 defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  4, [1], 1, 5>; // Vector integer multiply.
 362 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  4, [1], 1, 6>;
 363 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  4, [1], 1, 7>;
 364 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 365 defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
 366 defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
 367 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 368 defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 369 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
 370 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
 371 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 372 defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 373 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
 374 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 375 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 376 defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
 377 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
 378 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 379 defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
 380 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
 381 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 382 defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
 383 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
 384 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 385 defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
 386 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
 387 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
 388 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 389 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
 390
 391 // Vector integer shifts.
 392 defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
 393 defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
 394 defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
 395 defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
 396 defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
 397 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 398
 399 defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
 400 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
 401 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
 402 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 403 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
 404 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
 405 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 406
 407 // Vector insert/extract operations.
 408 def : WriteRes<WriteVecInsert, [SKLPort5]> {
 409   let Latency = 2;
 410   let NumMicroOps = 2;
 411   let ResourceCycles = [2];
 412 }
 413 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
 414   let Latency = 6;
 415   let NumMicroOps = 2;
 416 }
 417 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 418
 419 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
 420   let Latency = 3;
 421   let NumMicroOps = 2;
 422 }
 423 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
 424   let Latency = 2;
 425   let NumMicroOps = 3;
 426 }
 427
 428 // Conversion between integer and float.
 429 defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort1], 3>;
 430 defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort1], 3>;
 431 defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort1], 3>;
 432 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 433 defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort1], 3>;
 434 defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort1], 3>;
 435 defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort1], 3>;
 436 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 437
 438 defm : SKLWriteResPair<WriteCvtI2SS,   [SKLPort1], 4>;
 439 defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort1], 4>;
 440 defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort1], 4>;
 441 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 442 defm : SKLWriteResPair<WriteCvtI2SD,   [SKLPort1], 4>;
 443 defm : SKLWriteResPair<WriteCvtI2PD,   [SKLPort1], 4>;
 444 defm : SKLWriteResPair<WriteCvtI2PDY,  [SKLPort1], 4>;
 445 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 446
 447 defm : SKLWriteResPair<WriteCvtSS2SD,  [SKLPort1], 3>;
 448 defm : SKLWriteResPair<WriteCvtPS2PD,  [SKLPort1], 3>;
 449 defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>;
 450 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 451 defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort1], 3>;
 452 defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort1], 3>;
 453 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>;
 454 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 455
 456 defm : X86WriteRes<WriteCvtPH2PS,    [SKLPort5,SKLPort015],  5, [1,1], 2>;
 457 defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 458 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 459 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 460 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
 461 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 462
 463 defm : X86WriteRes<WriteCvtPS2PH,                       [SKLPort5,SKLPort015], 5, [1,1], 2>;
 464 defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
 465 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 466 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
 467 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
 468 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 469
 470 // Strings instructions.
 471
 472 // Packed Compare Implicit Length Strings, Return Mask
 473 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
 474   let Latency = 10;
 475   let NumMicroOps = 3;
 476   let ResourceCycles = [3];
 477 }
 478 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
 479   let Latency = 16;
 480   let NumMicroOps = 4;
 481   let ResourceCycles = [3,1];
 482 }
 483
 484 // Packed Compare Explicit Length Strings, Return Mask
 485 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
 486   let Latency = 19;
 487   let NumMicroOps = 9;
 488   let ResourceCycles = [4,3,1,1];
 489 }
 490 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
 491   let Latency = 25;
 492   let NumMicroOps = 10;
 493   let ResourceCycles = [4,3,1,1,1];
 494 }
 495
 496 // Packed Compare Implicit Length Strings, Return Index
 497 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
 498   let Latency = 10;
 499   let NumMicroOps = 3;
 500   let ResourceCycles = [3];
 501 }
 502 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
 503   let Latency = 16;
 504   let NumMicroOps = 4;
 505   let ResourceCycles = [3,1];
 506 }
 507
 508 // Packed Compare Explicit Length Strings, Return Index
 509 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
 510   let Latency = 18;
 511   let NumMicroOps = 8;
 512   let ResourceCycles = [4,3,1];
 513 }
 514 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
 515   let Latency = 24;
 516   let NumMicroOps = 9;
 517   let ResourceCycles = [4,3,1,1];
 518 }
 519
 520 // MOVMSK Instructions.
 521 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
 522 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
 523 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
 524 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
 525
 526 // AES instructions.
 527 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
 528   let Latency = 4;
 529   let NumMicroOps = 1;
 530   let ResourceCycles = [1];
 531 }
 532 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
 533   let Latency = 10;
 534   let NumMicroOps = 2;
 535   let ResourceCycles = [1,1];
 536 }
 537
 538 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
 539   let Latency = 8;
 540   let NumMicroOps = 2;
 541   let ResourceCycles = [2];
 542 }
 543 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
 544   let Latency = 14;
 545   let NumMicroOps = 3;
 546   let ResourceCycles = [2,1];
 547 }
 548
 549 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
 550   let Latency = 20;
 551   let NumMicroOps = 11;
 552   let ResourceCycles = [3,6,2];
 553 }
 554 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
 555   let Latency = 25;
 556   let NumMicroOps = 11;
 557   let ResourceCycles = [3,6,1,1];
 558 }
 559
 560 // Carry-less multiplication instructions.
 561 def : WriteRes<WriteCLMul, [SKLPort5]> {
 562   let Latency = 6;
 563   let NumMicroOps = 1;
 564   let ResourceCycles = [1];
 565 }
 566 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
 567   let Latency = 12;
 568   let NumMicroOps = 2;
 569   let ResourceCycles = [1,1];
 570 }
 571
 572 // Catch-all for expensive system instructions.
 573 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 574
 575 // AVX2.
 576 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 577 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 578 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 579 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 580
 581 // Old microcoded instructions that nobody use.
 582 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 583
 584 // Fence instructions.
 585 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
 586
 587 // Load/store MXCSR.
 588 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 589 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 590
 591 // Nop, not very useful expect it provides a model for nops!
 592 def : WriteRes<WriteNop, []>;
 593
 594 ////////////////////////////////////////////////////////////////////////////////
 595 // Horizontal add/sub  instructions.
 596 ////////////////////////////////////////////////////////////////////////////////
 597
 598 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
 599 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
 600 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
 601 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
 602 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
 603
 604 // Remaining instrs.
 605
 606 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
 607   let Latency = 1;
 608   let NumMicroOps = 1;
 609   let ResourceCycles = [1];
 610 }
 611 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
 612                                             "MMX_PADDUS(B|W)irr",
 613                                             "MMX_PAVG(B|W)irr",
 614                                             "MMX_PCMPEQ(B|D|W)irr",
 615                                             "MMX_PCMPGT(B|D|W)irr",
 616                                             "MMX_P(MAX|MIN)SWirr",
 617                                             "MMX_P(MAX|MIN)UBirr",
 618                                             "MMX_PSUBS(B|W)irr",
 619                                             "MMX_PSUBUS(B|W)irr")>;
 620
 621 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
 622   let Latency = 1;
 623   let NumMicroOps = 1;
 624   let ResourceCycles = [1];
 625 }
 626 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
 627                                             "UCOM_F(P?)r")>;
 628
 629 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
 630   let Latency = 1;
 631   let NumMicroOps = 1;
 632   let ResourceCycles = [1];
 633 }
 634 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 635
 636 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
 637   let Latency = 1;
 638   let NumMicroOps = 1;
 639   let ResourceCycles = [1];
 640 }
 641 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
 642
 643 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
 644   let Latency = 1;
 645   let NumMicroOps = 1;
 646   let ResourceCycles = [1];
 647 }
 648 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 649
 650 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
 651   let Latency = 1;
 652   let NumMicroOps = 1;
 653   let ResourceCycles = [1];
 654 }
 655 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
 656
 657 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
 658   let Latency = 1;
 659   let NumMicroOps = 1;
 660   let ResourceCycles = [1];
 661 }
 662 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
 663                                             "VPBLENDD(Y?)rri",
 664                                             "(V?)PSUB(B|D|Q|W)(Y?)rr")>;
 665
 666 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
 667   let Latency = 1;
 668   let NumMicroOps = 1;
 669   let ResourceCycles = [1];
 670 }
 671 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
 672                                           CMC, STC,
 673                                           SGDT64m,
 674                                           SIDT64m,
 675                                           SMSW16m,
 676                                           STRm,
 677                                           SYSCALL)>;
 678
 679 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
 680   let Latency = 1;
 681   let NumMicroOps = 2;
 682   let ResourceCycles = [1,1];
 683 }
 684 def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
 685 def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
 686
 687 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
 688   let Latency = 2;
 689   let NumMicroOps = 2;
 690   let ResourceCycles = [2];
 691 }
 692 def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
 693
 694 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
 695   let Latency = 2;
 696   let NumMicroOps = 2;
 697   let ResourceCycles = [2];
 698 }
 699 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
 700                                           MMX_MOVDQ2Qrr)>;
 701
 702 def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
 703   let Latency = 2;
 704   let NumMicroOps = 2;
 705   let ResourceCycles = [2];
 706 }
 707 def: InstRW<[SKLWriteResGroup15], (instregex "SET(A|BE)r")>;
 708
 709 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
 710   let Latency = 2;
 711   let NumMicroOps = 2;
 712   let ResourceCycles = [2];
 713 }
 714 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
 715                                           WAIT,
 716                                           XGETBV)>;
 717
 718 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 719   let Latency = 2;
 720   let NumMicroOps = 2;
 721   let ResourceCycles = [1,1];
 722 }
 723 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
 724
 725 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 726   let Latency = 2;
 727   let NumMicroOps = 2;
 728   let ResourceCycles = [1,1];
 729 }
 730 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
 731
 732 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 733   let Latency = 2;
 734   let NumMicroOps = 2;
 735   let ResourceCycles = [1,1];
 736 }
 737 def: InstRW<[SKLWriteResGroup23], (instrs CWD,
 738                                           JCXZ, JECXZ, JRCXZ,
 739                                           ADC8i8, SBB8i8)>;
 740 def: InstRW<[SKLWriteResGroup23], (instregex "ADC8ri",
 741                                              "SBB8ri")>;
 742
 743 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
 744   let Latency = 2;
 745   let NumMicroOps = 3;
 746   let ResourceCycles = [1,1,1];
 747 }
 748 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
 749
 750 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
 751   let Latency = 2;
 752   let NumMicroOps = 3;
 753   let ResourceCycles = [1,1,1];
 754 }
 755 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 756
 757 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 758   let Latency = 2;
 759   let NumMicroOps = 3;
 760   let ResourceCycles = [1,1,1];
 761 }
 762 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 763                                           STOSB, STOSL, STOSQ, STOSW)>;
 764 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
 765
 766 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
 767   let Latency = 3;
 768   let NumMicroOps = 1;
 769   let ResourceCycles = [1];
 770 }
 771 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
 772                                              "PEXT(32|64)rr")>;
 773
 774 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
 775   let Latency = 3;
 776   let NumMicroOps = 1;
 777   let ResourceCycles = [1];
 778 }
 779 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 780                                              "VPBROADCAST(B|W)rr",
 781                                              "(V?)PCMPGTQ(Y?)rr")>;
 782
 783 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
 784   let Latency = 3;
 785   let NumMicroOps = 2;
 786   let ResourceCycles = [1,1];
 787 }
 788 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
 789
 790 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 791   let Latency = 3;
 792   let NumMicroOps = 3;
 793   let ResourceCycles = [1,2];
 794 }
 795 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 796
 797 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
 798   let Latency = 3;
 799   let NumMicroOps = 3;
 800   let ResourceCycles = [2,1];
 801 }
 802 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
 803                                              "(V?)PHSUBSW(Y?)rr")>;
 804
 805 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
 806   let Latency = 3;
 807   let NumMicroOps = 3;
 808   let ResourceCycles = [2,1];
 809 }
 810 def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr,
 811                                           MMX_PACKSSWBirr,
 812                                           MMX_PACKUSWBirr)>;
 813
 814 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 815   let Latency = 3;
 816   let NumMicroOps = 3;
 817   let ResourceCycles = [1,2];
 818 }
 819 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
 820
 821 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 822   let Latency = 3;
 823   let NumMicroOps = 3;
 824   let ResourceCycles = [1,2];
 825 }
 826 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
 827
 828 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 829   let Latency = 3;
 830   let NumMicroOps = 3;
 831   let ResourceCycles = [1,2];
 832 }
 833 def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)",
 834                                              "RCR(8|16|32|64)r(1|i)")>;
 835
 836 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
 837   let Latency = 3;
 838   let NumMicroOps = 3;
 839   let ResourceCycles = [1,1,1];
 840 }
 841 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 842
 843 def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
 844   let Latency = 3;
 845   let NumMicroOps = 4;
 846   let ResourceCycles = [1,1,2];
 847 }
 848 def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;
 849
 850 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
 851   let Latency = 3;
 852   let NumMicroOps = 4;
 853   let ResourceCycles = [1,1,1,1];
 854 }
 855 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 856
 857 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
 858   let Latency = 3;
 859   let NumMicroOps = 4;
 860   let ResourceCycles = [1,1,1,1];
 861 }
 862 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
 863
 864 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
 865   let Latency = 4;
 866   let NumMicroOps = 1;
 867   let ResourceCycles = [1];
 868 }
 869 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 870
 871 def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
 872   let Latency = 4;
 873   let NumMicroOps = 1;
 874   let ResourceCycles = [1];
 875 }
 876 def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
 877                                              "(V?)CVT(T?)PS2DQ(Y?)rr")>;
 878
 879 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
 880   let Latency = 4;
 881   let NumMicroOps = 3;
 882   let ResourceCycles = [1,1,1];
 883 }
 884 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
 885                                              "IST_F(16|32)m")>;
 886
 887 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
 888   let Latency = 4;
 889   let NumMicroOps = 4;
 890   let ResourceCycles = [4];
 891 }
 892 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
 893
 894 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 895   let Latency = 4;
 896   let NumMicroOps = 4;
 897   let ResourceCycles = [1,3];
 898 }
 899 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
 900
 901 def SKLWriteResGroup56 : SchedWriteRes<[]> {
 902   let Latency = 0;
 903   let NumMicroOps = 4;
 904   let ResourceCycles = [];
 905 }
 906 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
 907
 908 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
 909   let Latency = 4;
 910   let NumMicroOps = 4;
 911   let ResourceCycles = [1,1,2];
 912 }
 913 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 914
 915 def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
 916   let Latency = 5;
 917   let NumMicroOps = 1;
 918   let ResourceCycles = [1];
 919 }
 920 def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
 921                                              "MOVZX(16|32|64)rm(8|16)",
 922                                              "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67?
 923
 924 def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 925   let Latency = 5;
 926   let NumMicroOps = 2;
 927   let ResourceCycles = [1,1];
 928 }
 929 def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr,
 930                                           CVTDQ2PDrr,
 931                                           VCVTDQ2PDrr)>;
 932
 933 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
 934   let Latency = 5;
 935   let NumMicroOps = 2;
 936   let ResourceCycles = [1,1];
 937 }
 938 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
 939                                              "MMX_CVT(T?)PS2PIirr",
 940                                              "(V?)CVT(T?)PD2DQrr",
 941                                              "(V?)CVTPD2PSrr",
 942                                              "(V?)CVTPS2PDrr",
 943                                              "(V?)CVTSD2SSrr",
 944                                              "(V?)CVTSI642SDrr",
 945                                              "(V?)CVTSI2SDrr",
 946                                              "(V?)CVTSI2SSrr",
 947                                              "(V?)CVTSS2SDrr")>;
 948
 949 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
 950   let Latency = 5;
 951   let NumMicroOps = 3;
 952   let ResourceCycles = [1,1,1];
 953 }
 954 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
 955
 956 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 957   let Latency = 5;
 958   let NumMicroOps = 5;
 959   let ResourceCycles = [1,4];
 960 }
 961 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 962
 963 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 964   let Latency = 5;
 965   let NumMicroOps = 6;
 966   let ResourceCycles = [1,1,4];
 967 }
 968 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
 969
 970 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
 971   let Latency = 6;
 972   let NumMicroOps = 1;
 973   let ResourceCycles = [1];
 974 }
 975 def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
 976                                           VPBROADCASTDrm,
 977                                           VPBROADCASTQrm)>;
 978 def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
 979                                              "(V?)MOVSLDUPrm")>;
 980
 981 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
 982   let Latency = 6;
 983   let NumMicroOps = 2;
 984   let ResourceCycles = [2];
 985 }
 986 def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>;
 987
 988 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
 989   let Latency = 6;
 990   let NumMicroOps = 2;
 991   let ResourceCycles = [1,1];
 992 }
 993 def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm,
 994                                           MMX_PADDSWirm,
 995                                           MMX_PADDUSBirm,
 996                                           MMX_PADDUSWirm,
 997                                           MMX_PAVGBirm,
 998                                           MMX_PAVGWirm,
 999                                           MMX_PCMPEQBirm,
1000                                           MMX_PCMPEQDirm,
1001                                           MMX_PCMPEQWirm,
1002                                           MMX_PCMPGTBirm,
1003                                           MMX_PCMPGTDirm,
1004                                           MMX_PCMPGTWirm,
1005                                           MMX_PMAXSWirm,
1006                                           MMX_PMAXUBirm,
1007                                           MMX_PMINSWirm,
1008                                           MMX_PMINUBirm,
1009                                           MMX_PSUBSBirm,
1010                                           MMX_PSUBSWirm,
1011                                           MMX_PSUBUSBirm,
1012                                           MMX_PSUBUSWirm)>;
1013
1014 def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
1015   let Latency = 6;
1016   let NumMicroOps = 2;
1017   let ResourceCycles = [1,1];
1018 }
1019 def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
1020                                              "(V?)CVT(T?)SD2SI(64)?rr")>;
1021
1022 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1023   let Latency = 6;
1024   let NumMicroOps = 2;
1025   let ResourceCycles = [1,1];
1026 }
1027 def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64)>;
1028 def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
1029
1030 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1031   let Latency = 6;
1032   let NumMicroOps = 2;
1033   let ResourceCycles = [1,1];
1034 }
1035 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1036                                              "MOVBE(16|32|64)rm")>;
1037
1038 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1039   let Latency = 6;
1040   let NumMicroOps = 2;
1041   let ResourceCycles = [1,1];
1042 }
1043 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1044 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1045
1046 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1047   let Latency = 6;
1048   let NumMicroOps = 3;
1049   let ResourceCycles = [2,1];
1050 }
1051 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1052
1053 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1054   let Latency = 6;
1055   let NumMicroOps = 4;
1056   let ResourceCycles = [1,1,1,1];
1057 }
1058 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1059
1060 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1061   let Latency = 6;
1062   let NumMicroOps = 4;
1063   let ResourceCycles = [1,1,1,1];
1064 }
1065 def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
1066                                              "SHL(8|16|32|64)m(1|i)",
1067                                              "SHR(8|16|32|64)m(1|i)")>;
1068
1069 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1070   let Latency = 6;
1071   let NumMicroOps = 4;
1072   let ResourceCycles = [1,1,1,1];
1073 }
1074 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1075                                              "PUSH(16|32|64)rmm")>;
1076
1077 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1078   let Latency = 6;
1079   let NumMicroOps = 6;
1080   let ResourceCycles = [1,5];
1081 }
1082 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1083
1084 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1085   let Latency = 7;
1086   let NumMicroOps = 1;
1087   let ResourceCycles = [1];
1088 }
1089 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
1090 def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
1091                                           VBROADCASTI128,
1092                                           VBROADCASTSDYrm,
1093                                           VBROADCASTSSYrm,
1094                                           VMOVDDUPYrm,
1095                                           VMOVSHDUPYrm,
1096                                           VMOVSLDUPYrm,
1097                                           VPBROADCASTDYrm,
1098                                           VPBROADCASTQYrm)>;
1099
1100 def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1101   let Latency = 7;
1102   let NumMicroOps = 2;
1103   let ResourceCycles = [1,1];
1104 }
1105 def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>;
1106
1107 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1108   let Latency = 6;
1109   let NumMicroOps = 2;
1110   let ResourceCycles = [1,1];
1111 }
1112 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1113                                              "(V?)PMOV(SX|ZX)BQrm",
1114                                              "(V?)PMOV(SX|ZX)BWrm",
1115                                              "(V?)PMOV(SX|ZX)DQrm",
1116                                              "(V?)PMOV(SX|ZX)WDrm",
1117                                              "(V?)PMOV(SX|ZX)WQrm")>;
1118
1119 def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1120   let Latency = 7;
1121   let NumMicroOps = 2;
1122   let ResourceCycles = [1,1];
1123 }
1124 def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr,
1125                                           VCVTPS2PDYrr,
1126                                           VCVTPD2DQYrr,
1127                                           VCVTTPD2DQYrr)>;
1128
1129 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1130   let Latency = 7;
1131   let NumMicroOps = 2;
1132   let ResourceCycles = [1,1];
1133 }
1134 def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
1135                                           VINSERTI128rm,
1136                                           VPBLENDDrmi)>;
1137 def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
1138                                   (instregex "(V?)PADD(B|D|Q|W)rm",
1139                                              "(V?)PSUB(B|D|Q|W)rm")>;
1140
1141 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1142   let Latency = 7;
1143   let NumMicroOps = 3;
1144   let ResourceCycles = [2,1];
1145 }
1146 def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm,
1147                                           MMX_PACKSSWBirm,
1148                                           MMX_PACKUSWBirm)>;
1149
1150 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1151   let Latency = 7;
1152   let NumMicroOps = 3;
1153   let ResourceCycles = [1,2];
1154 }
1155 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1156                                           SCASB, SCASL, SCASQ, SCASW)>;
1157
1158 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1159   let Latency = 7;
1160   let NumMicroOps = 3;
1161   let ResourceCycles = [1,1,1];
1162 }
1163 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
1164
1165 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1166   let Latency = 7;
1167   let NumMicroOps = 3;
1168   let ResourceCycles = [1,1,1];
1169 }
1170 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1171
1172 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1173   let Latency = 7;
1174   let NumMicroOps = 3;
1175   let ResourceCycles = [1,1,1];
1176 }
1177 def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>;
1178
1179 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1180   let Latency = 7;
1181   let NumMicroOps = 5;
1182   let ResourceCycles = [1,1,1,2];
1183 }
1184 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1185                                               "ROR(8|16|32|64)m(1|i)")>;
1186
1187 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1188   let Latency = 7;
1189   let NumMicroOps = 5;
1190   let ResourceCycles = [1,1,1,2];
1191 }
1192 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1193
1194 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1195   let Latency = 7;
1196   let NumMicroOps = 5;
1197   let ResourceCycles = [1,1,1,1,1];
1198 }
1199 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
1200 def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64)>;
1201
1202 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1203   let Latency = 7;
1204   let NumMicroOps = 7;
1205   let ResourceCycles = [1,3,1,2];
1206 }
1207 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1208
1209 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1210   let Latency = 8;
1211   let NumMicroOps = 2;
1212   let ResourceCycles = [1,1];
1213 }
1214 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1215                                               "PEXT(32|64)rm")>;
1216
1217 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1218   let Latency = 8;
1219   let NumMicroOps = 2;
1220   let ResourceCycles = [1,1];
1221 }
1222 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
1223 def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
1224                                            VPBROADCASTWYrm,
1225                                            VPMOVSXBDYrm,
1226                                            VPMOVSXBQYrm,
1227                                            VPMOVSXWQYrm)>;
1228
1229 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1230   let Latency = 8;
1231   let NumMicroOps = 2;
1232   let ResourceCycles = [1,1];
1233 }
1234 def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
1235 def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
1236                                    (instregex "VPADD(B|D|Q|W)Yrm",
1237                                               "VPSUB(B|D|Q|W)Yrm")>;
1238
1239 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1240   let Latency = 8;
1241   let NumMicroOps = 4;
1242   let ResourceCycles = [1,2,1];
1243 }
1244 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1245
1246 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1247   let Latency = 8;
1248   let NumMicroOps = 5;
1249   let ResourceCycles = [1,1,1,2];
1250 }
1251 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
1252                                               "RCR(8|16|32|64)m(1|i)")>;
1253
1254 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1255   let Latency = 8;
1256   let NumMicroOps = 6;
1257   let ResourceCycles = [1,1,1,3];
1258 }
1259 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1260                                               "ROR(8|16|32|64)mCL",
1261                                               "SAR(8|16|32|64)mCL",
1262                                               "SHL(8|16|32|64)mCL",
1263                                               "SHR(8|16|32|64)mCL")>;
1264
1265 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1266   let Latency = 8;
1267   let NumMicroOps = 6;
1268   let ResourceCycles = [1,1,1,2,1];
1269 }
1270 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1271
1272 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1273   let Latency = 9;
1274   let NumMicroOps = 2;
1275   let ResourceCycles = [1,1];
1276 }
1277 def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>;
1278
1279 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1280   let Latency = 9;
1281   let NumMicroOps = 2;
1282   let ResourceCycles = [1,1];
1283 }
1284 def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
1285                                            VPCMPGTQrm,
1286                                            VPMOVSXBWYrm,
1287                                            VPMOVSXDQYrm,
1288                                            VPMOVSXWDYrm,
1289                                            VPMOVZXWDYrm)>;
1290
1291 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1292   let Latency = 9;
1293   let NumMicroOps = 2;
1294   let ResourceCycles = [1,1];
1295 }
1296 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
1297                                               "(V?)CVTPS2PDrm")>;
1298
1299 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1300   let Latency = 9;
1301   let NumMicroOps = 4;
1302   let ResourceCycles = [2,1,1];
1303 }
1304 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1305                                               "(V?)PHSUBSWrm")>;
1306
1307 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1308   let Latency = 9;
1309   let NumMicroOps = 5;
1310   let ResourceCycles = [1,2,1,1];
1311 }
1312 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1313                                               "LSL(16|32|64)rm")>;
1314
1315 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1316   let Latency = 10;
1317   let NumMicroOps = 2;
1318   let ResourceCycles = [1,1];
1319 }
1320 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1321                                               "ILD_F(16|32|64)m")>;
1322 def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
1323
1324 def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1325   let Latency = 10;
1326   let NumMicroOps = 2;
1327   let ResourceCycles = [1,1];
1328 }
1329 def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm",
1330                                               "(V?)CVTPS2DQrm",
1331                                               "(V?)CVTSS2SDrm",
1332                                               "(V?)CVTTPS2DQrm")>;
1333
1334 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1335   let Latency = 10;
1336   let NumMicroOps = 3;
1337   let ResourceCycles = [1,1,1];
1338 }
1339 def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>;
1340
1341 def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1342   let Latency = 10;
1343   let NumMicroOps = 3;
1344   let ResourceCycles = [1,1,1];
1345 }
1346 def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
1347
1348 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1349   let Latency = 10;
1350   let NumMicroOps = 4;
1351   let ResourceCycles = [2,1,1];
1352 }
1353 def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
1354                                            VPHSUBSWYrm)>;
1355
1356 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1357   let Latency = 10;
1358   let NumMicroOps = 8;
1359   let ResourceCycles = [1,1,1,1,1,3];
1360 }
1361 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1362
1363 def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1364   let Latency = 11;
1365   let NumMicroOps = 1;
1366   let ResourceCycles = [1,3];
1367 }
1368 def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair
1369
1370 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1371   let Latency = 11;
1372   let NumMicroOps = 2;
1373   let ResourceCycles = [1,1];
1374 }
1375 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1376
1377 def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1378   let Latency = 11;
1379   let NumMicroOps = 2;
1380   let ResourceCycles = [1,1];
1381 }
1382 def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm,
1383                                            VCVTPS2PDYrm,
1384                                            VCVTPS2DQYrm,
1385                                            VCVTTPS2DQYrm)>;
1386
1387 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1388   let Latency = 11;
1389   let NumMicroOps = 3;
1390   let ResourceCycles = [2,1];
1391 }
1392 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1393
1394 def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1395   let Latency = 11;
1396   let NumMicroOps = 3;
1397   let ResourceCycles = [1,1,1];
1398 }
1399 def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
1400
1401 def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
1402   let Latency = 11;
1403   let NumMicroOps = 3;
1404   let ResourceCycles = [1,1,1];
1405 }
1406 def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1407                                               "(V?)CVT(T?)SD2SI(64)?rm",
1408                                               "VCVTTSS2SI64rm",
1409                                               "(V?)CVT(T?)SS2SIrm")>;
1410
1411 def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1412   let Latency = 11;
1413   let NumMicroOps = 3;
1414   let ResourceCycles = [1,1,1];
1415 }
1416 def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm,
1417                                            CVTPD2DQrm,
1418                                            CVTTPD2DQrm,
1419                                            MMX_CVTPD2PIirm,
1420                                            MMX_CVTTPD2PIirm)>;
1421
1422 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1423   let Latency = 11;
1424   let NumMicroOps = 7;
1425   let ResourceCycles = [2,3,2];
1426 }
1427 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1428                                               "RCR(16|32|64)rCL")>;
1429
1430 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1431   let Latency = 11;
1432   let NumMicroOps = 9;
1433   let ResourceCycles = [1,5,1,2];
1434 }
1435 def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
1436
1437 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1438   let Latency = 11;
1439   let NumMicroOps = 11;
1440   let ResourceCycles = [2,9];
1441 }
1442 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1443
1444 def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1445   let Latency = 12;
1446   let NumMicroOps = 4;
1447   let ResourceCycles = [1,1,1,1];
1448 }
1449 def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1450
1451 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1452   let Latency = 13;
1453   let NumMicroOps = 3;
1454   let ResourceCycles = [2,1];
1455 }
1456 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1457
1458 def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1459   let Latency = 13;
1460   let NumMicroOps = 3;
1461   let ResourceCycles = [1,1,1];
1462 }
1463 def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>;
1464
1465 def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1466   let Latency = 14;
1467   let NumMicroOps = 1;
1468   let ResourceCycles = [1,3];
1469 }
1470 def : SchedAlias<WriteFDiv64,  SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1471 def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1472
1473 def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1474   let Latency = 14;
1475   let NumMicroOps = 1;
1476   let ResourceCycles = [1,5];
1477 }
1478 def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair
1479
1480 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1481   let Latency = 14;
1482   let NumMicroOps = 3;
1483   let ResourceCycles = [1,1,1];
1484 }
1485 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1486
1487 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1488   let Latency = 14;
1489   let NumMicroOps = 10;
1490   let ResourceCycles = [2,4,1,3];
1491 }
1492 def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
1493
1494 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1495   let Latency = 15;
1496   let NumMicroOps = 1;
1497   let ResourceCycles = [1];
1498 }
1499 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1500
1501 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1502   let Latency = 15;
1503   let NumMicroOps = 10;
1504   let ResourceCycles = [1,1,1,5,1,1];
1505 }
1506 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1507
1508 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1509   let Latency = 16;
1510   let NumMicroOps = 14;
1511   let ResourceCycles = [1,1,1,4,2,5];
1512 }
1513 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1514
1515 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1516   let Latency = 16;
1517   let NumMicroOps = 16;
1518   let ResourceCycles = [16];
1519 }
1520 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1521
1522 def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1523   let Latency = 17;
1524   let NumMicroOps = 2;
1525   let ResourceCycles = [1,1,5];
1526 }
1527 def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair
1528
1529 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1530   let Latency = 17;
1531   let NumMicroOps = 15;
1532   let ResourceCycles = [2,1,2,4,2,4];
1533 }
1534 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1535
1536 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1537   let Latency = 18;
1538   let NumMicroOps = 8;
1539   let ResourceCycles = [1,1,1,5];
1540 }
1541 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1542
1543 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1544   let Latency = 18;
1545   let NumMicroOps = 11;
1546   let ResourceCycles = [2,1,1,4,1,2];
1547 }
1548 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1549
1550 def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1551   let Latency = 19;
1552   let NumMicroOps = 2;
1553   let ResourceCycles = [1,1,4];
1554 }
1555 def : SchedAlias<WriteFDiv64Ld,  SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair
1556
1557 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1558   let Latency = 20;
1559   let NumMicroOps = 1;
1560   let ResourceCycles = [1];
1561 }
1562 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1563
1564 def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1565   let Latency = 20;
1566   let NumMicroOps = 2;
1567   let ResourceCycles = [1,1,4];
1568 }
1569 def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair
1570
1571 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1572   let Latency = 20;
1573   let NumMicroOps = 8;
1574   let ResourceCycles = [1,1,1,1,1,1,2];
1575 }
1576 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1577
1578 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1579   let Latency = 20;
1580   let NumMicroOps = 10;
1581   let ResourceCycles = [1,2,7];
1582 }
1583 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1584
1585 def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1586   let Latency = 21;
1587   let NumMicroOps = 2;
1588   let ResourceCycles = [1,1,8];
1589 }
1590 def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair
1591
1592 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1593   let Latency = 22;
1594   let NumMicroOps = 2;
1595   let ResourceCycles = [1,1];
1596 }
1597 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1598
1599 def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1600   let Latency = 22;
1601   let NumMicroOps = 5;
1602   let ResourceCycles = [1,2,1,1];
1603 }
1604 def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
1605                                              VGATHERDPDrm,
1606                                              VGATHERQPDrm,
1607                                              VGATHERQPSrm,
1608                                              VPGATHERDDrm,
1609                                              VPGATHERDQrm,
1610                                              VPGATHERQDrm,
1611                                              VPGATHERQQrm)>;
1612
1613 def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1614   let Latency = 25;
1615   let NumMicroOps = 5;
1616   let ResourceCycles = [1,2,1,1];
1617 }
1618 def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
1619                                              VGATHERQPDYrm,
1620                                              VGATHERQPSYrm,
1621                                              VPGATHERDDYrm,
1622                                              VPGATHERDQYrm,
1623                                              VPGATHERQDYrm,
1624                                              VPGATHERQQYrm,
1625                                              VGATHERDPDYrm)>;
1626
1627 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1628   let Latency = 23;
1629   let NumMicroOps = 19;
1630   let ResourceCycles = [2,1,4,1,1,4,6];
1631 }
1632 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1633
1634 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1635   let Latency = 25;
1636   let NumMicroOps = 3;
1637   let ResourceCycles = [1,1,1];
1638 }
1639 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1640
1641 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1642   let Latency = 27;
1643   let NumMicroOps = 2;
1644   let ResourceCycles = [1,1];
1645 }
1646 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1647
1648 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1649   let Latency = 30;
1650   let NumMicroOps = 3;
1651   let ResourceCycles = [1,1,1];
1652 }
1653 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1654
1655 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1656   let Latency = 35;
1657   let NumMicroOps = 23;
1658   let ResourceCycles = [1,5,3,4,10];
1659 }
1660 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1661                                               "IN(8|16|32)rr")>;
1662
1663 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1664   let Latency = 35;
1665   let NumMicroOps = 23;
1666   let ResourceCycles = [1,5,2,1,4,10];
1667 }
1668 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1669                                               "OUT(8|16|32)rr")>;
1670
1671 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1672   let Latency = 37;
1673   let NumMicroOps = 31;
1674   let ResourceCycles = [1,8,1,21];
1675 }
1676 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1677
1678 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1679   let Latency = 40;
1680   let NumMicroOps = 18;
1681   let ResourceCycles = [1,1,2,3,1,1,1,8];
1682 }
1683 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1684
1685 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1686   let Latency = 41;
1687   let NumMicroOps = 39;
1688   let ResourceCycles = [1,10,1,1,26];
1689 }
1690 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1691
1692 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1693   let Latency = 42;
1694   let NumMicroOps = 22;
1695   let ResourceCycles = [2,20];
1696 }
1697 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1698
1699 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1700   let Latency = 42;
1701   let NumMicroOps = 40;
1702   let ResourceCycles = [1,11,1,1,26];
1703 }
1704 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1705 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1706
1707 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1708   let Latency = 46;
1709   let NumMicroOps = 44;
1710   let ResourceCycles = [1,11,1,1,30];
1711 }
1712 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1713
1714 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1715   let Latency = 62;
1716   let NumMicroOps = 64;
1717   let ResourceCycles = [2,8,5,10,39];
1718 }
1719 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1720
1721 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1722   let Latency = 63;
1723   let NumMicroOps = 88;
1724   let ResourceCycles = [4,4,31,1,2,1,45];
1725 }
1726 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1727
1728 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1729   let Latency = 63;
1730   let NumMicroOps = 90;
1731   let ResourceCycles = [4,2,33,1,2,1,47];
1732 }
1733 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1734
1735 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1736   let Latency = 75;
1737   let NumMicroOps = 15;
1738   let ResourceCycles = [6,3,6];
1739 }
1740 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1741
1742 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1743   let Latency = 106;
1744   let NumMicroOps = 100;
1745   let ResourceCycles = [9,1,11,16,1,11,21,30];
1746 }
1747 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1748
1749 def: InstRW<[WriteZero], (instrs CLC)>;
1750
1751 } // SchedModel