lib/Target/X86/X86Subtarget.cpp

   1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the X86 specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "X86.h"
  14
  15 #include "X86CallLowering.h"
  16 #include "X86LegalizerInfo.h"
  17 #include "X86RegisterBankInfo.h"
  18 #include "X86Subtarget.h"
  19 #include "MCTargetDesc/X86BaseInfo.h"
  20 #include "X86TargetMachine.h"
  21 #include "llvm/ADT/Triple.h"
  22 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  24 #include "llvm/IR/Attributes.h"
  25 #include "llvm/IR/ConstantRange.h"
  26 #include "llvm/IR/Function.h"
  27 #include "llvm/IR/GlobalValue.h"
  28 #include "llvm/Support/Casting.h"
  29 #include "llvm/Support/CodeGen.h"
  30 #include "llvm/Support/CommandLine.h"
  31 #include "llvm/Support/Debug.h"
  32 #include "llvm/Support/ErrorHandling.h"
  33 #include "llvm/Support/raw_ostream.h"
  34 #include "llvm/Target/TargetMachine.h"
  35
  36 #if defined(_MSC_VER)
  37 #include <intrin.h>
  38 #endif
  39
  40 using namespace llvm;
  41
  42 #define DEBUG_TYPE "subtarget"
  43
  44 #define GET_SUBTARGETINFO_TARGET_DESC
  45 #define GET_SUBTARGETINFO_CTOR
  46 #include "X86GenSubtargetInfo.inc"
  47
  48 // Temporary option to control early if-conversion for x86 while adding machine
  49 // models.
  50 static cl::opt<bool>
  51 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
  52                cl::desc("Enable early if-conversion on X86"));
  53
  54
  55 /// Classify a blockaddress reference for the current subtarget according to how
  56 /// we should reference it in a non-pcrel context.
  57 unsigned char X86Subtarget::classifyBlockAddressReference() const {
  58   return classifyLocalReference(nullptr);
  59 }
  60
  61 /// Classify a global variable reference for the current subtarget according to
  62 /// how we should reference it in a non-pcrel context.
  63 unsigned char
  64 X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const {
  65   return classifyGlobalReference(GV, *GV->getParent());
  66 }
  67
  68 unsigned char
  69 X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
  70   // If we're not PIC, it's not very interesting.
  71   if (!isPositionIndependent())
  72     return X86II::MO_NO_FLAG;
  73
  74   if (is64Bit()) {
  75     // 64-bit ELF PIC local references may use GOTOFF relocations.
  76     if (isTargetELF()) {
  77       switch (TM.getCodeModel()) {
  78       // 64-bit small code model is simple: All rip-relative.
  79       case CodeModel::Tiny:
  80         llvm_unreachable("Tiny codesize model not supported on X86");
  81       case CodeModel::Small:
  82       case CodeModel::Kernel:
  83         return X86II::MO_NO_FLAG;
  84
  85       // The large PIC code model uses GOTOFF.
  86       case CodeModel::Large:
  87         return X86II::MO_GOTOFF;
  88
  89       // Medium is a hybrid: RIP-rel for code, GOTOFF for DSO local data.
  90       case CodeModel::Medium:
  91         if (isa<Function>(GV))
  92           return X86II::MO_NO_FLAG; // All code is RIP-relative
  93         return X86II::MO_GOTOFF;    // Local symbols use GOTOFF.
  94       }
  95       llvm_unreachable("invalid code model");
  96     }
  97
  98     // Otherwise, this is either a RIP-relative reference or a 64-bit movabsq,
  99     // both of which use MO_NO_FLAG.
 100     return X86II::MO_NO_FLAG;
 101   }
 102
 103   // The COFF dynamic linker just patches the executable sections.
 104   if (isTargetCOFF())
 105     return X86II::MO_NO_FLAG;
 106
 107   if (isTargetDarwin()) {
 108     // 32 bit macho has no relocation for a-b if a is undefined, even if
 109     // b is in the section that is being relocated.
 110     // This means we have to use o load even for GVs that are known to be
 111     // local to the dso.
 112     if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
 113       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
 114
 115     return X86II::MO_PIC_BASE_OFFSET;
 116   }
 117
 118   return X86II::MO_GOTOFF;
 119 }
 120
 121 unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV,
 122                                                     const Module &M) const {
 123   // The static large model never uses stubs.
 124   if (TM.getCodeModel() == CodeModel::Large && !isPositionIndependent())
 125     return X86II::MO_NO_FLAG;
 126
 127   // Absolute symbols can be referenced directly.
 128   if (GV) {
 129     if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) {
 130       // See if we can use the 8-bit immediate form. Note that some instructions
 131       // will sign extend the immediate operand, so to be conservative we only
 132       // accept the range [0,128).
 133       if (CR->getUnsignedMax().ult(128))
 134         return X86II::MO_ABS8;
 135       else
 136         return X86II::MO_NO_FLAG;
 137     }
 138   }
 139
 140   if (TM.shouldAssumeDSOLocal(M, GV))
 141     return classifyLocalReference(GV);
 142
 143   if (isTargetCOFF()) {
 144     if (GV->hasDLLImportStorageClass())
 145       return X86II::MO_DLLIMPORT;
 146     return X86II::MO_COFFSTUB;
 147   }
 148
 149   if (is64Bit()) {
 150     // ELF supports a large, truly PIC code model with non-PC relative GOT
 151     // references. Other object file formats do not. Use the no-flag, 64-bit
 152     // reference for them.
 153     if (TM.getCodeModel() == CodeModel::Large)
 154       return isTargetELF() ? X86II::MO_GOT : X86II::MO_NO_FLAG;
 155     return X86II::MO_GOTPCREL;
 156   }
 157
 158   if (isTargetDarwin()) {
 159     if (!isPositionIndependent())
 160       return X86II::MO_DARWIN_NONLAZY;
 161     return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
 162   }
 163
 164   return X86II::MO_GOT;
 165 }
 166
 167 unsigned char
 168 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
 169   return classifyGlobalFunctionReference(GV, *GV->getParent());
 170 }
 171
 172 unsigned char
 173 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
 174                                               const Module &M) const {
 175   if (TM.shouldAssumeDSOLocal(M, GV))
 176     return X86II::MO_NO_FLAG;
 177
 178   if (isTargetCOFF()) {
 179     assert(GV->hasDLLImportStorageClass() &&
 180            "shouldAssumeDSOLocal gave inconsistent answer");
 181     return X86II::MO_DLLIMPORT;
 182   }
 183
 184   const Function *F = dyn_cast_or_null<Function>(GV);
 185
 186   if (isTargetELF()) {
 187     if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
 188       // According to psABI, PLT stub clobbers XMM8-XMM15.
 189       // In Regcall calling convention those registers are used for passing
 190       // parameters. Thus we need to prevent lazy binding in Regcall.
 191       return X86II::MO_GOTPCREL;
 192     // If PLT must be avoided then the call should be via GOTPCREL.
 193     if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) ||
 194          (!F && M.getRtLibUseGOT())) &&
 195         is64Bit())
 196        return X86II::MO_GOTPCREL;
 197     return X86II::MO_PLT;
 198   }
 199
 200   if (is64Bit()) {
 201     if (F && F->hasFnAttribute(Attribute::NonLazyBind))
 202       // If the function is marked as non-lazy, generate an indirect call
 203       // which loads from the GOT directly. This avoids runtime overhead
 204       // at the cost of eager binding (and one extra byte of encoding).
 205       return X86II::MO_GOTPCREL;
 206     return X86II::MO_NO_FLAG;
 207   }
 208
 209   return X86II::MO_NO_FLAG;
 210 }
 211
 212 /// Return true if the subtarget allows calls to immediate address.
 213 bool X86Subtarget::isLegalToCallImmediateAddr() const {
 214   // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
 215   // but WinCOFFObjectWriter::RecordRelocation cannot emit them.  Once it does,
 216   // the following check for Win32 should be removed.
 217   if (In64BitMode || isTargetWin32())
 218     return false;
 219   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
 220 }
 221
 222 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 223   std::string CPUName = CPU;
 224   if (CPUName.empty())
 225     CPUName = "generic";
 226
 227   std::string FullFS = FS;
 228   if (In64BitMode) {
 229     // SSE2 should default to enabled in 64-bit mode, but can be turned off
 230     // explicitly.
 231     if (!FullFS.empty())
 232       FullFS = "+sse2," + FullFS;
 233     else
 234       FullFS = "+sse2";
 235
 236     // If no CPU was specified, enable 64bit feature to satisy later check.
 237     if (CPUName == "generic") {
 238       if (!FullFS.empty())
 239         FullFS = "+64bit," + FullFS;
 240       else
 241         FullFS = "+64bit";
 242     }
 243   }
 244
 245   // LAHF/SAHF are always supported in non-64-bit mode.
 246   if (!In64BitMode) {
 247     if (!FullFS.empty())
 248       FullFS = "+sahf," + FullFS;
 249     else
 250       FullFS = "+sahf";
 251   }
 252
 253   // Parse features string and set the CPU.
 254   ParseSubtargetFeatures(CPUName, FullFS);
 255
 256   // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
 257   // 16-bytes and under that are reasonably fast. These features were
 258   // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
 259   // micro-architectures respectively.
 260   if (hasSSE42() || hasSSE4A())
 261     IsUAMem16Slow = false;
 262
 263   // It's important to keep the MCSubtargetInfo feature bits in sync with
 264   // target data structure which is shared with MC code emitter, etc.
 265   if (In64BitMode)
 266     ToggleFeature(X86::Mode64Bit);
 267   else if (In32BitMode)
 268     ToggleFeature(X86::Mode32Bit);
 269   else if (In16BitMode)
 270     ToggleFeature(X86::Mode16Bit);
 271   else
 272     llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
 273
 274   LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
 275                     << ", 3DNowLevel " << X863DNowLevel << ", 64bit "
 276                     << HasX86_64 << "\n");
 277   if (In64BitMode && !HasX86_64)
 278     report_fatal_error("64-bit code requested on a subtarget that doesn't "
 279                        "support it!");
 280
 281   // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
 282   // 32 and 64 bit) and for all 64-bit targets.
 283   if (StackAlignOverride)
 284     stackAlignment = StackAlignOverride;
 285   else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
 286            isTargetKFreeBSD() || In64BitMode)
 287     stackAlignment = 16;
 288
 289   // Some CPUs have more overhead for gather. The specified overhead is relative
 290   // to the Load operation. "2" is the number provided by Intel architects. This
 291   // parameter is used for cost estimation of Gather Op and comparison with
 292   // other alternatives.
 293   // TODO: Remove the explicit hasAVX512()?, That would mean we would only
 294   // enable gather with a -march.
 295   if (hasAVX512() || (hasAVX2() && hasFastGather()))
 296     GatherOverhead = 2;
 297   if (hasAVX512())
 298     ScatterOverhead = 2;
 299
 300   // Consume the vector width attribute or apply any target specific limit.
 301   if (PreferVectorWidthOverride)
 302     PreferVectorWidth = PreferVectorWidthOverride;
 303   else if (Prefer256Bit)
 304     PreferVectorWidth = 256;
 305 }
 306
 307 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
 308                                                             StringRef FS) {
 309   initSubtargetFeatures(CPU, FS);
 310   return *this;
 311 }
 312
 313 X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
 314                            const X86TargetMachine &TM,
 315                            unsigned StackAlignOverride,
 316                            unsigned PreferVectorWidthOverride,
 317                            unsigned RequiredVectorWidth)
 318     : X86GenSubtargetInfo(TT, CPU, FS),
 319       PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
 320       StackAlignOverride(StackAlignOverride),
 321       PreferVectorWidthOverride(PreferVectorWidthOverride),
 322       RequiredVectorWidth(RequiredVectorWidth),
 323       In64BitMode(TargetTriple.getArch() == Triple::x86_64),
 324       In32BitMode(TargetTriple.getArch() == Triple::x86 &&
 325                   TargetTriple.getEnvironment() != Triple::CODE16),
 326       In16BitMode(TargetTriple.getArch() == Triple::x86 &&
 327                   TargetTriple.getEnvironment() == Triple::CODE16),
 328       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
 329       FrameLowering(*this, getStackAlignment()) {
 330   // Determine the PICStyle based on the target selected.
 331   if (!isPositionIndependent())
 332     setPICStyle(PICStyles::None);
 333   else if (is64Bit())
 334     setPICStyle(PICStyles::RIPRel);
 335   else if (isTargetCOFF())
 336     setPICStyle(PICStyles::None);
 337   else if (isTargetDarwin())
 338     setPICStyle(PICStyles::StubPIC);
 339   else if (isTargetELF())
 340     setPICStyle(PICStyles::GOT);
 341
 342   CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
 343   Legalizer.reset(new X86LegalizerInfo(*this, TM));
 344
 345   auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
 346   RegBankInfo.reset(RBI);
 347   InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
 348 }
 349
 350 const CallLowering *X86Subtarget::getCallLowering() const {
 351   return CallLoweringInfo.get();
 352 }
 353
 354 const InstructionSelector *X86Subtarget::getInstructionSelector() const {
 355   return InstSelector.get();
 356 }
 357
 358 const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
 359   return Legalizer.get();
 360 }
 361
 362 const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
 363   return RegBankInfo.get();
 364 }
 365
 366 bool X86Subtarget::enableEarlyIfConversion() const {
 367   return hasCMov() && X86EarlyIfConv;
 368 }