lib/Target/X86/X86Subtarget.h

   1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
  14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
  15
  16 #include "X86FrameLowering.h"
  17 #include "X86ISelLowering.h"
  18 #include "X86InstrInfo.h"
  19 #include "X86SelectionDAGInfo.h"
  20 #include "llvm/ADT/StringRef.h"
  21 #include "llvm/ADT/Triple.h"
  22 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  23 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  24 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  25 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  26 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  27 #include "llvm/IR/CallingConv.h"
  28 #include "llvm/Target/TargetMachine.h"
  29 #include <climits>
  30 #include <memory>
  31
  32 #define GET_SUBTARGETINFO_HEADER
  33 #include "X86GenSubtargetInfo.inc"
  34
  35 namespace llvm {
  36
  37 class GlobalValue;
  38
  39 /// The X86 backend supports a number of different styles of PIC.
  40 ///
  41 namespace PICStyles {
  42
  43 enum Style {
  44   StubPIC,          // Used on i386-darwin in pic mode.
  45   GOT,              // Used on 32 bit elf on when in pic mode.
  46   RIPRel,           // Used on X86-64 when in pic mode.
  47   None              // Set when not in pic mode.
  48 };
  49
  50 } // end namespace PICStyles
  51
  52 class X86Subtarget final : public X86GenSubtargetInfo {
  53 public:
  54   // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
  55   // are not a good idea. We should be migrating away from these.
  56   enum X86ProcFamilyEnum {
  57     Others,
  58     IntelAtom,
  59     IntelSLM,
  60     IntelGLM,
  61     IntelGLP,
  62     IntelTRM
  63   };
  64
  65 protected:
  66   enum X86SSEEnum {
  67     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
  68   };
  69
  70   enum X863DNowEnum {
  71     NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
  72   };
  73
  74   /// X86 processor family: Intel Atom, and others
  75   X86ProcFamilyEnum X86ProcFamily = Others;
  76
  77   /// Which PIC style to use
  78   PICStyles::Style PICStyle;
  79
  80   const TargetMachine &TM;
  81
  82   /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
  83   X86SSEEnum X86SSELevel = NoSSE;
  84
  85   /// MMX, 3DNow, 3DNow Athlon, or none supported.
  86   X863DNowEnum X863DNowLevel = NoThreeDNow;
  87
  88   /// True if the processor supports X87 instructions.
  89   bool HasX87 = false;
  90
  91   /// True if this processor has NOPL instruction
  92   /// (generally pentium pro+).
  93   bool HasNOPL = false;
  94
  95   /// True if this processor has conditional move instructions
  96   /// (generally pentium pro+).
  97   bool HasCMov = false;
  98
  99   /// True if the processor supports X86-64 instructions.
 100   bool HasX86_64 = false;
 101
 102   /// True if the processor supports POPCNT.
 103   bool HasPOPCNT = false;
 104
 105   /// True if the processor supports SSE4A instructions.
 106   bool HasSSE4A = false;
 107
 108   /// Target has AES instructions
 109   bool HasAES = false;
 110   bool HasVAES = false;
 111
 112   /// Target has FXSAVE/FXRESTOR instructions
 113   bool HasFXSR = false;
 114
 115   /// Target has XSAVE instructions
 116   bool HasXSAVE = false;
 117
 118   /// Target has XSAVEOPT instructions
 119   bool HasXSAVEOPT = false;
 120
 121   /// Target has XSAVEC instructions
 122   bool HasXSAVEC = false;
 123
 124   /// Target has XSAVES instructions
 125   bool HasXSAVES = false;
 126
 127   /// Target has carry-less multiplication
 128   bool HasPCLMUL = false;
 129   bool HasVPCLMULQDQ = false;
 130
 131   /// Target has Galois Field Arithmetic instructions
 132   bool HasGFNI = false;
 133
 134   /// Target has 3-operand fused multiply-add
 135   bool HasFMA = false;
 136
 137   /// Target has 4-operand fused multiply-add
 138   bool HasFMA4 = false;
 139
 140   /// Target has XOP instructions
 141   bool HasXOP = false;
 142
 143   /// Target has TBM instructions.
 144   bool HasTBM = false;
 145
 146   /// Target has LWP instructions
 147   bool HasLWP = false;
 148
 149   /// True if the processor has the MOVBE instruction.
 150   bool HasMOVBE = false;
 151
 152   /// True if the processor has the RDRAND instruction.
 153   bool HasRDRAND = false;
 154
 155   /// Processor has 16-bit floating point conversion instructions.
 156   bool HasF16C = false;
 157
 158   /// Processor has FS/GS base insturctions.
 159   bool HasFSGSBase = false;
 160
 161   /// Processor has LZCNT instruction.
 162   bool HasLZCNT = false;
 163
 164   /// Processor has BMI1 instructions.
 165   bool HasBMI = false;
 166
 167   /// Processor has BMI2 instructions.
 168   bool HasBMI2 = false;
 169
 170   /// Processor has VBMI instructions.
 171   bool HasVBMI = false;
 172
 173   /// Processor has VBMI2 instructions.
 174   bool HasVBMI2 = false;
 175
 176   /// Processor has Integer Fused Multiply Add
 177   bool HasIFMA = false;
 178
 179   /// Processor has RTM instructions.
 180   bool HasRTM = false;
 181
 182   /// Processor has ADX instructions.
 183   bool HasADX = false;
 184
 185   /// Processor has SHA instructions.
 186   bool HasSHA = false;
 187
 188   /// Processor has PRFCHW instructions.
 189   bool HasPRFCHW = false;
 190
 191   /// Processor has RDSEED instructions.
 192   bool HasRDSEED = false;
 193
 194   /// Processor has LAHF/SAHF instructions.
 195   bool HasLAHFSAHF = false;
 196
 197   /// Processor has MONITORX/MWAITX instructions.
 198   bool HasMWAITX = false;
 199
 200   /// Processor has Cache Line Zero instruction
 201   bool HasCLZERO = false;
 202
 203   /// Processor has Cache Line Demote instruction
 204   bool HasCLDEMOTE = false;
 205
 206   /// Processor has MOVDIRI instruction (direct store integer).
 207   bool HasMOVDIRI = false;
 208
 209   /// Processor has MOVDIR64B instruction (direct store 64 bytes).
 210   bool HasMOVDIR64B = false;
 211
 212   /// Processor has ptwrite instruction.
 213   bool HasPTWRITE = false;
 214
 215   /// Processor has Prefetch with intent to Write instruction
 216   bool HasPREFETCHWT1 = false;
 217
 218   /// True if SHLD instructions are slow.
 219   bool IsSHLDSlow = false;
 220
 221   /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
 222   //  PMULUDQ.
 223   bool IsPMULLDSlow = false;
 224
 225   /// True if the PMADDWD instruction is slow compared to PMULLD.
 226   bool IsPMADDWDSlow = false;
 227
 228   /// True if unaligned memory accesses of 16-bytes are slow.
 229   bool IsUAMem16Slow = false;
 230
 231   /// True if unaligned memory accesses of 32-bytes are slow.
 232   bool IsUAMem32Slow = false;
 233
 234   /// True if SSE operations can have unaligned memory operands.
 235   /// This may require setting a configuration bit in the processor.
 236   bool HasSSEUnalignedMem = false;
 237
 238   /// True if this processor has the CMPXCHG16B instruction;
 239   /// this is true for most x86-64 chips, but not the first AMD chips.
 240   bool HasCmpxchg16b = false;
 241
 242   /// True if the LEA instruction should be used for adjusting
 243   /// the stack pointer. This is an optimization for Intel Atom processors.
 244   bool UseLeaForSP = false;
 245
 246   /// True if POPCNT instruction has a false dependency on the destination register.
 247   bool HasPOPCNTFalseDeps = false;
 248
 249   /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
 250   bool HasLZCNTFalseDeps = false;
 251
 252   /// True if its preferable to combine to a single shuffle using a variable
 253   /// mask over multiple fixed shuffles.
 254   bool HasFastVariableShuffle = false;
 255
 256   /// True if there is no performance penalty to writing only the lower parts
 257   /// of a YMM or ZMM register without clearing the upper part.
 258   bool HasFastPartialYMMorZMMWrite = false;
 259
 260   /// True if there is no performance penalty for writing NOPs with up to
 261   /// 11 bytes.
 262   bool HasFast11ByteNOP = false;
 263
 264   /// True if there is no performance penalty for writing NOPs with up to
 265   /// 15 bytes.
 266   bool HasFast15ByteNOP = false;
 267
 268   /// True if gather is reasonably fast. This is true for Skylake client and
 269   /// all AVX-512 CPUs.
 270   bool HasFastGather = false;
 271
 272   /// True if hardware SQRTSS instruction is at least as fast (latency) as
 273   /// RSQRTSS followed by a Newton-Raphson iteration.
 274   bool HasFastScalarFSQRT = false;
 275
 276   /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
 277   /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
 278   bool HasFastVectorFSQRT = false;
 279
 280   /// True if 8-bit divisions are significantly faster than
 281   /// 32-bit divisions and should be used when possible.
 282   bool HasSlowDivide32 = false;
 283
 284   /// True if 32-bit divides are significantly faster than
 285   /// 64-bit divisions and should be used when possible.
 286   bool HasSlowDivide64 = false;
 287
 288   /// True if LZCNT instruction is fast.
 289   bool HasFastLZCNT = false;
 290
 291   /// True if SHLD based rotate is fast.
 292   bool HasFastSHLDRotate = false;
 293
 294   /// True if the processor supports macrofusion.
 295   bool HasMacroFusion = false;
 296
 297   /// True if the processor has enhanced REP MOVSB/STOSB.
 298   bool HasERMSB = false;
 299
 300   /// True if the short functions should be padded to prevent
 301   /// a stall when returning too early.
 302   bool PadShortFunctions = false;
 303
 304   /// True if two memory operand instructions should use a temporary register
 305   /// instead.
 306   bool SlowTwoMemOps = false;
 307
 308   /// True if the LEA instruction inputs have to be ready at address generation
 309   /// (AG) time.
 310   bool LEAUsesAG = false;
 311
 312   /// True if the LEA instruction with certain arguments is slow
 313   bool SlowLEA = false;
 314
 315   /// True if the LEA instruction has all three source operands: base, index,
 316   /// and offset or if the LEA instruction uses base and index registers where
 317   /// the base is EBP, RBP,or R13
 318   bool Slow3OpsLEA = false;
 319
 320   /// True if INC and DEC instructions are slow when writing to flags
 321   bool SlowIncDec = false;
 322
 323   /// Processor has AVX-512 PreFetch Instructions
 324   bool HasPFI = false;
 325
 326   /// Processor has AVX-512 Exponential and Reciprocal Instructions
 327   bool HasERI = false;
 328
 329   /// Processor has AVX-512 Conflict Detection Instructions
 330   bool HasCDI = false;
 331
 332   /// Processor has AVX-512 population count Instructions
 333   bool HasVPOPCNTDQ = false;
 334
 335   /// Processor has AVX-512 Doubleword and Quadword instructions
 336   bool HasDQI = false;
 337
 338   /// Processor has AVX-512 Byte and Word instructions
 339   bool HasBWI = false;
 340
 341   /// Processor has AVX-512 Vector Length eXtenstions
 342   bool HasVLX = false;
 343
 344   /// Processor has PKU extenstions
 345   bool HasPKU = false;
 346
 347   /// Processor has AVX-512 Vector Neural Network Instructions
 348   bool HasVNNI = false;
 349
 350   /// Processor has AVX-512 Bit Algorithms instructions
 351   bool HasBITALG = false;
 352
 353   /// Processor supports MPX - Memory Protection Extensions
 354   bool HasMPX = false;
 355
 356   /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
 357   /// using Shadow Stack
 358   bool HasSHSTK = false;
 359
 360   /// Processor supports Invalidate Process-Context Identifier
 361   bool HasINVPCID = false;
 362
 363   /// Processor has Software Guard Extensions
 364   bool HasSGX = false;
 365
 366   /// Processor supports Flush Cache Line instruction
 367   bool HasCLFLUSHOPT = false;
 368
 369   /// Processor supports Cache Line Write Back instruction
 370   bool HasCLWB = false;
 371
 372   /// Processor supports Write Back No Invalidate instruction
 373   bool HasWBNOINVD = false;
 374
 375   /// Processor support RDPID instruction
 376   bool HasRDPID = false;
 377
 378   /// Processor supports WaitPKG instructions
 379   bool HasWAITPKG = false;
 380
 381   /// Processor supports PCONFIG instruction
 382   bool HasPCONFIG = false;
 383
 384   /// Processor has a single uop BEXTR implementation.
 385   bool HasFastBEXTR = false;
 386
 387   /// Try harder to combine to horizontal vector ops if they are fast.
 388   bool HasFastHorizontalOps = false;
 389
 390   /// Use a retpoline thunk rather than indirect calls to block speculative
 391   /// execution.
 392   bool UseRetpolineIndirectCalls = false;
 393
 394   /// Use a retpoline thunk or remove any indirect branch to block speculative
 395   /// execution.
 396   bool UseRetpolineIndirectBranches = false;
 397
 398   /// Deprecated flag, query `UseRetpolineIndirectCalls` and
 399   /// `UseRetpolineIndirectBranches` instead.
 400   bool DeprecatedUseRetpoline = false;
 401
 402   /// When using a retpoline thunk, call an externally provided thunk rather
 403   /// than emitting one inside the compiler.
 404   bool UseRetpolineExternalThunk = false;
 405
 406   /// Use software floating point for code generation.
 407   bool UseSoftFloat = false;
 408
 409   /// The minimum alignment known to hold of the stack frame on
 410   /// entry to the function and which must be maintained by every function.
 411   unsigned stackAlignment = 4;
 412
 413   /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
 414   ///
 415   // FIXME: this is a known good value for Yonah. How about others?
 416   unsigned MaxInlineSizeThreshold = 128;
 417
 418   /// Indicates target prefers 256 bit instructions.
 419   bool Prefer256Bit = false;
 420
 421   /// Threeway branch is profitable in this subtarget.
 422   bool ThreewayBranchProfitable = false;
 423
 424   /// What processor and OS we're targeting.
 425   Triple TargetTriple;
 426
 427   /// GlobalISel related APIs.
 428   std::unique_ptr<CallLowering> CallLoweringInfo;
 429   std::unique_ptr<LegalizerInfo> Legalizer;
 430   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 431   std::unique_ptr<InstructionSelector> InstSelector;
 432
 433 private:
 434   /// Override the stack alignment.
 435   unsigned StackAlignOverride;
 436
 437   /// Preferred vector width from function attribute.
 438   unsigned PreferVectorWidthOverride;
 439
 440   /// Resolved preferred vector width from function attribute and subtarget
 441   /// features.
 442   unsigned PreferVectorWidth = UINT32_MAX;
 443
 444   /// Required vector width from function attribute.
 445   unsigned RequiredVectorWidth;
 446
 447   /// True if compiling for 64-bit, false for 16-bit or 32-bit.
 448   bool In64BitMode;
 449
 450   /// True if compiling for 32-bit, false for 16-bit or 64-bit.
 451   bool In32BitMode;
 452
 453   /// True if compiling for 16-bit, false for 32-bit or 64-bit.
 454   bool In16BitMode;
 455
 456   /// Contains the Overhead of gather\scatter instructions
 457   int GatherOverhead = 1024;
 458   int ScatterOverhead = 1024;
 459
 460   X86SelectionDAGInfo TSInfo;
 461   // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
 462   // X86TargetLowering needs.
 463   X86InstrInfo InstrInfo;
 464   X86TargetLowering TLInfo;
 465   X86FrameLowering FrameLowering;
 466
 467 public:
 468   /// This constructor initializes the data members to match that
 469   /// of the specified triple.
 470   ///
 471   X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
 472                const X86TargetMachine &TM, unsigned StackAlignOverride,
 473                unsigned PreferVectorWidthOverride,
 474                unsigned RequiredVectorWidth);
 475
 476   const X86TargetLowering *getTargetLowering() const override {
 477     return &TLInfo;
 478   }
 479
 480   const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
 481
 482   const X86FrameLowering *getFrameLowering() const override {
 483     return &FrameLowering;
 484   }
 485
 486   const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
 487     return &TSInfo;
 488   }
 489
 490   const X86RegisterInfo *getRegisterInfo() const override {
 491     return &getInstrInfo()->getRegisterInfo();
 492   }
 493
 494   /// Returns the minimum alignment known to hold of the
 495   /// stack frame on entry to the function and which must be maintained by every
 496   /// function for this subtarget.
 497   unsigned getStackAlignment() const { return stackAlignment; }
 498
 499   /// Returns the maximum memset / memcpy size
 500   /// that still makes it profitable to inline the call.
 501   unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
 502
 503   /// ParseSubtargetFeatures - Parses features string setting specified
 504   /// subtarget options.  Definition of function is auto generated by tblgen.
 505   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 506
 507   /// Methods used by Global ISel
 508   const CallLowering *getCallLowering() const override;
 509   const InstructionSelector *getInstructionSelector() const override;
 510   const LegalizerInfo *getLegalizerInfo() const override;
 511   const RegisterBankInfo *getRegBankInfo() const override;
 512
 513 private:
 514   /// Initialize the full set of dependencies so we can use an initializer
 515   /// list for X86Subtarget.
 516   X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 517   void initSubtargetFeatures(StringRef CPU, StringRef FS);
 518
 519 public:
 520   /// Is this x86_64? (disregarding specific ABI / programming model)
 521   bool is64Bit() const {
 522     return In64BitMode;
 523   }
 524
 525   bool is32Bit() const {
 526     return In32BitMode;
 527   }
 528
 529   bool is16Bit() const {
 530     return In16BitMode;
 531   }
 532
 533   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
 534   bool isTarget64BitILP32() const {
 535     return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
 536                            TargetTriple.isOSNaCl());
 537   }
 538
 539   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
 540   bool isTarget64BitLP64() const {
 541     return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
 542                            !TargetTriple.isOSNaCl());
 543   }
 544
 545   PICStyles::Style getPICStyle() const { return PICStyle; }
 546   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
 547
 548   bool hasX87() const { return HasX87; }
 549   bool hasNOPL() const { return HasNOPL; }
 550   // SSE codegen depends on cmovs, and all SSE1+ processors support them.
 551   // All 64-bit processors support cmov.
 552   bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
 553   bool hasSSE1() const { return X86SSELevel >= SSE1; }
 554   bool hasSSE2() const { return X86SSELevel >= SSE2; }
 555   bool hasSSE3() const { return X86SSELevel >= SSE3; }
 556   bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
 557   bool hasSSE41() const { return X86SSELevel >= SSE41; }
 558   bool hasSSE42() const { return X86SSELevel >= SSE42; }
 559   bool hasAVX() const { return X86SSELevel >= AVX; }
 560   bool hasAVX2() const { return X86SSELevel >= AVX2; }
 561   bool hasAVX512() const { return X86SSELevel >= AVX512F; }
 562   bool hasInt256() const { return hasAVX2(); }
 563   bool hasSSE4A() const { return HasSSE4A; }
 564   bool hasMMX() const { return X863DNowLevel >= MMX; }
 565   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
 566   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
 567   bool hasPOPCNT() const { return HasPOPCNT; }
 568   bool hasAES() const { return HasAES; }
 569   bool hasVAES() const { return HasVAES; }
 570   bool hasFXSR() const { return HasFXSR; }
 571   bool hasXSAVE() const { return HasXSAVE; }
 572   bool hasXSAVEOPT() const { return HasXSAVEOPT; }
 573   bool hasXSAVEC() const { return HasXSAVEC; }
 574   bool hasXSAVES() const { return HasXSAVES; }
 575   bool hasPCLMUL() const { return HasPCLMUL; }
 576   bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
 577   bool hasGFNI() const { return HasGFNI; }
 578   // Prefer FMA4 to FMA - its better for commutation/memory folding and
 579   // has equal or better performance on all supported targets.
 580   bool hasFMA() const { return HasFMA; }
 581   bool hasFMA4() const { return HasFMA4; }
 582   bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
 583   bool hasXOP() const { return HasXOP; }
 584   bool hasTBM() const { return HasTBM; }
 585   bool hasLWP() const { return HasLWP; }
 586   bool hasMOVBE() const { return HasMOVBE; }
 587   bool hasRDRAND() const { return HasRDRAND; }
 588   bool hasF16C() const { return HasF16C; }
 589   bool hasFSGSBase() const { return HasFSGSBase; }
 590   bool hasLZCNT() const { return HasLZCNT; }
 591   bool hasBMI() const { return HasBMI; }
 592   bool hasBMI2() const { return HasBMI2; }
 593   bool hasVBMI() const { return HasVBMI; }
 594   bool hasVBMI2() const { return HasVBMI2; }
 595   bool hasIFMA() const { return HasIFMA; }
 596   bool hasRTM() const { return HasRTM; }
 597   bool hasADX() const { return HasADX; }
 598   bool hasSHA() const { return HasSHA; }
 599   bool hasPRFCHW() const { return HasPRFCHW || HasPREFETCHWT1; }
 600   bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
 601   bool hasSSEPrefetch() const {
 602     // We implicitly enable these when we have a write prefix supporting cache
 603     // level OR if we have prfchw, but don't already have a read prefetch from
 604     // 3dnow.
 605     return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
 606   }
 607   bool hasRDSEED() const { return HasRDSEED; }
 608   bool hasLAHFSAHF() const { return HasLAHFSAHF; }
 609   bool hasMWAITX() const { return HasMWAITX; }
 610   bool hasCLZERO() const { return HasCLZERO; }
 611   bool hasCLDEMOTE() const { return HasCLDEMOTE; }
 612   bool hasMOVDIRI() const { return HasMOVDIRI; }
 613   bool hasMOVDIR64B() const { return HasMOVDIR64B; }
 614   bool hasPTWRITE() const { return HasPTWRITE; }
 615   bool isSHLDSlow() const { return IsSHLDSlow; }
 616   bool isPMULLDSlow() const { return IsPMULLDSlow; }
 617   bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
 618   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
 619   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
 620   int getGatherOverhead() const { return GatherOverhead; }
 621   int getScatterOverhead() const { return ScatterOverhead; }
 622   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
 623   bool hasCmpxchg16b() const { return HasCmpxchg16b; }
 624   bool useLeaForSP() const { return UseLeaForSP; }
 625   bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
 626   bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
 627   bool hasFastVariableShuffle() const {
 628     return HasFastVariableShuffle;
 629   }
 630   bool hasFastPartialYMMorZMMWrite() const {
 631     return HasFastPartialYMMorZMMWrite;
 632   }
 633   bool hasFastGather() const { return HasFastGather; }
 634   bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
 635   bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
 636   bool hasFastLZCNT() const { return HasFastLZCNT; }
 637   bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
 638   bool hasFastBEXTR() const { return HasFastBEXTR; }
 639   bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
 640   bool hasMacroFusion() const { return HasMacroFusion; }
 641   bool hasERMSB() const { return HasERMSB; }
 642   bool hasSlowDivide32() const { return HasSlowDivide32; }
 643   bool hasSlowDivide64() const { return HasSlowDivide64; }
 644   bool padShortFunctions() const { return PadShortFunctions; }
 645   bool slowTwoMemOps() const { return SlowTwoMemOps; }
 646   bool LEAusesAG() const { return LEAUsesAG; }
 647   bool slowLEA() const { return SlowLEA; }
 648   bool slow3OpsLEA() const { return Slow3OpsLEA; }
 649   bool slowIncDec() const { return SlowIncDec; }
 650   bool hasCDI() const { return HasCDI; }
 651   bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
 652   bool hasPFI() const { return HasPFI; }
 653   bool hasERI() const { return HasERI; }
 654   bool hasDQI() const { return HasDQI; }
 655   bool hasBWI() const { return HasBWI; }
 656   bool hasVLX() const { return HasVLX; }
 657   bool hasPKU() const { return HasPKU; }
 658   bool hasVNNI() const { return HasVNNI; }
 659   bool hasBITALG() const { return HasBITALG; }
 660   bool hasMPX() const { return HasMPX; }
 661   bool hasSHSTK() const { return HasSHSTK; }
 662   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
 663   bool hasCLWB() const { return HasCLWB; }
 664   bool hasWBNOINVD() const { return HasWBNOINVD; }
 665   bool hasRDPID() const { return HasRDPID; }
 666   bool hasWAITPKG() const { return HasWAITPKG; }
 667   bool hasPCONFIG() const { return HasPCONFIG; }
 668   bool hasSGX() const { return HasSGX; }
 669   bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
 670   bool hasINVPCID() const { return HasINVPCID; }
 671   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
 672   bool useRetpolineIndirectBranches() const {
 673     return UseRetpolineIndirectBranches;
 674   }
 675   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
 676
 677   unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
 678   unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
 679
 680   // Helper functions to determine when we should allow widening to 512-bit
 681   // during codegen.
 682   // TODO: Currently we're always allowing widening on CPUs without VLX,
 683   // because for many cases we don't have a better option.
 684   bool canExtendTo512DQ() const {
 685     return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
 686   }
 687   bool canExtendTo512BW() const  {
 688     return hasBWI() && canExtendTo512DQ();
 689   }
 690
 691   // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
 692   // disable them in the legalizer.
 693   bool useAVX512Regs() const {
 694     return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
 695   }
 696
 697   bool useBWIRegs() const {
 698     return hasBWI() && useAVX512Regs();
 699   }
 700
 701   bool isXRaySupported() const override { return is64Bit(); }
 702
 703   X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; }
 704
 705   /// TODO: to be removed later and replaced with suitable properties
 706   bool isAtom() const { return X86ProcFamily == IntelAtom; }
 707   bool isSLM() const { return X86ProcFamily == IntelSLM; }
 708   bool isGLM() const {
 709     return X86ProcFamily == IntelGLM ||
 710            X86ProcFamily == IntelGLP ||
 711            X86ProcFamily == IntelTRM;
 712   }
 713   bool useSoftFloat() const { return UseSoftFloat; }
 714
 715   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
 716   /// no-sse2). There isn't any reason to disable it if the target processor
 717   /// supports it.
 718   bool hasMFence() const { return hasSSE2() || is64Bit(); }
 719
 720   const Triple &getTargetTriple() const { return TargetTriple; }
 721
 722   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 723   bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
 724   bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
 725   bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
 726   bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
 727
 728   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 729   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
 730   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 731
 732   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 733   bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
 734   bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
 735   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
 736   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
 737   bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
 738   bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
 739   bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
 740   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 741
 742   bool isTargetWindowsMSVC() const {
 743     return TargetTriple.isWindowsMSVCEnvironment();
 744   }
 745
 746   bool isTargetKnownWindowsMSVC() const {
 747     return TargetTriple.isKnownWindowsMSVCEnvironment();
 748   }
 749
 750   bool isTargetWindowsCoreCLR() const {
 751     return TargetTriple.isWindowsCoreCLREnvironment();
 752   }
 753
 754   bool isTargetWindowsCygwin() const {
 755     return TargetTriple.isWindowsCygwinEnvironment();
 756   }
 757
 758   bool isTargetWindowsGNU() const {
 759     return TargetTriple.isWindowsGNUEnvironment();
 760   }
 761
 762   bool isTargetWindowsItanium() const {
 763     return TargetTriple.isWindowsItaniumEnvironment();
 764   }
 765
 766   bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
 767
 768   bool isOSWindows() const { return TargetTriple.isOSWindows(); }
 769
 770   bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
 771
 772   bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
 773
 774   bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
 775   bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
 776
 777   bool isPICStyleStubPIC() const {
 778     return PICStyle == PICStyles::StubPIC;
 779   }
 780
 781   bool isPositionIndependent() const { return TM.isPositionIndependent(); }
 782
 783   bool isCallingConvWin64(CallingConv::ID CC) const {
 784     switch (CC) {
 785     // On Win64, all these conventions just use the default convention.
 786     case CallingConv::C:
 787     case CallingConv::Fast:
 788     case CallingConv::Swift:
 789     case CallingConv::X86_FastCall:
 790     case CallingConv::X86_StdCall:
 791     case CallingConv::X86_ThisCall:
 792     case CallingConv::X86_VectorCall:
 793     case CallingConv::Intel_OCL_BI:
 794       return isTargetWin64();
 795     // This convention allows using the Win64 convention on other targets.
 796     case CallingConv::Win64:
 797       return true;
 798     // This convention allows using the SysV convention on Windows targets.
 799     case CallingConv::X86_64_SysV:
 800       return false;
 801     // Otherwise, who knows what this is.
 802     default:
 803       return false;
 804     }
 805   }
 806
 807   /// Classify a global variable reference for the current subtarget according
 808   /// to how we should reference it in a non-pcrel context.
 809   unsigned char classifyLocalReference(const GlobalValue *GV) const;
 810
 811   unsigned char classifyGlobalReference(const GlobalValue *GV,
 812                                         const Module &M) const;
 813   unsigned char classifyGlobalReference(const GlobalValue *GV) const;
 814
 815   /// Classify a global function reference for the current subtarget.
 816   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
 817                                                 const Module &M) const;
 818   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
 819
 820   /// Classify a blockaddress reference for the current subtarget according to
 821   /// how we should reference it in a non-pcrel context.
 822   unsigned char classifyBlockAddressReference() const;
 823
 824   /// Return true if the subtarget allows calls to immediate address.
 825   bool isLegalToCallImmediateAddr() const;
 826
 827   /// If we are using retpolines, we need to expand indirectbr to avoid it
 828   /// lowering to an actual indirect jump.
 829   bool enableIndirectBrExpand() const override {
 830     return useRetpolineIndirectBranches();
 831   }
 832
 833   /// Enable the MachineScheduler pass for all X86 subtargets.
 834   bool enableMachineScheduler() const override { return true; }
 835
 836   bool enableEarlyIfConversion() const override;
 837
 838   AntiDepBreakMode getAntiDepBreakMode() const override {
 839     return TargetSubtargetInfo::ANTIDEP_CRITICAL;
 840   }
 841
 842   bool enableAdvancedRASplitCost() const override { return true; }
 843 };
 844
 845 } // end namespace llvm
 846
 847 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H