1 # RUN: llc -o - %s -mtriple=thumb-arm-none-eabi -mcpu=cortex-m0 -run-pass scavenger-test | FileCheck %s
3 # CHECK-LABEL: name: scavengebug0
4 # Make sure we are not spilling/using a physreg used in the very last
5 # instruction of the scavenging range.
6 # CHECK-NOT: tSTRi {{.*}}$r0,{{.*}}$r0
7 # CHECK-NOT: tSTRi {{.*}}$r1,{{.*}}$r1
8 # CHECK-NOT: tSTRi {{.*}}$r2,{{.*}}$r2
9 # CHECK-NOT: tSTRi {{.*}}$r3,{{.*}}$r3
10 # CHECK-NOT: tSTRi {{.*}}$r4,{{.*}}$r4
11 # CHECK-NOT: tSTRi {{.*}}$r5,{{.*}}$r5
12 # CHECK-NOT: tSTRi {{.*}}$r6,{{.*}}$r6
13 # CHECK-NOT: tSTRi {{.*}}$r7,{{.*}}$r7
17 ; Bring up register pressure to force emergency spilling
27 %0 : tgpr = IMPLICIT_DEF
28 %0 = tADDhirr %0, $sp, 14, $noreg
29 tSTRi $r0, %0, 0, 14, $noreg
31 %1 : tgpr = IMPLICIT_DEF
32 %1 = tADDhirr %1, $sp, 14, $noreg
33 tSTRi $r1, %1, 0, 14, $noreg
35 %2 : tgpr = IMPLICIT_DEF
36 %2 = tADDhirr %2, $sp, 14, $noreg
37 tSTRi $r2, %2, 0, 14, $noreg
39 %3 : tgpr = IMPLICIT_DEF
40 %3 = tADDhirr %3, $sp, 14, $noreg
41 tSTRi $r3, %3, 0, 14, $noreg
43 %4 : tgpr = IMPLICIT_DEF
44 %4 = tADDhirr %4, $sp, 14, $noreg
45 tSTRi $r4, %4, 0, 14, $noreg
47 %5 : tgpr = IMPLICIT_DEF
48 %5 = tADDhirr %5, $sp, 14, $noreg
49 tSTRi $r5, %5, 0, 14, $noreg
51 %6 : tgpr = IMPLICIT_DEF
52 %6 = tADDhirr %6, $sp, 14, $noreg
53 tSTRi $r6, %6, 0, 14, $noreg
55 %7 : tgpr = IMPLICIT_DEF
56 %7 = tADDhirr %7, $sp, 14, $noreg
57 tSTRi $r7, %7, 0, 14, $noreg