1 ; RUN: llc -fast-isel-sink-local-values -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
2 ; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \
3 ; RUN: FileCheck %s -check-prefixes=ALL,32R1
4 ; RUN: llc -fast-isel-sink-local-values -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
5 ; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \
6 ; RUN: FileCheck %s -check-prefixes=ALL,32R2
13 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10
15 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24
16 ; 32R1: sra $4, $[[T1]], 24
18 ; 32R2: seb $4, $[[T0]]
28 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10
30 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16
31 ; 32R1: sra $4, $[[T1]], 16
33 ; 32R2: seh $4, $[[T0]]
43 ; ALL-DAG: addiu $4, $zero, 10
44 ; ALL-DAG: lw $25, %got(xi)(${{[0-9]+}})
50 declare void @xbb(i8, i8)
55 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
56 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
58 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24
59 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24
60 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
61 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
63 ; 32R2-DAG: seb $4, $[[T0]]
64 ; 32R2-DAG: seb $5, $[[T1]]
65 call void @xbb(i8 76, i8 101)
69 declare void @xhh(i16, i16)
74 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
75 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
77 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
78 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16
79 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
80 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
82 ; 32R2-DAG: seh $4, $[[T0]]
83 ; 32R2-DAG: seh $5, $[[T1]]
84 call void @xhh(i16 76, i16 101)
88 declare void @xii(i32, i32)
93 ; ALL-DAG: addiu $4, $zero, 746
94 ; ALL-DAG: addiu $5, $zero, 892
95 ; ALL-DAG: lw $25, %got(xii)(${{[0-9]+}})
97 call void @xii(i32 746, i32 892)
101 declare void @xccc(i8, i8, i8)
103 define void @cxccc() {
106 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
107 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
108 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
110 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24
111 ; 32R1-DAG: sra $4, $[[T3]], 24
112 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
113 ; 32R1-DAG: sra $5, $[[T4]], 24
114 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24
115 ; 32R1-DAG: sra $6, $[[T5]], 24
117 ; 32R2-DAG: seb $4, $[[T0]]
118 ; 32R2-DAG: seb $5, $[[T1]]
119 ; 32R2-DAG: seb $6, $[[T2]]
120 call void @xccc(i8 88, i8 44, i8 11)
124 declare void @xhhh(i16, i16, i16)
126 define void @cxhhh() {
129 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
130 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
131 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
133 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16
134 ; 32R1-DAG: sra $4, $[[T3]], 16
135 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
136 ; 32R1-DAG: sra $5, $[[T4]], 16
137 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
138 ; 32R1-DAG: sra $6, $[[T5]], 16
140 ; 32R2-DAG: seh $4, $[[T0]]
141 ; 32R2-DAG: seh $5, $[[T1]]
142 ; 32R2-DAG: seh $6, $[[T2]]
143 call void @xhhh(i16 88, i16 44, i16 11)
147 declare void @xiii(i32, i32, i32)
149 define void @cxiii() {
152 ; ALL-DAG: addiu $4, $zero, 88
153 ; ALL-DAG: addiu $5, $zero, 44
154 ; ALL-DAG: addiu $6, $zero, 11
155 ; ALL-DAG: lw $25, %got(xiii)(${{[0-9]+}})
157 call void @xiii(i32 88, i32 44, i32 11)
161 declare void @xcccc(i8, i8, i8, i8)
163 define void @cxcccc() {
166 ; ALL: addiu $[[R:[0-9]+]], $zero, 88
167 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24
168 ; 32R1: sra $4, $[[R]], 24
169 ; 32R2: seb $4, $[[R]]
170 ; ALL: addiu $[[R:[0-9]+]], $zero, 44
171 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24
172 ; 32R1: sra $5, $[[R]], 24
173 ; 32R2: seb $5, $[[R]]
174 ; ALL: addiu $[[R:[0-9]+]], $zero, 11
175 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24
176 ; 32R1: sra $6, $[[R]], 24
177 ; 32R2: seb $6, $[[R]]
178 ; ALL: addiu $[[R:[0-9]+]], $zero, 33
179 ; 32R1: sll $[[R:[0-9]+]], $[[R]], 24
180 ; 32R1: sra $7, $[[R]], 24
181 ; 32R2: seb $7, $[[R]]
183 ; ALL: lw $25, %got(xcccc)(${{[0-9]+}})
186 call void @xcccc(i8 88, i8 44, i8 11, i8 33)
190 declare void @xhhhh(i16, i16, i16, i16)
192 define void @cxhhhh() {
195 ; ALL: addiu $[[R:[0-9]+]], $zero, 88
196 ; 32R1: sll $[[R]], $[[R]], 16
197 ; 32R1: sra $4, $[[R]], 16
198 ; 32R2: seh $4, $[[R]]
199 ; ALL: addiu $[[R:[0-9]+]], $zero, 44
200 ; 32R1: sll $[[R]], $[[R]], 16
201 ; 32R1: sra $5, $[[R]], 16
202 ; 32R2: seh $5, $[[R]]
203 ; ALL: addiu $[[R:[0-9]+]], $zero, 11
204 ; 32R1: sll $[[R]], $[[R]], 16
205 ; 32R1: sra $6, $[[R]], 16
206 ; 32R2: seh $6, $[[R]]
207 ; ALL: addiu $[[R:[0-9]+]], $zero, 33
208 ; 32R1: sll $[[R]], $[[R]], 16
209 ; 32R1: sra $7, $[[R]], 16
210 ; 32R2: seh $7, $[[R]]
212 ; ALL: lw $25, %got(xhhhh)(${{[0-9]+}})
216 call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
220 declare void @xiiii(i32, i32, i32, i32)
222 define void @cxiiii() {
225 ; ALL-DAG: addiu $4, $zero, 167
226 ; ALL-DAG: addiu $5, $zero, 320
227 ; ALL-DAG: addiu $6, $zero, 97
228 ; ALL-DAG: addiu $7, $zero, 14
229 ; ALL-DAG: lw $25, %got(xiiii)(${{[0-9]+}})
231 call void @xiiii(i32 167, i32 320, i32 97, i32 14)
235 @c1 = global i8 -45, align 1
236 @uc1 = global i8 27, align 1
237 @s1 = global i16 -1789, align 2
238 @us1 = global i16 1256, align 2
240 define void @cxiiiiconv() {
241 ; ALL-LABEL: cxiiiiconv:
243 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
244 ; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
245 ; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
246 ; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
247 ; 32R1-DAG: sra $4, $[[REG_C1_1]], 24
248 ; 32R2-DAG: seb $4, $[[REG_C1]]
249 ; FIXME: andi is superfulous
250 ; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
251 ; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
252 ; ALL-DAG: andi $5, $[[REG_UC1]], 255
253 ; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
254 ; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
255 ; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
256 ; 32R1-DAG: sra $6, $[[REG_S1_1]], 16
257 ; 32R2-DAG: seh $6, $[[REG_S1]]
258 ; FIXME andi is superfulous
259 ; ALL-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
260 ; ALL-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
261 ; ALL-DAG: andi $7, $[[REG_US1]], 65535
263 %1 = load i8, i8* @c1, align 1
264 %conv = sext i8 %1 to i32
265 %2 = load i8, i8* @uc1, align 1
266 %conv1 = zext i8 %2 to i32
267 %3 = load i16, i16* @s1, align 2
268 %conv2 = sext i16 %3 to i32
269 %4 = load i16, i16* @us1, align 2
270 %conv3 = zext i16 %4 to i32
271 call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)
275 declare void @xf(float)
280 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
281 ; ALL: lui $[[REG_FPCONST_1:[0-9]+]], 17886
282 ; ALL: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
283 ; ALL: mtc1 $[[REG_FPCONST]], $f12
284 ; ALL: lw $25, %got(xf)($[[REG_GP]])
286 call void @xf(float 0x40BBC85560000000)
290 declare void @xff(float, float)
292 define void @cxff() {
295 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
296 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314
297 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
298 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
299 ; ALL-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593
300 ; ALL-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
301 ; ALL-DAG: mtc1 $[[REG_FPCONST_3]], $f14
302 ; ALL-DAG: lw $25, %got(xff)($[[REG_GP]])
304 call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)
308 declare void @xfi(float, i32)
310 define void @cxfi() {
313 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
314 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540
315 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
316 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
317 ; ALL-DAG: addiu $5, $zero, 102
318 ; ALL-DAG: lw $25, %got(xfi)($[[REG_GP]])
320 call void @xfi(float 0x4013906240000000, i32 102)
324 declare void @xfii(float, i32, i32)
326 define void @cxfii() {
329 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
330 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142
331 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
332 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
333 ; ALL-DAG: addiu $5, $zero, 9993
334 ; ALL-DAG: addiu $6, $zero, 10922
335 ; ALL-DAG: lw $25, %got(xfii)($[[REG_GP]])
337 call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)
341 declare void @xfiii(float, i32, i32, i32)
343 define void @cxfiii() {
346 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
347 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120
348 ; ALL-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
349 ; ALL-DAG: mtc1 $[[REG_FPCONST]], $f12
350 ; ALL-DAG: addiu $5, $zero, 3948
351 ; ALL-DAG: lui $[[REG_I_1:[0-9]+]], 1
352 ; ALL-DAG: ori $6, $[[REG_I_1]], 23475
353 ; ALL-DAG: lui $[[REG_I_2:[0-9]+]], 1
354 ; ALL-DAG: ori $7, $[[REG_I_2]], 45686
355 ; ALL-DAG: lw $25, %got(xfiii)($[[REG_GP]])
357 call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)
361 declare void @xd(double)
366 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
367 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
368 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
369 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
370 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
371 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
372 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
373 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
374 ; ALL-DAG: lw $25, %got(xd)($[[REG_GP]])
376 call void @xd(double 5.994560e+02)
380 declare void @xdd(double, double)
382 define void @cxdd() {
385 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
386 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
387 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
388 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
389 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
390 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f12
391 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f13
392 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
393 ; ALL-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
394 ; ALL-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
395 ; ALL-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
396 ; ALL-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
397 ; ALL-DAG: mtc1 $[[REG_FPCONST_4]], $f14
398 ; 32R1-DAG: mtc1 $[[REG_FPCONST_2]], $f15
399 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f14
400 ; ALL-DAG: lw $25, %got(xdd)($[[REG_GP]])
402 call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)
406 declare void @xif(i32, float)
408 define void @cxif() {
411 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
412 ; ALL-DAG: addiu $4, $zero, 345
413 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17374
414 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
415 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
416 ; ALL-DAG: mfc1 $5, $f[[REGF_3]]
417 ; ALL-DAG: lw $25, %got(xif)($[[REG_GP]])
419 call void @xif(i32 345, float 0x407BCE5A20000000)
423 declare void @xiff(i32, float, float)
425 define void @cxiff() {
428 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
429 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17526
430 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706
431 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
432 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 16543
433 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326
434 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
435 ; ALL-DAG: addiu $4, $zero, 12239
436 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]]
437 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]]
438 ; ALL-DAG: lw $25, %got(xiff)($[[REG_GP]])
440 call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
444 declare void @xifi(i32, float, i32)
446 define void @cxifi() {
449 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
450 ; ALL-DAG: addiu $4, $zero, 887
451 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 16659
452 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
453 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
454 ; ALL-DAG: mfc1 $5, $f[[REGF_3]]
455 ; ALL-DAG: addiu $6, $zero, 888
456 ; ALL-DAG: lw $25, %got(xifi)($[[REG_GP]])
458 call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)
462 declare void @xifif(i32, float, i32, float)
464 define void @cxifif() {
467 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
468 ; ALL-DAG: lui $[[REGI:[0-9]+]], 1
469 ; ALL-DAG: ori $4, $[[REGI]], 2238
470 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 17527
471 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015
472 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
473 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17802
474 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470
475 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
476 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]]
477 ; ALL-DAG: addiu $6, $zero, 9991
478 ; ALL-DAG: mfc1 $7, $f[[REGF1_3]]
479 ; ALL-DAG: lw $25, %got(xifif)($[[REG_GP]])
481 call void @xifif(i32 67774, float 0x408EE0FBE0000000,
482 i32 9991, float 0x40B15C8CC0000000)
486 declare void @xiffi(i32, float, float, i32)
488 define void @cxiffi() {
491 ; ALL: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
492 ; ALL-DAG: lui $[[REGF0_1:[0-9]+]], 16307
493 ; ALL-DAG: ori $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107
494 ; ALL-DAG: mtc1 $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
495 ; ALL-DAG: lui $[[REGF1_1:[0-9]+]], 17529
496 ; ALL-DAG: ori $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322
497 ; ALL: mtc1 $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
498 ; ALL-DAG: addiu $4, $zero, 45
499 ; ALL-DAG: mfc1 $5, $f[[REGF0_3]]
500 ; ALL-DAG: mfc1 $6, $f[[REGF1_3]]
501 ; ALL-DAG: addiu $7, $zero, 234
502 ; ALL-DAG: lw $25, %got(xiffi)($[[REG_GP]])
504 call void @xiffi(i32 45, float 0x3FF6666660000000,
505 float 0x408F333340000000, i32 234)
509 declare void @xifii(i32, float, i32, i32)
511 define void @cxifii() {
514 ; ALL-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
515 ; ALL-DAG: addiu $4, $zero, 12239
516 ; ALL-DAG: lui $[[REGF_1:[0-9]+]], 17526
517 ; ALL-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
518 ; ALL-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
519 ; ALL-DAG: mfc1 $5, $f[[REGF_3]]
520 ; ALL-DAG: lui $[[REGI2:[0-9]+]], 15
521 ; ALL-DAG: ori $6, $[[REGI2]], 15837
522 ; ALL-DAG: addiu $7, $zero, 1234
523 ; ALL-DAG: lw $25, %got(xifii)($[[REG_GP]])
525 call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)