| blob | cd58947b186db8c067326b615f0d56cd3523a241 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=AVX --check-prefix=AVX512VL
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefix=AVX --check-prefix=AVX512DQVL
8 define <2 x i64> @combine_shuffle_sext_pmuldq(<4 x i32> %a0, <4 x i32> %a1) {
9 ; SSE-LABEL: combine_shuffle_sext_pmuldq:
10 ; SSE: # %bb.0:
11 ; SSE-NEXT: pmuldq %xmm1, %xmm0
12 ; SSE-NEXT: retq
13 ;
14 ; AVX-LABEL: combine_shuffle_sext_pmuldq:
15 ; AVX: # %bb.0:
16 ; AVX-NEXT: vpmuldq %xmm1, %xmm0, %xmm0
17 ; AVX-NEXT: retq
18 %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
19 %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
20 %3 = sext <2 x i32> %1 to <2 x i64>
21 %4 = sext <2 x i32> %2 to <2 x i64>
22 %5 = mul nuw <2 x i64> %3, %4
23 ret <2 x i64> %5
24 }
26 define <2 x i64> @combine_shuffle_zext_pmuludq(<4 x i32> %a0, <4 x i32> %a1) {
27 ; SSE-LABEL: combine_shuffle_zext_pmuludq:
28 ; SSE: # %bb.0:
29 ; SSE-NEXT: pmuludq %xmm1, %xmm0
30 ; SSE-NEXT: retq
31 ;
32 ; AVX-LABEL: combine_shuffle_zext_pmuludq:
33 ; AVX: # %bb.0:
34 ; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
35 ; AVX-NEXT: retq
36 %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
37 %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
38 %3 = zext <2 x i32> %1 to <2 x i64>
39 %4 = zext <2 x i32> %2 to <2 x i64>
40 %5 = mul nuw <2 x i64> %3, %4
41 ret <2 x i64> %5
42 }
44 define <2 x i64> @combine_shuffle_zero_pmuludq(<4 x i32> %a0, <4 x i32> %a1) {
45 ; SSE-LABEL: combine_shuffle_zero_pmuludq:
46 ; SSE: # %bb.0:
47 ; SSE-NEXT: pmuludq %xmm1, %xmm0
48 ; SSE-NEXT: retq
49 ;
50 ; AVX-LABEL: combine_shuffle_zero_pmuludq:
51 ; AVX: # %bb.0:
52 ; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
53 ; AVX-NEXT: retq
54 %1 = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
55 %2 = shufflevector <4 x i32> %a1, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
56 %3 = bitcast <4 x i32> %1 to <2 x i64>
57 %4 = bitcast <4 x i32> %2 to <2 x i64>
58 %5 = mul <2 x i64> %3, %4
59 ret <2 x i64> %5
60 }
62 define <4 x i64> @combine_shuffle_zero_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) {
63 ; SSE-LABEL: combine_shuffle_zero_pmuludq_256:
64 ; SSE: # %bb.0:
65 ; SSE-NEXT: pmuludq %xmm2, %xmm0
66 ; SSE-NEXT: pmuludq %xmm3, %xmm1
67 ; SSE-NEXT: retq
68 ;
69 ; AVX2-LABEL: combine_shuffle_zero_pmuludq_256:
70 ; AVX2: # %bb.0:
71 ; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
72 ; AVX2-NEXT: retq
73 ;
74 ; AVX512VL-LABEL: combine_shuffle_zero_pmuludq_256:
75 ; AVX512VL: # %bb.0:
76 ; AVX512VL-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
77 ; AVX512VL-NEXT: retq
78 ;
79 ; AVX512DQVL-LABEL: combine_shuffle_zero_pmuludq_256:
80 ; AVX512DQVL: # %bb.0:
81 ; AVX512DQVL-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
82 ; AVX512DQVL-NEXT: retq
83 %1 = shufflevector <8 x i32> %a0, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
84 %2 = shufflevector <8 x i32> %a1, <8 x i32> zeroinitializer, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
85 %3 = bitcast <8 x i32> %1 to <4 x i64>
86 %4 = bitcast <8 x i32> %2 to <4 x i64>
87 %5 = mul <4 x i64> %3, %4
88 ret <4 x i64> %5
89 }
91 define <8 x i64> @combine_zext_pmuludq_256(<8 x i32> %a) {
92 ; SSE-LABEL: combine_zext_pmuludq_256:
93 ; SSE: # %bb.0:
94 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
95 ; SSE-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero
96 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
97 ; SSE-NEXT: pmovzxdq {{.*#+}} xmm4 = xmm2[0],zero,xmm2[1],zero
98 ; SSE-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero
99 ; SSE-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
100 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [715827883,715827883]
101 ; SSE-NEXT: pmuludq %xmm1, %xmm0
102 ; SSE-NEXT: pmuludq %xmm1, %xmm2
103 ; SSE-NEXT: pmuludq %xmm1, %xmm4
104 ; SSE-NEXT: pmuludq %xmm1, %xmm3
105 ; SSE-NEXT: movdqa %xmm4, %xmm1
106 ; SSE-NEXT: retq
107 ;
108 ; AVX2-LABEL: combine_zext_pmuludq_256:
109 ; AVX2: # %bb.0:
110 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
111 ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
112 ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
113 ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [715827883,715827883,715827883,715827883]
114 ; AVX2-NEXT: vpmuludq %ymm2, %ymm0, %ymm0
115 ; AVX2-NEXT: vpmuludq %ymm2, %ymm1, %ymm1
116 ; AVX2-NEXT: retq
117 ;
118 ; AVX512VL-LABEL: combine_zext_pmuludq_256:
119 ; AVX512VL: # %bb.0:
120 ; AVX512VL-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero
121 ; AVX512VL-NEXT: vpmuludq {{.*}}(%rip){1to8}, %zmm0, %zmm0
122 ; AVX512VL-NEXT: retq
123 ;
124 ; AVX512DQVL-LABEL: combine_zext_pmuludq_256:
125 ; AVX512DQVL: # %bb.0:
126 ; AVX512DQVL-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero
127 ; AVX512DQVL-NEXT: vpmuludq {{.*}}(%rip){1to8}, %zmm0, %zmm0
128 ; AVX512DQVL-NEXT: retq
129 %1 = zext <8 x i32> %a to <8 x i64>
130 %2 = mul nuw nsw <8 x i64> %1, <i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883, i64 715827883>
131 ret <8 x i64> %2
132 }
134 define void @PR39398() {
135 ; SSE-LABEL: PR39398:
136 ; SSE: # %bb.0: # %bb
137 ; SSE-NEXT: .p2align 4, 0x90
138 ; SSE-NEXT: .LBB5_1: # %bb10
139 ; SSE-NEXT: # =>This Inner Loop Header: Depth=1
140 ; SSE-NEXT: cmpl $232, %eax
141 ; SSE-NEXT: jne .LBB5_1
142 ; SSE-NEXT: # %bb.2: # %bb34
143 ; SSE-NEXT: retq
144 ;
145 ; AVX-LABEL: PR39398:
146 ; AVX: # %bb.0: # %bb
147 ; AVX-NEXT: .p2align 4, 0x90
148 ; AVX-NEXT: .LBB5_1: # %bb10
149 ; AVX-NEXT: # =>This Inner Loop Header: Depth=1
150 ; AVX-NEXT: cmpl $232, %eax
151 ; AVX-NEXT: jne .LBB5_1
152 ; AVX-NEXT: # %bb.2: # %bb34
153 ; AVX-NEXT: retq
154 bb:
155 %tmp9 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> zeroinitializer
156 br label %bb10
158 bb10: ; preds = %bb10, %bb
159 %tmp12 = phi <4 x i32> [ <i32 9, i32 8, i32 7, i32 6>, %bb ], [ zeroinitializer, %bb10 ]
160 %tmp16 = add <4 x i32> %tmp12, <i32 -4, i32 -4, i32 -4, i32 -4>
161 %tmp18 = zext <4 x i32> %tmp12 to <4 x i64>
162 %tmp19 = zext <4 x i32> %tmp16 to <4 x i64>
163 %tmp20 = xor <4 x i64> %tmp18, <i64 -1, i64 -1, i64 -1, i64 -1>
164 %tmp21 = xor <4 x i64> %tmp19, <i64 -1, i64 -1, i64 -1, i64 -1>
165 %tmp24 = mul <4 x i64> %tmp9, %tmp20
166 %tmp25 = mul <4 x i64> %tmp9, %tmp21
167 %tmp26 = select <4 x i1> undef, <4 x i64> zeroinitializer, <4 x i64> %tmp24
168 %tmp27 = select <4 x i1> undef, <4 x i64> zeroinitializer, <4 x i64> %tmp25
169 %tmp28 = add <4 x i64> zeroinitializer, %tmp26
170 %tmp29 = add <4 x i64> zeroinitializer, %tmp27
171 %tmp33 = icmp eq i32 undef, 232
172 br i1 %tmp33, label %bb34, label %bb10
174 bb34: ; preds = %bb10
175 %tmp35 = add <4 x i64> %tmp29, %tmp28
176 ret void
177 }