1 ; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+lwp < %s | FileCheck %s
3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
4 target triple = "x86_64-unknown-unknown"
6 ; Stack reload folding tests.
8 ; By including a nop call with sideeffects we can force a partial register spill of the
9 ; relevant registers and check that the reload is correctly folded into the instruction.
11 define i8 @stack_fold_lwpins_u32(i32 %a0, i32 %a1) {
12 ; CHECK-LABEL: stack_fold_lwpins_u32
14 ; CHECK: lwpins $2814, {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
15 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
16 %2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 2814)
19 declare i8 @llvm.x86.lwpins32(i32, i32, i32)
21 define i8 @stack_fold_lwpins_u64(i64 %a0, i32 %a1) {
22 ; CHECK-LABEL: stack_fold_lwpins_u64
24 ; CHECK: lwpins $2814, {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 4-byte Folded Reload
25 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
26 %2 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 2814)
29 declare i8 @llvm.x86.lwpins64(i64, i32, i32)
31 define void @stack_fold_lwpval_u32(i32 %a0, i32 %a1) {
32 ; CHECK-LABEL: stack_fold_lwpval_u32
34 ; CHECK: lwpval $2814, {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
35 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
36 tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 2814)
39 declare void @llvm.x86.lwpval32(i32, i32, i32)
41 define void @stack_fold_lwpval_u64(i64 %a0, i32 %a1) {
42 ; CHECK-LABEL: stack_fold_lwpval_u64
44 ; CHECK: lwpval $2814, {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 4-byte Folded Reload
45 %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
46 tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 2814)
49 declare void @llvm.x86.lwpval64(i64, i32, i32)