test/MC/AArch64/SVE/fadda-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3 fadda b0, p7, b0, z31.b
   4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   5 // CHECK-NEXT: fadda b0, p7, b0, z31.b
   6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
   7
   8 fadda h0, p7, h1, z31.h
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
  10 // CHECK-NEXT: fadda h0, p7, h1, z31.h
  11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  12
  13 fadda h0, p8, h0, z31.h
  14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
  15 // CHECK-NEXT: fadda h0, p8, h0, z31.h
  16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  17
  18 fadda v0.8h, p7, v0.8h, z31.h
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  20 // CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
  21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  22
  23 // --------------------------------------------------------------------------//
  24 // Negative tests for instructions that are incompatible with movprfx
  25
  26 movprfx z31.d, p7/z, z6.d
  27 fadda d0, p7, d0, z31.d
  28 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  29 // CHECK-NEXT: fadda d0, p7, d0, z31.d
  30 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  31
  32 movprfx z31, z6
  33 fadda d0, p7, d0, z31.d
  34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
  35 // CHECK-NEXT: fadda d0, p7, d0, z31.d
  36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: