test/MC/Disassembler/AMDGPU/sopk_vi.txt

   1 # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
   2
   3 # VI:   s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb0]
   4 0x06 0x00 0x82 0xb0
   5
   6 # VI:   s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
   7 0x06 0x00 0x02 0xb1
   8
   9 # VI:   s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
  10 0x06 0x00 0x82 0xb1
  11
  12 # VI:   s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]
  13 0x06 0x00 0x02 0xb2
  14
  15 # VI:   s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]
  16 0x06 0x00 0x82 0xb2
  17
  18 # VI:   s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]
  19 0x06 0x00 0x02 0xb3
  20
  21 # VI:   s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]
  22 0x06 0x00 0x82 0xb3
  23
  24 # VI:   s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]
  25 0x06 0x00 0x02 0xb4
  26
  27 # VI:   s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]
  28 0x06 0x00 0x82 0xb4
  29
  30 # VI:   s_cmpk_gt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb5]
  31 0x06 0x00 0x02 0xb5
  32
  33 # VI:   s_cmpk_ge_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb5]
  34 0x06 0x00 0x82 0xb5
  35
  36 # VI:   s_cmpk_lt_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb6]
  37 0x06 0x00 0x02 0xb6
  38
  39 # VI:   s_cmpk_le_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb6]
  40 0x06 0x00 0x82 0xb6
  41
  42 # VI:   s_addk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb7]
  43 0x06 0x00 0x02 0xb7
  44
  45 # VI:   s_mulk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb7]
  46 0x06 0x00 0x82 0xb7
  47
  48 # VI:   s_cbranch_i_fork s[2:3], 0x6 ; encoding: [0x06,0x00,0x02,0xb8]
  49 0x06 0x00 0x02 0xb8
  50
  51 # VI:   s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8]
  52 0x06 0xf8 0x82 0xb8
  53
  54 # VI:   s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]
  55 0x33,0xf8,0x82,0xb8
  56
  57 # VI:   s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
  58 0x73,0xf0,0x82,0xb8
  59
  60 # VI:   s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
  61 0x06 0x00 0x02 0xb9
  62
  63 # VI:   s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0xff,0x00,0x00,0x00]
  64 0x45 0xf0 0x00 0xba 0xff 0x00 0x00 0x00