lib/Target/PowerPC/PPCTargetMachine.cpp

   1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Top-level implementation for the PowerPC target.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "PPCTargetMachine.h"
  14 #include "MCTargetDesc/PPCMCTargetDesc.h"
  15 #include "PPC.h"
  16 #include "PPCMachineScheduler.h"
  17 #include "PPCSubtarget.h"
  18 #include "PPCTargetObjectFile.h"
  19 #include "PPCTargetTransformInfo.h"
  20 #include "TargetInfo/PowerPCTargetInfo.h"
  21 #include "llvm/ADT/Optional.h"
  22 #include "llvm/ADT/STLExtras.h"
  23 #include "llvm/ADT/StringRef.h"
  24 #include "llvm/ADT/Triple.h"
  25 #include "llvm/Analysis/TargetTransformInfo.h"
  26 #include "llvm/CodeGen/Passes.h"
  27 #include "llvm/CodeGen/TargetPassConfig.h"
  28 #include "llvm/CodeGen/MachineScheduler.h"
  29 #include "llvm/IR/Attributes.h"
  30 #include "llvm/IR/DataLayout.h"
  31 #include "llvm/IR/Function.h"
  32 #include "llvm/Pass.h"
  33 #include "llvm/Support/CodeGen.h"
  34 #include "llvm/Support/CommandLine.h"
  35 #include "llvm/Support/TargetRegistry.h"
  36 #include "llvm/Target/TargetLoweringObjectFile.h"
  37 #include "llvm/Target/TargetOptions.h"
  38 #include "llvm/Transforms/Scalar.h"
  39 #include <cassert>
  40 #include <memory>
  41 #include <string>
  42
  43 using namespace llvm;
  44
  45
  46 static cl::opt<bool>
  47     EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
  48                            cl::desc("enable coalescing of duplicate branches for PPC"));
  49 static cl::
  50 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
  51                         cl::desc("Disable CTR loops for PPC"));
  52
  53 static cl::
  54 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
  55                             cl::desc("Disable PPC loop preinc prep"));
  56
  57 static cl::opt<bool>
  58 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
  59   cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
  60
  61 static cl::
  62 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
  63                                 cl::desc("Disable VSX Swap Removal for PPC"));
  64
  65 static cl::
  66 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
  67                               cl::desc("Disable QPX load splat simplification"));
  68
  69 static cl::
  70 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
  71                             cl::desc("Disable machine peepholes for PPC"));
  72
  73 static cl::opt<bool>
  74 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
  75              cl::desc("Enable optimizations on complex GEPs"),
  76              cl::init(true));
  77
  78 static cl::opt<bool>
  79 EnablePrefetch("enable-ppc-prefetching",
  80                   cl::desc("disable software prefetching on PPC"),
  81                   cl::init(false), cl::Hidden);
  82
  83 static cl::opt<bool>
  84 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
  85                       cl::desc("Add extra TOC register dependencies"),
  86                       cl::init(true), cl::Hidden);
  87
  88 static cl::opt<bool>
  89 EnableMachineCombinerPass("ppc-machine-combiner",
  90                           cl::desc("Enable the machine combiner pass"),
  91                           cl::init(true), cl::Hidden);
  92
  93 static cl::opt<bool>
  94   ReduceCRLogical("ppc-reduce-cr-logicals",
  95                   cl::desc("Expand eligible cr-logical binary ops to branches"),
  96                   cl::init(false), cl::Hidden);
  97 extern "C" void LLVMInitializePowerPCTarget() {
  98   // Register the targets
  99   RegisterTargetMachine<PPCTargetMachine> A(getThePPC32Target());
 100   RegisterTargetMachine<PPCTargetMachine> B(getThePPC64Target());
 101   RegisterTargetMachine<PPCTargetMachine> C(getThePPC64LETarget());
 102
 103   PassRegistry &PR = *PassRegistry::getPassRegistry();
 104 #ifndef NDEBUG
 105   initializePPCCTRLoopsVerifyPass(PR);
 106 #endif
 107   initializePPCLoopPreIncPrepPass(PR);
 108   initializePPCTOCRegDepsPass(PR);
 109   initializePPCEarlyReturnPass(PR);
 110   initializePPCVSXCopyPass(PR);
 111   initializePPCVSXFMAMutatePass(PR);
 112   initializePPCVSXSwapRemovalPass(PR);
 113   initializePPCReduceCRLogicalsPass(PR);
 114   initializePPCBSelPass(PR);
 115   initializePPCBranchCoalescingPass(PR);
 116   initializePPCQPXLoadSplatPass(PR);
 117   initializePPCBoolRetToIntPass(PR);
 118   initializePPCExpandISELPass(PR);
 119   initializePPCPreEmitPeepholePass(PR);
 120   initializePPCTLSDynamicCallPass(PR);
 121   initializePPCMIPeepholePass(PR);
 122 }
 123
 124 /// Return the datalayout string of a subtarget.
 125 static std::string getDataLayoutString(const Triple &T) {
 126   bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
 127   std::string Ret;
 128
 129   // Most PPC* platforms are big endian, PPC64LE is little endian.
 130   if (T.getArch() == Triple::ppc64le)
 131     Ret = "e";
 132   else
 133     Ret = "E";
 134
 135   Ret += DataLayout::getManglingComponent(T);
 136
 137   // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
 138   // pointers.
 139   if (!is64Bit || T.getOS() == Triple::Lv2)
 140     Ret += "-p:32:32";
 141
 142   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
 143   // documentation are wrong; these are correct (i.e. "what gcc does").
 144   if (is64Bit || !T.isOSDarwin())
 145     Ret += "-i64:64";
 146   else
 147     Ret += "-f64:32:64";
 148
 149   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
 150   if (is64Bit)
 151     Ret += "-n32:64";
 152   else
 153     Ret += "-n32";
 154
 155   return Ret;
 156 }
 157
 158 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL,
 159                                       const Triple &TT) {
 160   std::string FullFS = FS;
 161
 162   // Make sure 64-bit features are available when CPUname is generic
 163   if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
 164     if (!FullFS.empty())
 165       FullFS = "+64bit," + FullFS;
 166     else
 167       FullFS = "+64bit";
 168   }
 169
 170   if (OL >= CodeGenOpt::Default) {
 171     if (!FullFS.empty())
 172       FullFS = "+crbits," + FullFS;
 173     else
 174       FullFS = "+crbits";
 175   }
 176
 177   if (OL != CodeGenOpt::None) {
 178     if (!FullFS.empty())
 179       FullFS = "+invariant-function-descriptors," + FullFS;
 180     else
 181       FullFS = "+invariant-function-descriptors";
 182   }
 183
 184   return FullFS;
 185 }
 186
 187 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
 188   if (TT.isOSDarwin())
 189     return llvm::make_unique<TargetLoweringObjectFileMachO>();
 190
 191   if (TT.isOSAIX())
 192     return llvm::make_unique<TargetLoweringObjectFileXCOFF>();
 193
 194   return llvm::make_unique<PPC64LinuxTargetObjectFile>();
 195 }
 196
 197 static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
 198                                                  const TargetOptions &Options) {
 199   if (TT.isOSDarwin())
 200     report_fatal_error("Darwin is no longer supported for PowerPC");
 201
 202   if (Options.MCOptions.getABIName().startswith("elfv1"))
 203     return PPCTargetMachine::PPC_ABI_ELFv1;
 204   else if (Options.MCOptions.getABIName().startswith("elfv2"))
 205     return PPCTargetMachine::PPC_ABI_ELFv2;
 206
 207   assert(Options.MCOptions.getABIName().empty() &&
 208          "Unknown target-abi option!");
 209
 210   if (TT.isMacOSX())
 211     return PPCTargetMachine::PPC_ABI_UNKNOWN;
 212
 213   switch (TT.getArch()) {
 214   case Triple::ppc64le:
 215     return PPCTargetMachine::PPC_ABI_ELFv2;
 216   case Triple::ppc64:
 217     if (TT.getEnvironment() == llvm::Triple::ELFv2)
 218       return PPCTargetMachine::PPC_ABI_ELFv2;
 219     return PPCTargetMachine::PPC_ABI_ELFv1;
 220   default:
 221     return PPCTargetMachine::PPC_ABI_UNKNOWN;
 222   }
 223 }
 224
 225 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
 226                                            Optional<Reloc::Model> RM) {
 227   if (RM.hasValue())
 228     return *RM;
 229
 230   // Darwin defaults to dynamic-no-pic.
 231   if (TT.isOSDarwin())
 232     return Reloc::DynamicNoPIC;
 233
 234   // Big Endian PPC is PIC by default.
 235   if (TT.getArch() == Triple::ppc64)
 236     return Reloc::PIC_;
 237
 238   // Rest are static by default.
 239   return Reloc::Static;
 240 }
 241
 242 static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
 243                                                  Optional<CodeModel::Model> CM,
 244                                                  bool JIT) {
 245   if (CM) {
 246     if (*CM == CodeModel::Tiny)
 247       report_fatal_error("Target does not support the tiny CodeModel", false);
 248     if (*CM == CodeModel::Kernel)
 249       report_fatal_error("Target does not support the kernel CodeModel", false);
 250     return *CM;
 251   }
 252   if (!TT.isOSDarwin() && !JIT &&
 253       (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
 254     return CodeModel::Medium;
 255   return CodeModel::Small;
 256 }
 257
 258
 259 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
 260   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
 261   ScheduleDAGMILive *DAG =
 262     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
 263                           llvm::make_unique<PPCPreRASchedStrategy>(C) :
 264                           llvm::make_unique<GenericScheduler>(C));
 265   // add DAG Mutations here.
 266   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
 267   return DAG;
 268 }
 269
 270 static ScheduleDAGInstrs *createPPCPostMachineScheduler(
 271   MachineSchedContext *C) {
 272   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
 273   ScheduleDAGMI *DAG =
 274     new ScheduleDAGMI(C, ST.usePPCPostRASchedStrategy() ?
 275                       llvm::make_unique<PPCPostRASchedStrategy>(C) :
 276                       llvm::make_unique<PostGenericScheduler>(C), true);
 277   // add DAG Mutations here.
 278   return DAG;
 279 }
 280
 281 // The FeatureString here is a little subtle. We are modifying the feature
 282 // string with what are (currently) non-function specific overrides as it goes
 283 // into the LLVMTargetMachine constructor and then using the stored value in the
 284 // Subtarget constructor below it.
 285 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
 286                                    StringRef CPU, StringRef FS,
 287                                    const TargetOptions &Options,
 288                                    Optional<Reloc::Model> RM,
 289                                    Optional<CodeModel::Model> CM,
 290                                    CodeGenOpt::Level OL, bool JIT)
 291     : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
 292                         computeFSAdditions(FS, OL, TT), Options,
 293                         getEffectiveRelocModel(TT, RM),
 294                         getEffectivePPCCodeModel(TT, CM, JIT), OL),
 295       TLOF(createTLOF(getTargetTriple())),
 296       TargetABI(computeTargetABI(TT, Options)) {
 297   initAsmInfo();
 298 }
 299
 300 PPCTargetMachine::~PPCTargetMachine() = default;
 301
 302 const PPCSubtarget *
 303 PPCTargetMachine::getSubtargetImpl(const Function &F) const {
 304   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 305   Attribute FSAttr = F.getFnAttribute("target-features");
 306
 307   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
 308                         ? CPUAttr.getValueAsString().str()
 309                         : TargetCPU;
 310   std::string FS = !FSAttr.hasAttribute(Attribute::None)
 311                        ? FSAttr.getValueAsString().str()
 312                        : TargetFS;
 313
 314   // FIXME: This is related to the code below to reset the target options,
 315   // we need to know whether or not the soft float flag is set on the
 316   // function before we can generate a subtarget. We also need to use
 317   // it as a key for the subtarget since that can be the only difference
 318   // between two functions.
 319   bool SoftFloat =
 320       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
 321   // If the soft float attribute is set on the function turn on the soft float
 322   // subtarget feature.
 323   if (SoftFloat)
 324     FS += FS.empty() ? "-hard-float" : ",-hard-float";
 325
 326   auto &I = SubtargetMap[CPU + FS];
 327   if (!I) {
 328     // This needs to be done before we create a new subtarget since any
 329     // creation will depend on the TM and the code generation flags on the
 330     // function that reside in TargetOptions.
 331     resetTargetOptions(F);
 332     I = llvm::make_unique<PPCSubtarget>(
 333         TargetTriple, CPU,
 334         // FIXME: It would be good to have the subtarget additions here
 335         // not necessary. Anything that turns them on/off (overrides) ends
 336         // up being put at the end of the feature string, but the defaults
 337         // shouldn't require adding them. Fixing this means pulling Feature64Bit
 338         // out of most of the target cpus in the .td file and making it set only
 339         // as part of initialization via the TargetTriple.
 340         computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
 341   }
 342   return I.get();
 343 }
 344
 345 //===----------------------------------------------------------------------===//
 346 // Pass Pipeline Configuration
 347 //===----------------------------------------------------------------------===//
 348
 349 namespace {
 350
 351 /// PPC Code Generator Pass Configuration Options.
 352 class PPCPassConfig : public TargetPassConfig {
 353 public:
 354   PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
 355     : TargetPassConfig(TM, PM) {
 356     // At any optimization level above -O0 we use the Machine Scheduler and not
 357     // the default Post RA List Scheduler.
 358     if (TM.getOptLevel() != CodeGenOpt::None)
 359       substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
 360   }
 361
 362   PPCTargetMachine &getPPCTargetMachine() const {
 363     return getTM<PPCTargetMachine>();
 364   }
 365
 366   void addIRPasses() override;
 367   bool addPreISel() override;
 368   bool addILPOpts() override;
 369   bool addInstSelector() override;
 370   void addMachineSSAOptimization() override;
 371   void addPreRegAlloc() override;
 372   void addPreSched2() override;
 373   void addPreEmitPass() override;
 374   ScheduleDAGInstrs *
 375   createMachineScheduler(MachineSchedContext *C) const override {
 376     return createPPCMachineScheduler(C);
 377   }
 378   ScheduleDAGInstrs *
 379   createPostMachineScheduler(MachineSchedContext *C) const override {
 380     return createPPCPostMachineScheduler(C);
 381   }
 382 };
 383
 384 } // end anonymous namespace
 385
 386 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
 387   return new PPCPassConfig(*this, PM);
 388 }
 389
 390 void PPCPassConfig::addIRPasses() {
 391   if (TM->getOptLevel() != CodeGenOpt::None)
 392     addPass(createPPCBoolRetToIntPass());
 393   addPass(createAtomicExpandPass());
 394
 395   // For the BG/Q (or if explicitly requested), add explicit data prefetch
 396   // intrinsics.
 397   bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
 398                         getOptLevel() != CodeGenOpt::None;
 399   if (EnablePrefetch.getNumOccurrences() > 0)
 400     UsePrefetching = EnablePrefetch;
 401   if (UsePrefetching)
 402     addPass(createLoopDataPrefetchPass());
 403
 404   if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
 405     // Call SeparateConstOffsetFromGEP pass to extract constants within indices
 406     // and lower a GEP with multiple indices to either arithmetic operations or
 407     // multiple GEPs with single index.
 408     addPass(createSeparateConstOffsetFromGEPPass(true));
 409     // Call EarlyCSE pass to find and remove subexpressions in the lowered
 410     // result.
 411     addPass(createEarlyCSEPass());
 412     // Do loop invariant code motion in case part of the lowered result is
 413     // invariant.
 414     addPass(createLICMPass());
 415   }
 416
 417   TargetPassConfig::addIRPasses();
 418 }
 419
 420 bool PPCPassConfig::addPreISel() {
 421   if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
 422     addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
 423
 424   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
 425     addPass(createHardwareLoopsPass());
 426
 427   return false;
 428 }
 429
 430 bool PPCPassConfig::addILPOpts() {
 431   addPass(&EarlyIfConverterID);
 432
 433   if (EnableMachineCombinerPass)
 434     addPass(&MachineCombinerID);
 435
 436   return true;
 437 }
 438
 439 bool PPCPassConfig::addInstSelector() {
 440   // Install an instruction selector.
 441   addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));
 442
 443 #ifndef NDEBUG
 444   if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
 445     addPass(createPPCCTRLoopsVerify());
 446 #endif
 447
 448   addPass(createPPCVSXCopyPass());
 449   return false;
 450 }
 451
 452 void PPCPassConfig::addMachineSSAOptimization() {
 453   // PPCBranchCoalescingPass need to be done before machine sinking
 454   // since it merges empty blocks.
 455   if (EnableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
 456     addPass(createPPCBranchCoalescingPass());
 457   TargetPassConfig::addMachineSSAOptimization();
 458   // For little endian, remove where possible the vector swap instructions
 459   // introduced at code generation to normalize vector element order.
 460   if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
 461       !DisableVSXSwapRemoval)
 462     addPass(createPPCVSXSwapRemovalPass());
 463   // Reduce the number of cr-logical ops.
 464   if (ReduceCRLogical && getOptLevel() != CodeGenOpt::None)
 465     addPass(createPPCReduceCRLogicalsPass());
 466   // Target-specific peephole cleanups performed after instruction
 467   // selection.
 468   if (!DisableMIPeephole) {
 469     addPass(createPPCMIPeepholePass());
 470     addPass(&DeadMachineInstructionElimID);
 471   }
 472 }
 473
 474 void PPCPassConfig::addPreRegAlloc() {
 475   if (getOptLevel() != CodeGenOpt::None) {
 476     initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
 477     insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
 478                &PPCVSXFMAMutateID);
 479   }
 480
 481   // FIXME: We probably don't need to run these for -fPIE.
 482   if (getPPCTargetMachine().isPositionIndependent()) {
 483     // FIXME: LiveVariables should not be necessary here!
 484     // PPCTLSDynamicCallPass uses LiveIntervals which previously dependent on
 485     // LiveVariables. This (unnecessary) dependency has been removed now,
 486     // however a stage-2 clang build fails without LiveVariables computed here.
 487     addPass(&LiveVariablesID, false);
 488     addPass(createPPCTLSDynamicCallPass());
 489   }
 490   if (EnableExtraTOCRegDeps)
 491     addPass(createPPCTOCRegDepsPass());
 492
 493   if (getOptLevel() != CodeGenOpt::None)
 494     addPass(&MachinePipelinerID);
 495 }
 496
 497 void PPCPassConfig::addPreSched2() {
 498   if (getOptLevel() != CodeGenOpt::None) {
 499     addPass(&IfConverterID);
 500
 501     // This optimization must happen after anything that might do store-to-load
 502     // forwarding. Here we're after RA (and, thus, when spills are inserted)
 503     // but before post-RA scheduling.
 504     if (!DisableQPXLoadSplat)
 505       addPass(createPPCQPXLoadSplatPass());
 506   }
 507 }
 508
 509 void PPCPassConfig::addPreEmitPass() {
 510   addPass(createPPCPreEmitPeepholePass());
 511   addPass(createPPCExpandISELPass());
 512
 513   if (getOptLevel() != CodeGenOpt::None)
 514     addPass(createPPCEarlyReturnPass(), false);
 515   // Must run branch selection immediately preceding the asm printer.
 516   addPass(createPPCBranchSelectionPass(), false);
 517 }
 518
 519 TargetTransformInfo
 520 PPCTargetMachine::getTargetTransformInfo(const Function &F) {
 521   return TargetTransformInfo(PPCTTIImpl(this, F));
 522 }
 523
 524 static MachineSchedRegistry
 525 PPCPreRASchedRegistry("ppc-prera",
 526                       "Run PowerPC PreRA specific scheduler",
 527                       createPPCMachineScheduler);
 528
 529 static MachineSchedRegistry
 530 PPCPostRASchedRegistry("ppc-postra",
 531                        "Run PowerPC PostRA specific scheduler",
 532                        createPPCPostMachineScheduler);