1 # RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
4 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
5 target triple = "thumbv8.1m.main-arm-none-eabi"
7 define hidden arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32_v2(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9 %conv.i = zext i16 %p to i32
10 %0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
11 %1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
12 %2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
13 %3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive2, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
17 declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
18 declare void @llvm.stackprotector(i8*, i8**) #2
20 attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-frame-pointer-elim"="false" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
21 attributes #1 = { nounwind readnone }
22 attributes #2 = { nounwind }
26 name: test_vminnmq_m_f32_v2
28 exposesReturnsTwice: false
30 regBankSelected: false
33 tracksRegLiveness: true
37 - { reg: '$q0', virtual-reg: '' }
38 - { reg: '$q1', virtual-reg: '' }
39 - { reg: '$q2', virtual-reg: '' }
40 - { reg: '$q3', virtual-reg: '' }
41 - { reg: '$r0', virtual-reg: '' }
43 isFrameAddressTaken: false
44 isReturnAddressTaken: false
54 cvBytesOfCalleeSavedRegisters: 0
55 hasOpaqueSPAdjustment: false
57 hasMustTailInVarArgFunc: false
66 liveins: $q0, $q1, $q2, $q3, $r0
68 ; CHECK: MVE_VPST 1, implicit-def $p0
69 ; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VMINNMf32
70 ; CHECK-NEXT: renamable $q2 = nnan ninf nsz MVE_VMINNMf32
71 ; CHECK-NEXT: renamable $q0 = nnan ninf nsz MVE_VMINNMf32
72 ; CHECK-NEXT: renamable $q1 = nnan ninf nsz MVE_VMINNMf32
74 $vpr = VMSR_P0 killed $r0, 14, $noreg
75 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2
76 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2
77 renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0
78 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1
79 $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0
80 tBX_RET 14, $noreg, implicit $q0