[AArch64] Default to SEH exception handling on MinGW
[llvm-complete.git] / lib / MC / MCInstrDesc.cpp
blobd54aeba89edc5f85d7ec25319c00e855c84bd5cc
1 //===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
10 // are used to describe target instructions and their operands.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/MC/MCInstrDesc.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
19 using namespace llvm;
21 bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
22 std::string &Info) const {
23 if (ComplexDeprecationInfo)
24 return ComplexDeprecationInfo(MI, STI, Info);
25 if (DeprecatedFeature != -1 && STI.getFeatureBits()[DeprecatedFeature]) {
26 // FIXME: it would be nice to include the subtarget feature here.
27 Info = "deprecated";
28 return true;
30 return false;
32 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
33 const MCRegisterInfo &RI) const {
34 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
35 return true;
36 unsigned PC = RI.getProgramCounter();
37 if (PC == 0)
38 return false;
39 if (hasDefOfPhysReg(MI, PC, RI))
40 return true;
41 return false;
44 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
45 const MCRegisterInfo *MRI) const {
46 if (const MCPhysReg *ImpDefs = ImplicitDefs)
47 for (; *ImpDefs; ++ImpDefs)
48 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
49 return true;
50 return false;
53 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
54 const MCRegisterInfo &RI) const {
55 for (int i = 0, e = NumDefs; i != e; ++i)
56 if (MI.getOperand(i).isReg() &&
57 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
58 return true;
59 if (variadicOpsAreDefs())
60 for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
61 if (MI.getOperand(i).isReg() &&
62 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
63 return true;
64 return hasImplicitDefOfPhysReg(Reg, &RI);