1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
12 //===----------------------------------------------------------------------===//
14 #include "MipsAsmPrinter.h"
15 #include "MCTargetDesc/MipsABIInfo.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsInstPrinter.h"
18 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MCTargetDesc/MipsMCTargetDesc.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsMachineFunction.h"
23 #include "MipsSubtarget.h"
24 #include "MipsTargetMachine.h"
25 #include "MipsTargetStreamer.h"
26 #include "TargetInfo/MipsTargetInfo.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/ADT/Triple.h"
30 #include "llvm/ADT/Twine.h"
31 #include "llvm/BinaryFormat/ELF.h"
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineConstantPool.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstr.h"
37 #include "llvm/CodeGen/MachineJumpTableInfo.h"
38 #include "llvm/CodeGen/MachineOperand.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/BasicBlock.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCInst.h"
50 #include "llvm/MC/MCInstBuilder.h"
51 #include "llvm/MC/MCObjectFileInfo.h"
52 #include "llvm/MC/MCSectionELF.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/MC/MCSymbolELF.h"
55 #include "llvm/Support/Casting.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/TargetRegistry.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetLoweringObjectFile.h"
60 #include "llvm/Target/TargetMachine.h"
70 #define DEBUG_TYPE "mips-asm-printer"
72 extern cl::opt
<bool> EmitJalrReloc
;
74 MipsTargetStreamer
&MipsAsmPrinter::getTargetStreamer() const {
75 return static_cast<MipsTargetStreamer
&>(*OutStreamer
->getTargetStreamer());
78 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction
&MF
) {
79 Subtarget
= &MF
.getSubtarget
<MipsSubtarget
>();
81 MipsFI
= MF
.getInfo
<MipsFunctionInfo
>();
82 if (Subtarget
->inMips16Mode())
85 const Mips16HardFloatInfo::FuncSignature
*>::const_iterator
86 it
= MipsFI
->StubsNeeded
.begin();
87 it
!= MipsFI
->StubsNeeded
.end(); ++it
) {
88 const char *Symbol
= it
->first
;
89 const Mips16HardFloatInfo::FuncSignature
*Signature
= it
->second
;
90 if (StubsNeeded
.find(Symbol
) == StubsNeeded
.end())
91 StubsNeeded
[Symbol
] = Signature
;
93 MCP
= MF
.getConstantPool();
95 // In NaCl, all indirect jump targets must be aligned to bundle size.
96 if (Subtarget
->isTargetNaCl())
97 NaClAlignIndirectJumpTargets(MF
);
99 AsmPrinter::runOnMachineFunction(MF
);
106 bool MipsAsmPrinter::lowerOperand(const MachineOperand
&MO
, MCOperand
&MCOp
) {
107 MCOp
= MCInstLowering
.LowerOperand(MO
);
108 return MCOp
.isValid();
111 #include "MipsGenMCPseudoLowering.inc"
113 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
114 // JALR, or JALR64 as appropriate for the target.
115 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer
&OutStreamer
,
116 const MachineInstr
*MI
) {
117 bool HasLinkReg
= false;
118 bool InMicroMipsMode
= Subtarget
->inMicroMipsMode();
121 if (Subtarget
->hasMips64r6()) {
122 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
123 TmpInst0
.setOpcode(Mips::JALR64
);
125 } else if (Subtarget
->hasMips32r6()) {
126 // MIPS32r6 should use (JALR ZERO, $rs)
128 TmpInst0
.setOpcode(Mips::JRC16_MMR6
);
130 TmpInst0
.setOpcode(Mips::JALR
);
133 } else if (Subtarget
->inMicroMipsMode())
134 // microMIPS should use (JR_MM $rs)
135 TmpInst0
.setOpcode(Mips::JR_MM
);
137 // Everything else should use (JR $rs)
138 TmpInst0
.setOpcode(Mips::JR
);
144 unsigned ZeroReg
= Subtarget
->isGP64bit() ? Mips::ZERO_64
: Mips::ZERO
;
145 TmpInst0
.addOperand(MCOperand::createReg(ZeroReg
));
148 lowerOperand(MI
->getOperand(0), MCOp
);
149 TmpInst0
.addOperand(MCOp
);
151 EmitToStreamer(OutStreamer
, TmpInst0
);
154 // If there is an MO_JALR operand, insert:
156 // .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
159 // This is an optimization hint for the linker which may then replace
160 // an indirect call with a direct branch.
161 static void emitDirectiveRelocJalr(const MachineInstr
&MI
,
162 MCContext
&OutContext
,
164 MCStreamer
&OutStreamer
,
165 const MipsSubtarget
&Subtarget
) {
166 for (unsigned int I
= MI
.getDesc().getNumOperands(), E
= MI
.getNumOperands();
168 MachineOperand MO
= MI
.getOperand(I
);
169 if (MO
.isMCSymbol() && (MO
.getTargetFlags() & MipsII::MO_JALR
)) {
170 MCSymbol
*Callee
= MO
.getMCSymbol();
171 if (Callee
&& !Callee
->getName().empty()) {
172 MCSymbol
*OffsetLabel
= OutContext
.createTempSymbol();
173 const MCExpr
*OffsetExpr
=
174 MCSymbolRefExpr::create(OffsetLabel
, OutContext
);
175 const MCExpr
*CaleeExpr
=
176 MCSymbolRefExpr::create(Callee
, OutContext
);
177 OutStreamer
.EmitRelocDirective
179 Subtarget
.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
180 CaleeExpr
, SMLoc(), *TM
.getMCSubtargetInfo());
181 OutStreamer
.EmitLabel(OffsetLabel
);
188 void MipsAsmPrinter::EmitInstruction(const MachineInstr
*MI
) {
189 MipsTargetStreamer
&TS
= getTargetStreamer();
190 unsigned Opc
= MI
->getOpcode();
191 TS
.forbidModuleDirective();
193 if (MI
->isDebugValue()) {
194 SmallString
<128> Str
;
195 raw_svector_ostream
OS(Str
);
197 PrintDebugValueComment(MI
, OS
);
200 if (MI
->isDebugLabel())
203 // If we just ended a constant pool, mark it as such.
204 if (InConstantPool
&& Opc
!= Mips::CONSTPOOL_ENTRY
) {
205 OutStreamer
->EmitDataRegion(MCDR_DataRegionEnd
);
206 InConstantPool
= false;
208 if (Opc
== Mips::CONSTPOOL_ENTRY
) {
209 // CONSTPOOL_ENTRY - This instruction represents a floating
210 // constant pool in the function. The first operand is the ID#
211 // for this instruction, the second is the index into the
212 // MachineConstantPool that this is, the third is the size in
213 // bytes of this constant pool entry.
214 // The required alignment is specified on the basic block holding this MI.
216 unsigned LabelId
= (unsigned)MI
->getOperand(0).getImm();
217 unsigned CPIdx
= (unsigned)MI
->getOperand(1).getIndex();
219 // If this is the first entry of the pool, mark it.
220 if (!InConstantPool
) {
221 OutStreamer
->EmitDataRegion(MCDR_DataRegion
);
222 InConstantPool
= true;
225 OutStreamer
->EmitLabel(GetCPISymbol(LabelId
));
227 const MachineConstantPoolEntry
&MCPE
= MCP
->getConstants()[CPIdx
];
228 if (MCPE
.isMachineConstantPoolEntry())
229 EmitMachineConstantPoolValue(MCPE
.Val
.MachineCPVal
);
231 EmitGlobalConstant(MF
->getDataLayout(), MCPE
.Val
.ConstVal
);
236 case Mips::PATCHABLE_FUNCTION_ENTER
:
237 LowerPATCHABLE_FUNCTION_ENTER(*MI
);
239 case Mips::PATCHABLE_FUNCTION_EXIT
:
240 LowerPATCHABLE_FUNCTION_EXIT(*MI
);
242 case Mips::PATCHABLE_TAIL_CALL
:
243 LowerPATCHABLE_TAIL_CALL(*MI
);
248 (MI
->isReturn() || MI
->isCall() || MI
->isIndirectBranch())) {
249 emitDirectiveRelocJalr(*MI
, OutContext
, TM
, *OutStreamer
, *Subtarget
);
252 MachineBasicBlock::const_instr_iterator I
= MI
->getIterator();
253 MachineBasicBlock::const_instr_iterator E
= MI
->getParent()->instr_end();
256 // Do any auto-generated pseudo lowerings.
257 if (emitPseudoExpansionLowering(*OutStreamer
, &*I
))
260 if (I
->getOpcode() == Mips::PseudoReturn
||
261 I
->getOpcode() == Mips::PseudoReturn64
||
262 I
->getOpcode() == Mips::PseudoIndirectBranch
||
263 I
->getOpcode() == Mips::PseudoIndirectBranch64
||
264 I
->getOpcode() == Mips::TAILCALLREG
||
265 I
->getOpcode() == Mips::TAILCALLREG64
) {
266 emitPseudoIndirectBranch(*OutStreamer
, &*I
);
270 // The inMips16Mode() test is not permanent.
271 // Some instructions are marked as pseudo right now which
272 // would make the test fail for the wrong reason but
273 // that will be fixed soon. We need this here because we are
274 // removing another test for this situation downstream in the
277 if (I
->isPseudo() && !Subtarget
->inMips16Mode()
278 && !isLongBranchPseudo(I
->getOpcode()))
279 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
282 MCInstLowering
.Lower(&*I
, TmpInst0
);
283 EmitToStreamer(*OutStreamer
, TmpInst0
);
284 } while ((++I
!= E
) && I
->isInsideBundle()); // Delay slot check
287 //===----------------------------------------------------------------------===//
289 // Mips Asm Directives
291 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
292 // Describe the stack frame.
294 // -- Mask directives "(f)mask bitmask, offset"
295 // Tells the assembler which registers are saved and where.
296 // bitmask - contain a little endian bitset indicating which registers are
297 // saved on function prologue (e.g. with a 0x80000000 mask, the
298 // assembler knows the register 31 (RA) is saved at prologue.
299 // offset - the position before stack pointer subtraction indicating where
300 // the first saved register on prologue is located. (e.g. with a
302 // Consider the following function prologue:
305 // .mask 0xc0000000,-8
306 // addiu $sp, $sp, -48
310 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
311 // 30 (FP) are saved at prologue. As the save order on prologue is from
312 // left to right, RA is saved first. A -8 offset means that after the
313 // stack pointer subtration, the first register in the mask (RA) will be
314 // saved at address 48-8=40.
316 //===----------------------------------------------------------------------===//
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
322 // Create a bitmask with all callee saved registers for CPU or Floating Point
323 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
324 void MipsAsmPrinter::printSavedRegsBitmask() {
325 // CPU and FPU Saved Registers Bitmasks
326 unsigned CPUBitmask
= 0, FPUBitmask
= 0;
327 int CPUTopSavedRegOff
, FPUTopSavedRegOff
;
329 // Set the CPU and FPU Bitmasks
330 const MachineFrameInfo
&MFI
= MF
->getFrameInfo();
331 const TargetRegisterInfo
*TRI
= MF
->getSubtarget().getRegisterInfo();
332 const std::vector
<CalleeSavedInfo
> &CSI
= MFI
.getCalleeSavedInfo();
333 // size of stack area to which FP callee-saved regs are saved.
334 unsigned CPURegSize
= TRI
->getRegSizeInBits(Mips::GPR32RegClass
) / 8;
335 unsigned FGR32RegSize
= TRI
->getRegSizeInBits(Mips::FGR32RegClass
) / 8;
336 unsigned AFGR64RegSize
= TRI
->getRegSizeInBits(Mips::AFGR64RegClass
) / 8;
337 bool HasAFGR64Reg
= false;
338 unsigned CSFPRegsSize
= 0;
340 for (const auto &I
: CSI
) {
341 unsigned Reg
= I
.getReg();
342 unsigned RegNum
= TRI
->getEncodingValue(Reg
);
344 // If it's a floating point register, set the FPU Bitmask.
345 // If it's a general purpose register, set the CPU Bitmask.
346 if (Mips::FGR32RegClass
.contains(Reg
)) {
347 FPUBitmask
|= (1 << RegNum
);
348 CSFPRegsSize
+= FGR32RegSize
;
349 } else if (Mips::AFGR64RegClass
.contains(Reg
)) {
350 FPUBitmask
|= (3 << RegNum
);
351 CSFPRegsSize
+= AFGR64RegSize
;
353 } else if (Mips::GPR32RegClass
.contains(Reg
))
354 CPUBitmask
|= (1 << RegNum
);
357 // FP Regs are saved right below where the virtual frame pointer points to.
358 FPUTopSavedRegOff
= FPUBitmask
?
359 (HasAFGR64Reg
? -AFGR64RegSize
: -FGR32RegSize
) : 0;
361 // CPU Regs are saved below FP Regs.
362 CPUTopSavedRegOff
= CPUBitmask
? -CSFPRegsSize
- CPURegSize
: 0;
364 MipsTargetStreamer
&TS
= getTargetStreamer();
366 TS
.emitMask(CPUBitmask
, CPUTopSavedRegOff
);
369 TS
.emitFMask(FPUBitmask
, FPUTopSavedRegOff
);
372 //===----------------------------------------------------------------------===//
373 // Frame and Set directives
374 //===----------------------------------------------------------------------===//
377 void MipsAsmPrinter::emitFrameDirective() {
378 const TargetRegisterInfo
&RI
= *MF
->getSubtarget().getRegisterInfo();
380 Register stackReg
= RI
.getFrameRegister(*MF
);
381 unsigned returnReg
= RI
.getRARegister();
382 unsigned stackSize
= MF
->getFrameInfo().getStackSize();
384 getTargetStreamer().emitFrame(stackReg
, stackSize
, returnReg
);
387 /// Emit Set directives.
388 const char *MipsAsmPrinter::getCurrentABIString() const {
389 switch (static_cast<MipsTargetMachine
&>(TM
).getABI().GetEnumValue()) {
390 case MipsABIInfo::ABI::O32
: return "abi32";
391 case MipsABIInfo::ABI::N32
: return "abiN32";
392 case MipsABIInfo::ABI::N64
: return "abi64";
393 default: llvm_unreachable("Unknown Mips ABI");
397 void MipsAsmPrinter::EmitFunctionEntryLabel() {
398 MipsTargetStreamer
&TS
= getTargetStreamer();
400 // NaCl sandboxing requires that indirect call instructions are masked.
401 // This means that function entry points should be bundle-aligned.
402 if (Subtarget
->isTargetNaCl())
403 EmitAlignment(std::max(MF
->getAlignment(), MIPS_NACL_BUNDLE_ALIGN
));
405 if (Subtarget
->inMicroMipsMode()) {
406 TS
.emitDirectiveSetMicroMips();
407 TS
.setUsesMicroMips();
408 TS
.updateABIInfo(*Subtarget
);
410 TS
.emitDirectiveSetNoMicroMips();
412 if (Subtarget
->inMips16Mode())
413 TS
.emitDirectiveSetMips16();
415 TS
.emitDirectiveSetNoMips16();
417 TS
.emitDirectiveEnt(*CurrentFnSym
);
418 OutStreamer
->EmitLabel(CurrentFnSym
);
421 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
422 /// the first basic block in the function.
423 void MipsAsmPrinter::EmitFunctionBodyStart() {
424 MipsTargetStreamer
&TS
= getTargetStreamer();
426 MCInstLowering
.Initialize(&MF
->getContext());
428 bool IsNakedFunction
= MF
->getFunction().hasFnAttribute(Attribute::Naked
);
429 if (!IsNakedFunction
)
430 emitFrameDirective();
432 if (!IsNakedFunction
)
433 printSavedRegsBitmask();
435 if (!Subtarget
->inMips16Mode()) {
436 TS
.emitDirectiveSetNoReorder();
437 TS
.emitDirectiveSetNoMacro();
438 TS
.emitDirectiveSetNoAt();
442 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
443 /// the last basic block in the function.
444 void MipsAsmPrinter::EmitFunctionBodyEnd() {
445 MipsTargetStreamer
&TS
= getTargetStreamer();
447 // There are instruction for this macros, but they must
448 // always be at the function end, and we can't emit and
449 // break with BB logic.
450 if (!Subtarget
->inMips16Mode()) {
451 TS
.emitDirectiveSetAt();
452 TS
.emitDirectiveSetMacro();
453 TS
.emitDirectiveSetReorder();
455 TS
.emitDirectiveEnd(CurrentFnSym
->getName());
456 // Make sure to terminate any constant pools that were at the end
460 InConstantPool
= false;
461 OutStreamer
->EmitDataRegion(MCDR_DataRegionEnd
);
464 void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock
&MBB
) {
465 AsmPrinter::EmitBasicBlockEnd(MBB
);
466 MipsTargetStreamer
&TS
= getTargetStreamer();
468 TS
.emitDirectiveInsn();
471 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
472 /// exactly one predecessor and the control transfer mechanism between
473 /// the predecessor and this block is a fall-through.
474 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock
*
476 // The predecessor has to be immediately before this block.
477 const MachineBasicBlock
*Pred
= *MBB
->pred_begin();
479 // If the predecessor is a switch statement, assume a jump table
480 // implementation, so it is not a fall through.
481 if (const BasicBlock
*bb
= Pred
->getBasicBlock())
482 if (isa
<SwitchInst
>(bb
->getTerminator()))
485 // If this is a landing pad, it isn't a fall through. If it has no preds,
486 // then nothing falls through to it.
487 if (MBB
->isEHPad() || MBB
->pred_empty())
490 // If there isn't exactly one predecessor, it can't be a fall through.
491 MachineBasicBlock::const_pred_iterator PI
= MBB
->pred_begin(), PI2
= PI
;
494 if (PI2
!= MBB
->pred_end())
497 // The predecessor has to be immediately before this block.
498 if (!Pred
->isLayoutSuccessor(MBB
))
501 // If the block is completely empty, then it definitely does fall through.
505 // Otherwise, check the last instruction.
506 // Check if the last terminator is an unconditional branch.
507 MachineBasicBlock::const_iterator I
= Pred
->end();
508 while (I
!= Pred
->begin() && !(--I
)->isTerminator()) ;
510 return !I
->isBarrier();
513 // Print out an operand for an inline asm expression.
514 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr
*MI
, unsigned OpNum
,
515 const char *ExtraCode
, raw_ostream
&O
) {
516 // Does this asm operand have a single letter operand modifier?
517 if (ExtraCode
&& ExtraCode
[0]) {
518 if (ExtraCode
[1] != 0) return true; // Unknown modifier.
520 const MachineOperand
&MO
= MI
->getOperand(OpNum
);
521 switch (ExtraCode
[0]) {
523 // See if this is a generic print operand
524 return AsmPrinter::PrintAsmOperand(MI
, OpNum
, ExtraCode
, O
);
525 case 'X': // hex const int
526 if ((MO
.getType()) != MachineOperand::MO_Immediate
)
528 O
<< "0x" << Twine::utohexstr(MO
.getImm());
530 case 'x': // hex const int (low 16 bits)
531 if ((MO
.getType()) != MachineOperand::MO_Immediate
)
533 O
<< "0x" << Twine::utohexstr(MO
.getImm() & 0xffff);
535 case 'd': // decimal const int
536 if ((MO
.getType()) != MachineOperand::MO_Immediate
)
540 case 'm': // decimal const int minus 1
541 if ((MO
.getType()) != MachineOperand::MO_Immediate
)
543 O
<< MO
.getImm() - 1;
545 case 'y': // exact log2
546 if ((MO
.getType()) != MachineOperand::MO_Immediate
)
548 if (!isPowerOf2_64(MO
.getImm()))
550 O
<< Log2_64(MO
.getImm());
553 // $0 if zero, regular printing otherwise
554 if (MO
.getType() == MachineOperand::MO_Immediate
&& MO
.getImm() == 0) {
558 // If not, call printOperand as normal.
560 case 'D': // Second part of a double word register operand
561 case 'L': // Low order register of a double word register operand
562 case 'M': // High order register of a double word register operand
566 const MachineOperand
&FlagsOP
= MI
->getOperand(OpNum
- 1);
567 if (!FlagsOP
.isImm())
569 unsigned Flags
= FlagsOP
.getImm();
570 unsigned NumVals
= InlineAsm::getNumOperandRegisters(Flags
);
571 // Number of registers represented by this operand. We are looking
572 // for 2 for 32 bit mode and 1 for 64 bit mode.
574 if (Subtarget
->isGP64bit() && NumVals
== 1 && MO
.isReg()) {
575 Register Reg
= MO
.getReg();
576 O
<< '$' << MipsInstPrinter::getRegisterName(Reg
);
582 unsigned RegOp
= OpNum
;
583 if (!Subtarget
->isGP64bit()){
584 // Endianness reverses which register holds the high or low value
586 switch(ExtraCode
[0]) {
588 RegOp
= (Subtarget
->isLittle()) ? OpNum
+ 1 : OpNum
;
591 RegOp
= (Subtarget
->isLittle()) ? OpNum
: OpNum
+ 1;
593 case 'D': // Always the second part
596 if (RegOp
>= MI
->getNumOperands())
598 const MachineOperand
&MO
= MI
->getOperand(RegOp
);
601 Register Reg
= MO
.getReg();
602 O
<< '$' << MipsInstPrinter::getRegisterName(Reg
);
608 // Print MSA registers for the 'f' constraint
609 // In LLVM, the 'w' modifier doesn't need to do anything.
610 // We can just call printOperand as normal.
615 printOperand(MI
, OpNum
, O
);
619 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr
*MI
,
621 const char *ExtraCode
,
623 assert(OpNum
+ 1 < MI
->getNumOperands() && "Insufficient operands");
624 const MachineOperand
&BaseMO
= MI
->getOperand(OpNum
);
625 const MachineOperand
&OffsetMO
= MI
->getOperand(OpNum
+ 1);
626 assert(BaseMO
.isReg() && "Unexpected base pointer for inline asm memory operand.");
627 assert(OffsetMO
.isImm() && "Unexpected offset for inline asm memory operand.");
628 int Offset
= OffsetMO
.getImm();
630 // Currently we are expecting either no ExtraCode or 'D','M','L'.
632 switch (ExtraCode
[0]) {
637 if (Subtarget
->isLittle())
641 if (!Subtarget
->isLittle())
645 return true; // Unknown modifier.
649 O
<< Offset
<< "($" << MipsInstPrinter::getRegisterName(BaseMO
.getReg())
655 void MipsAsmPrinter::printOperand(const MachineInstr
*MI
, int opNum
,
657 const MachineOperand
&MO
= MI
->getOperand(opNum
);
660 if (MO
.getTargetFlags())
663 switch(MO
.getTargetFlags()) {
664 case MipsII::MO_GPREL
: O
<< "%gp_rel("; break;
665 case MipsII::MO_GOT_CALL
: O
<< "%call16("; break;
666 case MipsII::MO_GOT
: O
<< "%got("; break;
667 case MipsII::MO_ABS_HI
: O
<< "%hi("; break;
668 case MipsII::MO_ABS_LO
: O
<< "%lo("; break;
669 case MipsII::MO_HIGHER
: O
<< "%higher("; break;
670 case MipsII::MO_HIGHEST
: O
<< "%highest(("; break;
671 case MipsII::MO_TLSGD
: O
<< "%tlsgd("; break;
672 case MipsII::MO_GOTTPREL
: O
<< "%gottprel("; break;
673 case MipsII::MO_TPREL_HI
: O
<< "%tprel_hi("; break;
674 case MipsII::MO_TPREL_LO
: O
<< "%tprel_lo("; break;
675 case MipsII::MO_GPOFF_HI
: O
<< "%hi(%neg(%gp_rel("; break;
676 case MipsII::MO_GPOFF_LO
: O
<< "%lo(%neg(%gp_rel("; break;
677 case MipsII::MO_GOT_DISP
: O
<< "%got_disp("; break;
678 case MipsII::MO_GOT_PAGE
: O
<< "%got_page("; break;
679 case MipsII::MO_GOT_OFST
: O
<< "%got_ofst("; break;
682 switch (MO
.getType()) {
683 case MachineOperand::MO_Register
:
685 << StringRef(MipsInstPrinter::getRegisterName(MO
.getReg())).lower();
688 case MachineOperand::MO_Immediate
:
692 case MachineOperand::MO_MachineBasicBlock
:
693 MO
.getMBB()->getSymbol()->print(O
, MAI
);
696 case MachineOperand::MO_GlobalAddress
:
697 PrintSymbolOperand(MO
, O
);
700 case MachineOperand::MO_BlockAddress
: {
701 MCSymbol
*BA
= GetBlockAddressSymbol(MO
.getBlockAddress());
706 case MachineOperand::MO_ConstantPoolIndex
:
707 O
<< getDataLayout().getPrivateGlobalPrefix() << "CPI"
708 << getFunctionNumber() << "_" << MO
.getIndex();
710 O
<< "+" << MO
.getOffset();
714 llvm_unreachable("<unknown operand type>");
717 if (closeP
) O
<< ")";
720 void MipsAsmPrinter::
721 printMemOperand(const MachineInstr
*MI
, int opNum
, raw_ostream
&O
) {
722 // Load/Store memory operands -- imm($reg)
723 // If PIC target the target is loaded as the
724 // pattern lw $25,%call16($28)
726 // opNum can be invalid if instruction has reglist as operand.
727 // MemOperand is always last operand of instruction (base + offset).
728 switch (MI
->getOpcode()) {
733 opNum
= MI
->getNumOperands() - 2;
737 printOperand(MI
, opNum
+1, O
);
739 printOperand(MI
, opNum
, O
);
743 void MipsAsmPrinter::
744 printMemOperandEA(const MachineInstr
*MI
, int opNum
, raw_ostream
&O
) {
745 // when using stack locations for not load/store instructions
746 // print the same way as all normal 3 operand instructions.
747 printOperand(MI
, opNum
, O
);
749 printOperand(MI
, opNum
+1, O
);
752 void MipsAsmPrinter::
753 printFCCOperand(const MachineInstr
*MI
, int opNum
, raw_ostream
&O
,
754 const char *Modifier
) {
755 const MachineOperand
&MO
= MI
->getOperand(opNum
);
756 O
<< Mips::MipsFCCToString((Mips::CondCode
)MO
.getImm());
759 void MipsAsmPrinter::
760 printRegisterList(const MachineInstr
*MI
, int opNum
, raw_ostream
&O
) {
761 for (int i
= opNum
, e
= MI
->getNumOperands(); i
!= e
; ++i
) {
762 if (i
!= opNum
) O
<< ", ";
763 printOperand(MI
, i
, O
);
767 void MipsAsmPrinter::EmitStartOfAsmFile(Module
&M
) {
768 MipsTargetStreamer
&TS
= getTargetStreamer();
770 // MipsTargetStreamer has an initialization order problem when emitting an
771 // object file directly (see MipsTargetELFStreamer for full details). Work
772 // around it by re-initializing the PIC state here.
773 TS
.setPic(OutContext
.getObjectFileInfo()->isPositionIndependent());
775 // Compute MIPS architecture attributes based on the default subtarget
776 // that we'd have constructed. Module level directives aren't LTO
778 // FIXME: For ifunc related functions we could iterate over and look
779 // for a feature string that doesn't match the default one.
780 const Triple
&TT
= TM
.getTargetTriple();
781 StringRef CPU
= MIPS_MC::selectMipsCPU(TT
, TM
.getTargetCPU());
782 StringRef FS
= TM
.getTargetFeatureString();
783 const MipsTargetMachine
&MTM
= static_cast<const MipsTargetMachine
&>(TM
);
784 const MipsSubtarget
STI(TT
, CPU
, FS
, MTM
.isLittleEndian(), MTM
, 0);
786 bool IsABICalls
= STI
.isABICalls();
787 const MipsABIInfo
&ABI
= MTM
.getABI();
789 TS
.emitDirectiveAbiCalls();
790 // FIXME: This condition should be a lot more complicated that it is here.
791 // Ideally it should test for properties of the ABI and not the ABI
793 // For the moment, I'm only correcting enough to make MIPS-IV work.
794 if (!isPositionIndependent() && STI
.hasSym32())
795 TS
.emitDirectiveOptionPic0();
798 // Tell the assembler which ABI we are using
799 std::string SectionName
= std::string(".mdebug.") + getCurrentABIString();
800 OutStreamer
->SwitchSection(
801 OutContext
.getELFSection(SectionName
, ELF::SHT_PROGBITS
, 0));
803 // NaN: At the moment we only support:
804 // 1. .nan legacy (default)
806 STI
.isNaN2008() ? TS
.emitDirectiveNaN2008()
807 : TS
.emitDirectiveNaNLegacy();
809 // TODO: handle O64 ABI
811 TS
.updateABIInfo(STI
);
813 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
814 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
815 // -mfp64) and omit it otherwise.
816 if ((ABI
.IsO32() && (STI
.isABI_FPXX() || STI
.isFP64bit())) ||
818 TS
.emitDirectiveModuleFP();
820 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
821 // accept it. We therefore emit it when it contradicts the default or an
822 // option has changed the default (i.e. FPXX) and omit it otherwise.
823 if (ABI
.IsO32() && (!STI
.useOddSPReg() || STI
.isABI_FPXX()))
824 TS
.emitDirectiveModuleOddSPReg();
826 // Switch to the .text section.
827 OutStreamer
->SwitchSection(getObjFileLowering().getTextSection());
830 void MipsAsmPrinter::emitInlineAsmStart() const {
831 MipsTargetStreamer
&TS
= getTargetStreamer();
833 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
834 // and 'reorder') is different from LLVM's choice for generated code ('noat',
835 // 'nomacro' and 'noreorder').
836 // In order to maintain compatibility with inline assembly code which depends
837 // on GCC's assembler options being used, we have to switch to those options
838 // for the duration of the inline assembly block and then switch back.
839 TS
.emitDirectiveSetPush();
840 TS
.emitDirectiveSetAt();
841 TS
.emitDirectiveSetMacro();
842 TS
.emitDirectiveSetReorder();
843 OutStreamer
->AddBlankLine();
846 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo
&StartInfo
,
847 const MCSubtargetInfo
*EndInfo
) const {
848 OutStreamer
->AddBlankLine();
849 getTargetStreamer().emitDirectiveSetPop();
852 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo
&STI
, MCSymbol
*Symbol
) {
854 I
.setOpcode(Mips::JAL
);
856 MCOperand::createExpr(MCSymbolRefExpr::create(Symbol
, OutContext
)));
857 OutStreamer
->EmitInstruction(I
, STI
);
860 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo
&STI
, unsigned Opcode
,
864 I
.addOperand(MCOperand::createReg(Reg
));
865 OutStreamer
->EmitInstruction(I
, STI
);
868 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo
&STI
,
869 unsigned Opcode
, unsigned Reg1
,
873 // Because of the current td files for Mips32, the operands for MTC1
874 // appear backwards from their normal assembly order. It's not a trivial
875 // change to fix this in the td file so we adjust for it here.
877 if (Opcode
== Mips::MTC1
) {
878 unsigned Temp
= Reg1
;
883 I
.addOperand(MCOperand::createReg(Reg1
));
884 I
.addOperand(MCOperand::createReg(Reg2
));
885 OutStreamer
->EmitInstruction(I
, STI
);
888 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo
&STI
,
889 unsigned Opcode
, unsigned Reg1
,
890 unsigned Reg2
, unsigned Reg3
) {
893 I
.addOperand(MCOperand::createReg(Reg1
));
894 I
.addOperand(MCOperand::createReg(Reg2
));
895 I
.addOperand(MCOperand::createReg(Reg3
));
896 OutStreamer
->EmitInstruction(I
, STI
);
899 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo
&STI
,
900 unsigned MovOpc
, unsigned Reg1
,
901 unsigned Reg2
, unsigned FPReg1
,
902 unsigned FPReg2
, bool LE
) {
904 unsigned temp
= Reg1
;
908 EmitInstrRegReg(STI
, MovOpc
, Reg1
, FPReg1
);
909 EmitInstrRegReg(STI
, MovOpc
, Reg2
, FPReg2
);
912 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo
&STI
,
913 Mips16HardFloatInfo::FPParamVariant PV
,
914 bool LE
, bool ToFP
) {
915 using namespace Mips16HardFloatInfo
;
917 unsigned MovOpc
= ToFP
? Mips::MTC1
: Mips::MFC1
;
920 EmitInstrRegReg(STI
, MovOpc
, Mips::A0
, Mips::F12
);
923 EmitMovFPIntPair(STI
, MovOpc
, Mips::A0
, Mips::A1
, Mips::F12
, Mips::F14
, LE
);
926 EmitInstrRegReg(STI
, MovOpc
, Mips::A0
, Mips::F12
);
927 EmitMovFPIntPair(STI
, MovOpc
, Mips::A2
, Mips::A3
, Mips::F14
, Mips::F15
, LE
);
930 EmitMovFPIntPair(STI
, MovOpc
, Mips::A0
, Mips::A1
, Mips::F12
, Mips::F13
, LE
);
933 EmitMovFPIntPair(STI
, MovOpc
, Mips::A0
, Mips::A1
, Mips::F12
, Mips::F13
, LE
);
934 EmitMovFPIntPair(STI
, MovOpc
, Mips::A2
, Mips::A3
, Mips::F14
, Mips::F15
, LE
);
937 EmitMovFPIntPair(STI
, MovOpc
, Mips::A0
, Mips::A1
, Mips::F12
, Mips::F13
, LE
);
938 EmitInstrRegReg(STI
, MovOpc
, Mips::A2
, Mips::F14
);
945 void MipsAsmPrinter::EmitSwapFPIntRetval(
946 const MCSubtargetInfo
&STI
, Mips16HardFloatInfo::FPReturnVariant RV
,
948 using namespace Mips16HardFloatInfo
;
950 unsigned MovOpc
= Mips::MFC1
;
953 EmitInstrRegReg(STI
, MovOpc
, Mips::V0
, Mips::F0
);
956 EmitMovFPIntPair(STI
, MovOpc
, Mips::V0
, Mips::V1
, Mips::F0
, Mips::F1
, LE
);
959 EmitMovFPIntPair(STI
, MovOpc
, Mips::V0
, Mips::V1
, Mips::F0
, Mips::F1
, LE
);
962 EmitMovFPIntPair(STI
, MovOpc
, Mips::V0
, Mips::V1
, Mips::F0
, Mips::F1
, LE
);
963 EmitMovFPIntPair(STI
, MovOpc
, Mips::A0
, Mips::A1
, Mips::F2
, Mips::F3
, LE
);
970 void MipsAsmPrinter::EmitFPCallStub(
971 const char *Symbol
, const Mips16HardFloatInfo::FuncSignature
*Signature
) {
972 using namespace Mips16HardFloatInfo
;
974 MCSymbol
*MSymbol
= OutContext
.getOrCreateSymbol(StringRef(Symbol
));
975 bool LE
= getDataLayout().isLittleEndian();
976 // Construct a local MCSubtargetInfo here.
977 // This is because the MachineFunction won't exist (but have not yet been
978 // freed) and since we're at the global level we can use the default
979 // constructed subtarget.
980 std::unique_ptr
<MCSubtargetInfo
> STI(TM
.getTarget().createMCSubtargetInfo(
981 TM
.getTargetTriple().str(), TM
.getTargetCPU(),
982 TM
.getTargetFeatureString()));
987 OutStreamer
->EmitSymbolAttribute(MSymbol
, MCSA_Global
);
990 // make the comment field identifying the return and parameter
991 // types of the floating point stub
992 // # Stub function to call rettype xxxx (params)
994 switch (Signature
->RetSig
) {
1002 RetType
= "complex";
1005 RetType
= "double complex";
1012 switch (Signature
->ParamSig
) {
1017 Parms
= "float, float";
1020 Parms
= "float, double";
1026 Parms
= "double, double";
1029 Parms
= "double, float";
1035 OutStreamer
->AddComment("\t# Stub function to call " + Twine(RetType
) + " " +
1036 Twine(Symbol
) + " (" + Twine(Parms
) + ")");
1038 // probably not necessary but we save and restore the current section state
1040 OutStreamer
->PushSection();
1042 // .section mips16.call.fpxxxx,"ax",@progbits
1044 MCSectionELF
*M
= OutContext
.getELFSection(
1045 ".mips16.call.fp." + std::string(Symbol
), ELF::SHT_PROGBITS
,
1046 ELF::SHF_ALLOC
| ELF::SHF_EXECINSTR
);
1047 OutStreamer
->SwitchSection(M
, nullptr);
1051 OutStreamer
->EmitValueToAlignment(4);
1052 MipsTargetStreamer
&TS
= getTargetStreamer();
1057 TS
.emitDirectiveSetNoMips16();
1058 TS
.emitDirectiveSetNoMicroMips();
1060 // .ent __call_stub_fp_xxxx
1061 // .type __call_stub_fp_xxxx,@function
1062 // __call_stub_fp_xxxx:
1064 std::string x
= "__call_stub_fp_" + std::string(Symbol
);
1066 cast
<MCSymbolELF
>(OutContext
.getOrCreateSymbol(StringRef(x
)));
1067 TS
.emitDirectiveEnt(*Stub
);
1069 OutContext
.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol
));
1070 OutStreamer
->EmitSymbolAttribute(MType
, MCSA_ELF_TypeFunction
);
1071 OutStreamer
->EmitLabel(Stub
);
1073 // Only handle non-pic for now.
1074 assert(!isPositionIndependent() &&
1075 "should not be here if we are compiling pic");
1076 TS
.emitDirectiveSetReorder();
1078 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
1079 // stubs without raw text but this current patch is for compiler generated
1080 // functions and they all return some value.
1081 // The calling sequence for non pic is different in that case and we need
1082 // to implement %lo and %hi in order to handle the case of no return value
1083 // See the corresponding method in Mips16HardFloat for details.
1085 // mov the return address to S2.
1086 // we have no stack space to store it and we are about to make another call.
1087 // We need to make sure that the enclosing function knows to save S2
1088 // This should have already been handled.
1092 EmitInstrRegRegReg(*STI
, Mips::OR
, Mips::S2
, Mips::RA
, Mips::ZERO
);
1094 EmitSwapFPIntParams(*STI
, Signature
->ParamSig
, LE
, true);
1098 EmitJal(*STI
, MSymbol
);
1100 // fix return values
1101 EmitSwapFPIntRetval(*STI
, Signature
->RetSig
, LE
);
1104 // if (Signature->RetSig == NoFPRet)
1105 // llvm_unreachable("should not be any stubs here with no return value");
1107 EmitInstrReg(*STI
, Mips::JR
, Mips::S2
);
1109 MCSymbol
*Tmp
= OutContext
.createTempSymbol();
1110 OutStreamer
->EmitLabel(Tmp
);
1111 const MCSymbolRefExpr
*E
= MCSymbolRefExpr::create(Stub
, OutContext
);
1112 const MCSymbolRefExpr
*T
= MCSymbolRefExpr::create(Tmp
, OutContext
);
1113 const MCExpr
*T_min_E
= MCBinaryExpr::createSub(T
, E
, OutContext
);
1114 OutStreamer
->emitELFSize(Stub
, T_min_E
);
1115 TS
.emitDirectiveEnd(x
);
1116 OutStreamer
->PopSection();
1119 void MipsAsmPrinter::EmitEndOfAsmFile(Module
&M
) {
1120 // Emit needed stubs
1124 const Mips16HardFloatInfo::FuncSignature
*>::const_iterator
1125 it
= StubsNeeded
.begin();
1126 it
!= StubsNeeded
.end(); ++it
) {
1127 const char *Symbol
= it
->first
;
1128 const Mips16HardFloatInfo::FuncSignature
*Signature
= it
->second
;
1129 EmitFPCallStub(Symbol
, Signature
);
1131 // return to the text section
1132 OutStreamer
->SwitchSection(OutContext
.getObjectFileInfo()->getTextSection());
1135 void MipsAsmPrinter::EmitSled(const MachineInstr
&MI
, SledKind Kind
) {
1136 const uint8_t NoopsInSledCount
= Subtarget
->isGP64bit() ? 15 : 11;
1137 // For mips32 we want to emit the following pattern:
1142 // 11 NOP instructions (44 bytes)
1146 // We need the 44 bytes (11 instructions) because at runtime, we'd
1147 // be patching over the full 48 bytes (12 instructions) with the following
1154 // LUI T9, %hi(__xray_FunctionEntry/Exit)
1155 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1156 // LUI T0, %hi(function_id)
1158 // ORI T0, T0, %lo(function_id)
1163 // We add 52 bytes to t9 because we want to adjust the function pointer to
1164 // the actual start of function i.e. the address just after the noop sled.
1165 // We do this because gp displacement relocation is emitted at the start of
1166 // of the function i.e after the nop sled and to correctly calculate the
1167 // global offset table address, t9 must hold the address of the instruction
1168 // containing the gp displacement relocation.
1169 // FIXME: Is this correct for the static relocation model?
1171 // For mips64 we want to emit the following pattern:
1176 // 15 NOP instructions (60 bytes)
1179 // We need the 60 bytes (15 instructions) because at runtime, we'd
1180 // be patching over the full 64 bytes (16 instructions) with the following
1183 // DADDIU SP, SP, -16
1187 // LUI T9, %highest(__xray_FunctionEntry/Exit)
1188 // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1190 // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1192 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1193 // LUI T0, %hi(function_id)
1195 // ADDIU T0, T0, %lo(function_id)
1198 // DADDIU SP, SP, 16
1200 OutStreamer
->EmitCodeAlignment(4);
1201 auto CurSled
= OutContext
.createTempSymbol("xray_sled_", true);
1202 OutStreamer
->EmitLabel(CurSled
);
1203 auto Target
= OutContext
.createTempSymbol();
1205 // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1206 // start of function
1207 const MCExpr
*TargetExpr
= MCSymbolRefExpr::create(
1208 Target
, MCSymbolRefExpr::VariantKind::VK_None
, OutContext
);
1209 EmitToStreamer(*OutStreamer
, MCInstBuilder(Mips::BEQ
)
1212 .addExpr(TargetExpr
));
1214 for (int8_t I
= 0; I
< NoopsInSledCount
; I
++)
1215 EmitToStreamer(*OutStreamer
, MCInstBuilder(Mips::SLL
)
1220 OutStreamer
->EmitLabel(Target
);
1222 if (!Subtarget
->isGP64bit()) {
1223 EmitToStreamer(*OutStreamer
,
1224 MCInstBuilder(Mips::ADDiu
)
1230 recordSled(CurSled
, MI
, Kind
);
1233 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr
&MI
) {
1234 EmitSled(MI
, SledKind::FUNCTION_ENTER
);
1237 void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr
&MI
) {
1238 EmitSled(MI
, SledKind::FUNCTION_EXIT
);
1241 void MipsAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr
&MI
) {
1242 EmitSled(MI
, SledKind::TAIL_CALL
);
1245 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr
*MI
,
1250 // Emit .dtprelword or .dtpreldword directive
1251 // and value for debug thread local expression.
1252 void MipsAsmPrinter::EmitDebugValue(const MCExpr
*Value
, unsigned Size
) const {
1253 if (auto *MipsExpr
= dyn_cast
<MipsMCExpr
>(Value
)) {
1254 if (MipsExpr
&& MipsExpr
->getKind() == MipsMCExpr::MEK_DTPREL
) {
1257 OutStreamer
->EmitDTPRel32Value(MipsExpr
->getSubExpr());
1260 OutStreamer
->EmitDTPRel64Value(MipsExpr
->getSubExpr());
1263 llvm_unreachable("Unexpected size of expression value.");
1268 AsmPrinter::EmitDebugValue(Value
, Size
);
1271 // Align all targets of indirect branches on bundle size. Used only if target
1273 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction
&MF
) {
1274 // Align all blocks that are jumped to through jump table.
1275 if (MachineJumpTableInfo
*JtInfo
= MF
.getJumpTableInfo()) {
1276 const std::vector
<MachineJumpTableEntry
> &JT
= JtInfo
->getJumpTables();
1277 for (unsigned I
= 0; I
< JT
.size(); ++I
) {
1278 const std::vector
<MachineBasicBlock
*> &MBBs
= JT
[I
].MBBs
;
1280 for (unsigned J
= 0; J
< MBBs
.size(); ++J
)
1281 MBBs
[J
]->setAlignment(MIPS_NACL_BUNDLE_ALIGN
);
1285 // If basic block address is taken, block can be target of indirect branch.
1286 for (auto &MBB
: MF
) {
1287 if (MBB
.hasAddressTaken())
1288 MBB
.setAlignment(MIPS_NACL_BUNDLE_ALIGN
);
1292 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode
) const {
1293 return (Opcode
== Mips::LONG_BRANCH_LUi
1294 || Opcode
== Mips::LONG_BRANCH_LUi2Op
1295 || Opcode
== Mips::LONG_BRANCH_LUi2Op_64
1296 || Opcode
== Mips::LONG_BRANCH_ADDiu
1297 || Opcode
== Mips::LONG_BRANCH_ADDiu2Op
1298 || Opcode
== Mips::LONG_BRANCH_DADDiu
1299 || Opcode
== Mips::LONG_BRANCH_DADDiu2Op
);
1302 // Force static initialization.
1303 extern "C" void LLVMInitializeMipsAsmPrinter() {
1304 RegisterAsmPrinter
<MipsAsmPrinter
> X(getTheMipsTarget());
1305 RegisterAsmPrinter
<MipsAsmPrinter
> Y(getTheMipselTarget());
1306 RegisterAsmPrinter
<MipsAsmPrinter
> A(getTheMips64Target());
1307 RegisterAsmPrinter
<MipsAsmPrinter
> B(getTheMips64elTarget());