1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Pass to verify generated machine code. The following is checked:
11 // Operand counts: All explicit operands must be present.
13 // Register classes: All physical and virtual register operands must be
14 // compatible with the register class required by the instruction descriptor.
16 // Register live intervals: Registers must be defined only once, and must be
17 // defined before use.
19 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
20 // command-line option -verify-machineinstrs, or by defining the environment
21 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
22 // the verifier errors.
23 //===----------------------------------------------------------------------===//
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SetOperations.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringRef.h"
34 #include "llvm/ADT/Twine.h"
35 #include "llvm/Analysis/EHPersonalities.h"
36 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
37 #include "llvm/CodeGen/LiveInterval.h"
38 #include "llvm/CodeGen/LiveIntervals.h"
39 #include "llvm/CodeGen/LiveRangeCalc.h"
40 #include "llvm/CodeGen/LiveStacks.h"
41 #include "llvm/CodeGen/LiveVariables.h"
42 #include "llvm/CodeGen/MachineBasicBlock.h"
43 #include "llvm/CodeGen/MachineFrameInfo.h"
44 #include "llvm/CodeGen/MachineFunction.h"
45 #include "llvm/CodeGen/MachineFunctionPass.h"
46 #include "llvm/CodeGen/MachineInstr.h"
47 #include "llvm/CodeGen/MachineInstrBundle.h"
48 #include "llvm/CodeGen/MachineMemOperand.h"
49 #include "llvm/CodeGen/MachineOperand.h"
50 #include "llvm/CodeGen/MachineRegisterInfo.h"
51 #include "llvm/CodeGen/PseudoSourceValue.h"
52 #include "llvm/CodeGen/SlotIndexes.h"
53 #include "llvm/CodeGen/StackMaps.h"
54 #include "llvm/CodeGen/TargetInstrInfo.h"
55 #include "llvm/CodeGen/TargetOpcodes.h"
56 #include "llvm/CodeGen/TargetRegisterInfo.h"
57 #include "llvm/CodeGen/TargetSubtargetInfo.h"
58 #include "llvm/IR/BasicBlock.h"
59 #include "llvm/IR/Function.h"
60 #include "llvm/IR/InlineAsm.h"
61 #include "llvm/IR/Instructions.h"
62 #include "llvm/MC/LaneBitmask.h"
63 #include "llvm/MC/MCAsmInfo.h"
64 #include "llvm/MC/MCInstrDesc.h"
65 #include "llvm/MC/MCRegisterInfo.h"
66 #include "llvm/MC/MCTargetOptions.h"
67 #include "llvm/Pass.h"
68 #include "llvm/Support/Casting.h"
69 #include "llvm/Support/ErrorHandling.h"
70 #include "llvm/Support/LowLevelTypeImpl.h"
71 #include "llvm/Support/MathExtras.h"
72 #include "llvm/Support/raw_ostream.h"
73 #include "llvm/Target/TargetMachine.h"
86 struct MachineVerifier
{
87 MachineVerifier(Pass
*pass
, const char *b
) : PASS(pass
), Banner(b
) {}
89 unsigned verify(MachineFunction
&MF
);
93 const MachineFunction
*MF
;
94 const TargetMachine
*TM
;
95 const TargetInstrInfo
*TII
;
96 const TargetRegisterInfo
*TRI
;
97 const MachineRegisterInfo
*MRI
;
101 // Avoid querying the MachineFunctionProperties for each operand.
102 bool isFunctionRegBankSelected
;
103 bool isFunctionSelected
;
105 using RegVector
= SmallVector
<unsigned, 16>;
106 using RegMaskVector
= SmallVector
<const uint32_t *, 4>;
107 using RegSet
= DenseSet
<unsigned>;
108 using RegMap
= DenseMap
<unsigned, const MachineInstr
*>;
109 using BlockSet
= SmallPtrSet
<const MachineBasicBlock
*, 8>;
111 const MachineInstr
*FirstNonPHI
;
112 const MachineInstr
*FirstTerminator
;
113 BlockSet FunctionBlocks
;
115 BitVector regsReserved
;
117 RegVector regsDefined
, regsDead
, regsKilled
;
118 RegMaskVector regMasks
;
122 // Add Reg and any sub-registers to RV
123 void addRegWithSubRegs(RegVector
&RV
, unsigned Reg
) {
125 if (Register::isPhysicalRegister(Reg
))
126 for (MCSubRegIterator
SubRegs(Reg
, TRI
); SubRegs
.isValid(); ++SubRegs
)
127 RV
.push_back(*SubRegs
);
131 // Is this MBB reachable from the MF entry point?
132 bool reachable
= false;
134 // Vregs that must be live in because they are used without being
135 // defined. Map value is the user.
138 // Regs killed in MBB. They may be defined again, and will then be in both
139 // regsKilled and regsLiveOut.
142 // Regs defined in MBB and live out. Note that vregs passing through may
143 // be live out without being mentioned here.
146 // Vregs that pass through MBB untouched. This set is disjoint from
147 // regsKilled and regsLiveOut.
150 // Vregs that must pass through MBB because they are needed by a successor
151 // block. This set is disjoint from regsLiveOut.
152 RegSet vregsRequired
;
154 // Set versions of block's predecessor and successor lists.
155 BlockSet Preds
, Succs
;
159 // Add register to vregsPassed if it belongs there. Return true if
161 bool addPassed(unsigned Reg
) {
162 if (!Register::isVirtualRegister(Reg
))
164 if (regsKilled
.count(Reg
) || regsLiveOut
.count(Reg
))
166 return vregsPassed
.insert(Reg
).second
;
169 // Same for a full set.
170 bool addPassed(const RegSet
&RS
) {
171 bool changed
= false;
172 for (RegSet::const_iterator I
= RS
.begin(), E
= RS
.end(); I
!= E
; ++I
)
178 // Add register to vregsRequired if it belongs there. Return true if
180 bool addRequired(unsigned Reg
) {
181 if (!Register::isVirtualRegister(Reg
))
183 if (regsLiveOut
.count(Reg
))
185 return vregsRequired
.insert(Reg
).second
;
188 // Same for a full set.
189 bool addRequired(const RegSet
&RS
) {
190 bool changed
= false;
191 for (RegSet::const_iterator I
= RS
.begin(), E
= RS
.end(); I
!= E
; ++I
)
197 // Same for a full map.
198 bool addRequired(const RegMap
&RM
) {
199 bool changed
= false;
200 for (RegMap::const_iterator I
= RM
.begin(), E
= RM
.end(); I
!= E
; ++I
)
201 if (addRequired(I
->first
))
206 // Live-out registers are either in regsLiveOut or vregsPassed.
207 bool isLiveOut(unsigned Reg
) const {
208 return regsLiveOut
.count(Reg
) || vregsPassed
.count(Reg
);
212 // Extra register info per MBB.
213 DenseMap
<const MachineBasicBlock
*, BBInfo
> MBBInfoMap
;
215 bool isReserved(unsigned Reg
) {
216 return Reg
< regsReserved
.size() && regsReserved
.test(Reg
);
219 bool isAllocatable(unsigned Reg
) const {
220 return Reg
< TRI
->getNumRegs() && TRI
->isInAllocatableClass(Reg
) &&
221 !regsReserved
.test(Reg
);
224 // Analysis information if available
225 LiveVariables
*LiveVars
;
226 LiveIntervals
*LiveInts
;
227 LiveStacks
*LiveStks
;
228 SlotIndexes
*Indexes
;
230 void visitMachineFunctionBefore();
231 void visitMachineBasicBlockBefore(const MachineBasicBlock
*MBB
);
232 void visitMachineBundleBefore(const MachineInstr
*MI
);
234 bool verifyVectorElementMatch(LLT Ty0
, LLT Ty1
, const MachineInstr
*MI
);
235 void verifyPreISelGenericInstruction(const MachineInstr
*MI
);
236 void visitMachineInstrBefore(const MachineInstr
*MI
);
237 void visitMachineOperand(const MachineOperand
*MO
, unsigned MONum
);
238 void visitMachineInstrAfter(const MachineInstr
*MI
);
239 void visitMachineBundleAfter(const MachineInstr
*MI
);
240 void visitMachineBasicBlockAfter(const MachineBasicBlock
*MBB
);
241 void visitMachineFunctionAfter();
243 void report(const char *msg
, const MachineFunction
*MF
);
244 void report(const char *msg
, const MachineBasicBlock
*MBB
);
245 void report(const char *msg
, const MachineInstr
*MI
);
246 void report(const char *msg
, const MachineOperand
*MO
, unsigned MONum
,
247 LLT MOVRegType
= LLT
{});
249 void report_context(const LiveInterval
&LI
) const;
250 void report_context(const LiveRange
&LR
, unsigned VRegUnit
,
251 LaneBitmask LaneMask
) const;
252 void report_context(const LiveRange::Segment
&S
) const;
253 void report_context(const VNInfo
&VNI
) const;
254 void report_context(SlotIndex Pos
) const;
255 void report_context(MCPhysReg PhysReg
) const;
256 void report_context_liverange(const LiveRange
&LR
) const;
257 void report_context_lanemask(LaneBitmask LaneMask
) const;
258 void report_context_vreg(unsigned VReg
) const;
259 void report_context_vreg_regunit(unsigned VRegOrUnit
) const;
261 void verifyInlineAsm(const MachineInstr
*MI
);
263 void checkLiveness(const MachineOperand
*MO
, unsigned MONum
);
264 void checkLivenessAtUse(const MachineOperand
*MO
, unsigned MONum
,
265 SlotIndex UseIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
266 LaneBitmask LaneMask
= LaneBitmask::getNone());
267 void checkLivenessAtDef(const MachineOperand
*MO
, unsigned MONum
,
268 SlotIndex DefIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
269 bool SubRangeCheck
= false,
270 LaneBitmask LaneMask
= LaneBitmask::getNone());
272 void markReachable(const MachineBasicBlock
*MBB
);
273 void calcRegsPassed();
274 void checkPHIOps(const MachineBasicBlock
&MBB
);
276 void calcRegsRequired();
277 void verifyLiveVariables();
278 void verifyLiveIntervals();
279 void verifyLiveInterval(const LiveInterval
&);
280 void verifyLiveRangeValue(const LiveRange
&, const VNInfo
*, unsigned,
282 void verifyLiveRangeSegment(const LiveRange
&,
283 const LiveRange::const_iterator I
, unsigned,
285 void verifyLiveRange(const LiveRange
&, unsigned,
286 LaneBitmask LaneMask
= LaneBitmask::getNone());
288 void verifyStackFrame();
290 void verifySlotIndexes() const;
291 void verifyProperties(const MachineFunction
&MF
);
294 struct MachineVerifierPass
: public MachineFunctionPass
{
295 static char ID
; // Pass ID, replacement for typeid
297 const std::string Banner
;
299 MachineVerifierPass(std::string banner
= std::string())
300 : MachineFunctionPass(ID
), Banner(std::move(banner
)) {
301 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
304 void getAnalysisUsage(AnalysisUsage
&AU
) const override
{
305 AU
.setPreservesAll();
306 MachineFunctionPass::getAnalysisUsage(AU
);
309 bool runOnMachineFunction(MachineFunction
&MF
) override
{
310 unsigned FoundErrors
= MachineVerifier(this, Banner
.c_str()).verify(MF
);
312 report_fatal_error("Found "+Twine(FoundErrors
)+" machine code errors.");
317 } // end anonymous namespace
319 char MachineVerifierPass::ID
= 0;
321 INITIALIZE_PASS(MachineVerifierPass
, "machineverifier",
322 "Verify generated machine code", false, false)
324 FunctionPass
*llvm::createMachineVerifierPass(const std::string
&Banner
) {
325 return new MachineVerifierPass(Banner
);
328 bool MachineFunction::verify(Pass
*p
, const char *Banner
, bool AbortOnErrors
)
330 MachineFunction
&MF
= const_cast<MachineFunction
&>(*this);
331 unsigned FoundErrors
= MachineVerifier(p
, Banner
).verify(MF
);
332 if (AbortOnErrors
&& FoundErrors
)
333 report_fatal_error("Found "+Twine(FoundErrors
)+" machine code errors.");
334 return FoundErrors
== 0;
337 void MachineVerifier::verifySlotIndexes() const {
338 if (Indexes
== nullptr)
341 // Ensure the IdxMBB list is sorted by slot indexes.
343 for (SlotIndexes::MBBIndexIterator I
= Indexes
->MBBIndexBegin(),
344 E
= Indexes
->MBBIndexEnd(); I
!= E
; ++I
) {
345 assert(!Last
.isValid() || I
->first
> Last
);
350 void MachineVerifier::verifyProperties(const MachineFunction
&MF
) {
351 // If a pass has introduced virtual registers without clearing the
352 // NoVRegs property (or set it without allocating the vregs)
353 // then report an error.
354 if (MF
.getProperties().hasProperty(
355 MachineFunctionProperties::Property::NoVRegs
) &&
356 MRI
->getNumVirtRegs())
357 report("Function has NoVRegs property but there are VReg operands", &MF
);
360 unsigned MachineVerifier::verify(MachineFunction
&MF
) {
364 TM
= &MF
.getTarget();
365 TII
= MF
.getSubtarget().getInstrInfo();
366 TRI
= MF
.getSubtarget().getRegisterInfo();
367 MRI
= &MF
.getRegInfo();
369 const bool isFunctionFailedISel
= MF
.getProperties().hasProperty(
370 MachineFunctionProperties::Property::FailedISel
);
372 // If we're mid-GlobalISel and we already triggered the fallback path then
373 // it's expected that the MIR is somewhat broken but that's ok since we'll
374 // reset it and clear the FailedISel attribute in ResetMachineFunctions.
375 if (isFunctionFailedISel
)
378 isFunctionRegBankSelected
=
379 !isFunctionFailedISel
&&
380 MF
.getProperties().hasProperty(
381 MachineFunctionProperties::Property::RegBankSelected
);
382 isFunctionSelected
= !isFunctionFailedISel
&&
383 MF
.getProperties().hasProperty(
384 MachineFunctionProperties::Property::Selected
);
390 LiveInts
= PASS
->getAnalysisIfAvailable
<LiveIntervals
>();
391 // We don't want to verify LiveVariables if LiveIntervals is available.
393 LiveVars
= PASS
->getAnalysisIfAvailable
<LiveVariables
>();
394 LiveStks
= PASS
->getAnalysisIfAvailable
<LiveStacks
>();
395 Indexes
= PASS
->getAnalysisIfAvailable
<SlotIndexes
>();
400 verifyProperties(MF
);
402 visitMachineFunctionBefore();
403 for (MachineFunction::const_iterator MFI
= MF
.begin(), MFE
= MF
.end();
405 visitMachineBasicBlockBefore(&*MFI
);
406 // Keep track of the current bundle header.
407 const MachineInstr
*CurBundle
= nullptr;
408 // Do we expect the next instruction to be part of the same bundle?
409 bool InBundle
= false;
411 for (MachineBasicBlock::const_instr_iterator MBBI
= MFI
->instr_begin(),
412 MBBE
= MFI
->instr_end(); MBBI
!= MBBE
; ++MBBI
) {
413 if (MBBI
->getParent() != &*MFI
) {
414 report("Bad instruction parent pointer", &*MFI
);
415 errs() << "Instruction: " << *MBBI
;
419 // Check for consistent bundle flags.
420 if (InBundle
&& !MBBI
->isBundledWithPred())
421 report("Missing BundledPred flag, "
422 "BundledSucc was set on predecessor",
424 if (!InBundle
&& MBBI
->isBundledWithPred())
425 report("BundledPred flag is set, "
426 "but BundledSucc not set on predecessor",
429 // Is this a bundle header?
430 if (!MBBI
->isInsideBundle()) {
432 visitMachineBundleAfter(CurBundle
);
434 visitMachineBundleBefore(CurBundle
);
435 } else if (!CurBundle
)
436 report("No bundle header", &*MBBI
);
437 visitMachineInstrBefore(&*MBBI
);
438 for (unsigned I
= 0, E
= MBBI
->getNumOperands(); I
!= E
; ++I
) {
439 const MachineInstr
&MI
= *MBBI
;
440 const MachineOperand
&Op
= MI
.getOperand(I
);
441 if (Op
.getParent() != &MI
) {
442 // Make sure to use correct addOperand / RemoveOperand / ChangeTo
443 // functions when replacing operands of a MachineInstr.
444 report("Instruction has operand with wrong parent set", &MI
);
447 visitMachineOperand(&Op
, I
);
450 visitMachineInstrAfter(&*MBBI
);
452 // Was this the last bundled instruction?
453 InBundle
= MBBI
->isBundledWithSucc();
456 visitMachineBundleAfter(CurBundle
);
458 report("BundledSucc flag set on last instruction in block", &MFI
->back());
459 visitMachineBasicBlockAfter(&*MFI
);
461 visitMachineFunctionAfter();
474 void MachineVerifier::report(const char *msg
, const MachineFunction
*MF
) {
477 if (!foundErrors
++) {
479 errs() << "# " << Banner
<< '\n';
480 if (LiveInts
!= nullptr)
481 LiveInts
->print(errs());
483 MF
->print(errs(), Indexes
);
485 errs() << "*** Bad machine code: " << msg
<< " ***\n"
486 << "- function: " << MF
->getName() << "\n";
489 void MachineVerifier::report(const char *msg
, const MachineBasicBlock
*MBB
) {
491 report(msg
, MBB
->getParent());
492 errs() << "- basic block: " << printMBBReference(*MBB
) << ' '
493 << MBB
->getName() << " (" << (const void *)MBB
<< ')';
495 errs() << " [" << Indexes
->getMBBStartIdx(MBB
)
496 << ';' << Indexes
->getMBBEndIdx(MBB
) << ')';
500 void MachineVerifier::report(const char *msg
, const MachineInstr
*MI
) {
502 report(msg
, MI
->getParent());
503 errs() << "- instruction: ";
504 if (Indexes
&& Indexes
->hasIndex(*MI
))
505 errs() << Indexes
->getInstructionIndex(*MI
) << '\t';
506 MI
->print(errs(), /*SkipOpers=*/true);
509 void MachineVerifier::report(const char *msg
, const MachineOperand
*MO
,
510 unsigned MONum
, LLT MOVRegType
) {
512 report(msg
, MO
->getParent());
513 errs() << "- operand " << MONum
<< ": ";
514 MO
->print(errs(), MOVRegType
, TRI
);
518 void MachineVerifier::report_context(SlotIndex Pos
) const {
519 errs() << "- at: " << Pos
<< '\n';
522 void MachineVerifier::report_context(const LiveInterval
&LI
) const {
523 errs() << "- interval: " << LI
<< '\n';
526 void MachineVerifier::report_context(const LiveRange
&LR
, unsigned VRegUnit
,
527 LaneBitmask LaneMask
) const {
528 report_context_liverange(LR
);
529 report_context_vreg_regunit(VRegUnit
);
531 report_context_lanemask(LaneMask
);
534 void MachineVerifier::report_context(const LiveRange::Segment
&S
) const {
535 errs() << "- segment: " << S
<< '\n';
538 void MachineVerifier::report_context(const VNInfo
&VNI
) const {
539 errs() << "- ValNo: " << VNI
.id
<< " (def " << VNI
.def
<< ")\n";
542 void MachineVerifier::report_context_liverange(const LiveRange
&LR
) const {
543 errs() << "- liverange: " << LR
<< '\n';
546 void MachineVerifier::report_context(MCPhysReg PReg
) const {
547 errs() << "- p. register: " << printReg(PReg
, TRI
) << '\n';
550 void MachineVerifier::report_context_vreg(unsigned VReg
) const {
551 errs() << "- v. register: " << printReg(VReg
, TRI
) << '\n';
554 void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit
) const {
555 if (Register::isVirtualRegister(VRegOrUnit
)) {
556 report_context_vreg(VRegOrUnit
);
558 errs() << "- regunit: " << printRegUnit(VRegOrUnit
, TRI
) << '\n';
562 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask
) const {
563 errs() << "- lanemask: " << PrintLaneMask(LaneMask
) << '\n';
566 void MachineVerifier::markReachable(const MachineBasicBlock
*MBB
) {
567 BBInfo
&MInfo
= MBBInfoMap
[MBB
];
568 if (!MInfo
.reachable
) {
569 MInfo
.reachable
= true;
570 for (MachineBasicBlock::const_succ_iterator SuI
= MBB
->succ_begin(),
571 SuE
= MBB
->succ_end(); SuI
!= SuE
; ++SuI
)
576 void MachineVerifier::visitMachineFunctionBefore() {
577 lastIndex
= SlotIndex();
578 regsReserved
= MRI
->reservedRegsFrozen() ? MRI
->getReservedRegs()
579 : TRI
->getReservedRegs(*MF
);
582 markReachable(&MF
->front());
584 // Build a set of the basic blocks in the function.
585 FunctionBlocks
.clear();
586 for (const auto &MBB
: *MF
) {
587 FunctionBlocks
.insert(&MBB
);
588 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
590 MInfo
.Preds
.insert(MBB
.pred_begin(), MBB
.pred_end());
591 if (MInfo
.Preds
.size() != MBB
.pred_size())
592 report("MBB has duplicate entries in its predecessor list.", &MBB
);
594 MInfo
.Succs
.insert(MBB
.succ_begin(), MBB
.succ_end());
595 if (MInfo
.Succs
.size() != MBB
.succ_size())
596 report("MBB has duplicate entries in its successor list.", &MBB
);
599 // Check that the register use lists are sane.
600 MRI
->verifyUseLists();
606 // Does iterator point to a and b as the first two elements?
607 static bool matchPair(MachineBasicBlock::const_succ_iterator i
,
608 const MachineBasicBlock
*a
, const MachineBasicBlock
*b
) {
617 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock
*MBB
) {
618 FirstTerminator
= nullptr;
619 FirstNonPHI
= nullptr;
621 if (!MF
->getProperties().hasProperty(
622 MachineFunctionProperties::Property::NoPHIs
) && MRI
->tracksLiveness()) {
623 // If this block has allocatable physical registers live-in, check that
624 // it is an entry block or landing pad.
625 for (const auto &LI
: MBB
->liveins()) {
626 if (isAllocatable(LI
.PhysReg
) && !MBB
->isEHPad() &&
627 MBB
->getIterator() != MBB
->getParent()->begin()) {
628 report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB
);
629 report_context(LI
.PhysReg
);
634 // Count the number of landing pad successors.
635 SmallPtrSet
<MachineBasicBlock
*, 4> LandingPadSuccs
;
636 for (MachineBasicBlock::const_succ_iterator I
= MBB
->succ_begin(),
637 E
= MBB
->succ_end(); I
!= E
; ++I
) {
639 LandingPadSuccs
.insert(*I
);
640 if (!FunctionBlocks
.count(*I
))
641 report("MBB has successor that isn't part of the function.", MBB
);
642 if (!MBBInfoMap
[*I
].Preds
.count(MBB
)) {
643 report("Inconsistent CFG", MBB
);
644 errs() << "MBB is not in the predecessor list of the successor "
645 << printMBBReference(*(*I
)) << ".\n";
649 // Check the predecessor list.
650 for (MachineBasicBlock::const_pred_iterator I
= MBB
->pred_begin(),
651 E
= MBB
->pred_end(); I
!= E
; ++I
) {
652 if (!FunctionBlocks
.count(*I
))
653 report("MBB has predecessor that isn't part of the function.", MBB
);
654 if (!MBBInfoMap
[*I
].Succs
.count(MBB
)) {
655 report("Inconsistent CFG", MBB
);
656 errs() << "MBB is not in the successor list of the predecessor "
657 << printMBBReference(*(*I
)) << ".\n";
661 const MCAsmInfo
*AsmInfo
= TM
->getMCAsmInfo();
662 const BasicBlock
*BB
= MBB
->getBasicBlock();
663 const Function
&F
= MF
->getFunction();
664 if (LandingPadSuccs
.size() > 1 &&
666 AsmInfo
->getExceptionHandlingType() == ExceptionHandling::SjLj
&&
667 BB
&& isa
<SwitchInst
>(BB
->getTerminator())) &&
668 !isScopedEHPersonality(classifyEHPersonality(F
.getPersonalityFn())))
669 report("MBB has more than one landing pad successor", MBB
);
671 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
672 MachineBasicBlock
*TBB
= nullptr, *FBB
= nullptr;
673 SmallVector
<MachineOperand
, 4> Cond
;
674 if (!TII
->analyzeBranch(*const_cast<MachineBasicBlock
*>(MBB
), TBB
, FBB
,
676 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
677 // check whether its answers match up with reality.
679 // Block falls through to its successor.
680 MachineFunction::const_iterator MBBI
= MBB
->getIterator();
682 if (MBBI
== MF
->end()) {
683 // It's possible that the block legitimately ends with a noreturn
684 // call or an unreachable, in which case it won't actually fall
685 // out the bottom of the function.
686 } else if (MBB
->succ_size() == LandingPadSuccs
.size()) {
687 // It's possible that the block legitimately ends with a noreturn
688 // call or an unreachable, in which case it won't actually fall
690 } else if (MBB
->succ_size() != 1+LandingPadSuccs
.size()) {
691 report("MBB exits via unconditional fall-through but doesn't have "
692 "exactly one CFG successor!", MBB
);
693 } else if (!MBB
->isSuccessor(&*MBBI
)) {
694 report("MBB exits via unconditional fall-through but its successor "
695 "differs from its CFG successor!", MBB
);
697 if (!MBB
->empty() && MBB
->back().isBarrier() &&
698 !TII
->isPredicated(MBB
->back())) {
699 report("MBB exits via unconditional fall-through but ends with a "
700 "barrier instruction!", MBB
);
703 report("MBB exits via unconditional fall-through but has a condition!",
706 } else if (TBB
&& !FBB
&& Cond
.empty()) {
707 // Block unconditionally branches somewhere.
708 // If the block has exactly one successor, that happens to be a
709 // landingpad, accept it as valid control flow.
710 if (MBB
->succ_size() != 1+LandingPadSuccs
.size() &&
711 (MBB
->succ_size() != 1 || LandingPadSuccs
.size() != 1 ||
712 *MBB
->succ_begin() != *LandingPadSuccs
.begin())) {
713 report("MBB exits via unconditional branch but doesn't have "
714 "exactly one CFG successor!", MBB
);
715 } else if (!MBB
->isSuccessor(TBB
)) {
716 report("MBB exits via unconditional branch but the CFG "
717 "successor doesn't match the actual successor!", MBB
);
720 report("MBB exits via unconditional branch but doesn't contain "
721 "any instructions!", MBB
);
722 } else if (!MBB
->back().isBarrier()) {
723 report("MBB exits via unconditional branch but doesn't end with a "
724 "barrier instruction!", MBB
);
725 } else if (!MBB
->back().isTerminator()) {
726 report("MBB exits via unconditional branch but the branch isn't a "
727 "terminator instruction!", MBB
);
729 } else if (TBB
&& !FBB
&& !Cond
.empty()) {
730 // Block conditionally branches somewhere, otherwise falls through.
731 MachineFunction::const_iterator MBBI
= MBB
->getIterator();
733 if (MBBI
== MF
->end()) {
734 report("MBB conditionally falls through out of function!", MBB
);
735 } else if (MBB
->succ_size() == 1) {
736 // A conditional branch with only one successor is weird, but allowed.
738 report("MBB exits via conditional branch/fall-through but only has "
739 "one CFG successor!", MBB
);
740 else if (TBB
!= *MBB
->succ_begin())
741 report("MBB exits via conditional branch/fall-through but the CFG "
742 "successor don't match the actual successor!", MBB
);
743 } else if (MBB
->succ_size() != 2) {
744 report("MBB exits via conditional branch/fall-through but doesn't have "
745 "exactly two CFG successors!", MBB
);
746 } else if (!matchPair(MBB
->succ_begin(), TBB
, &*MBBI
)) {
747 report("MBB exits via conditional branch/fall-through but the CFG "
748 "successors don't match the actual successors!", MBB
);
751 report("MBB exits via conditional branch/fall-through but doesn't "
752 "contain any instructions!", MBB
);
753 } else if (MBB
->back().isBarrier()) {
754 report("MBB exits via conditional branch/fall-through but ends with a "
755 "barrier instruction!", MBB
);
756 } else if (!MBB
->back().isTerminator()) {
757 report("MBB exits via conditional branch/fall-through but the branch "
758 "isn't a terminator instruction!", MBB
);
760 } else if (TBB
&& FBB
) {
761 // Block conditionally branches somewhere, otherwise branches
763 if (MBB
->succ_size() == 1) {
764 // A conditional branch with only one successor is weird, but allowed.
766 report("MBB exits via conditional branch/branch through but only has "
767 "one CFG successor!", MBB
);
768 else if (TBB
!= *MBB
->succ_begin())
769 report("MBB exits via conditional branch/branch through but the CFG "
770 "successor don't match the actual successor!", MBB
);
771 } else if (MBB
->succ_size() != 2) {
772 report("MBB exits via conditional branch/branch but doesn't have "
773 "exactly two CFG successors!", MBB
);
774 } else if (!matchPair(MBB
->succ_begin(), TBB
, FBB
)) {
775 report("MBB exits via conditional branch/branch but the CFG "
776 "successors don't match the actual successors!", MBB
);
779 report("MBB exits via conditional branch/branch but doesn't "
780 "contain any instructions!", MBB
);
781 } else if (!MBB
->back().isBarrier()) {
782 report("MBB exits via conditional branch/branch but doesn't end with a "
783 "barrier instruction!", MBB
);
784 } else if (!MBB
->back().isTerminator()) {
785 report("MBB exits via conditional branch/branch but the branch "
786 "isn't a terminator instruction!", MBB
);
789 report("MBB exits via conditional branch/branch but there's no "
793 report("AnalyzeBranch returned invalid data!", MBB
);
798 if (MRI
->tracksLiveness()) {
799 for (const auto &LI
: MBB
->liveins()) {
800 if (!Register::isPhysicalRegister(LI
.PhysReg
)) {
801 report("MBB live-in list contains non-physical register", MBB
);
804 for (MCSubRegIterator
SubRegs(LI
.PhysReg
, TRI
, /*IncludeSelf=*/true);
805 SubRegs
.isValid(); ++SubRegs
)
806 regsLive
.insert(*SubRegs
);
810 const MachineFrameInfo
&MFI
= MF
->getFrameInfo();
811 BitVector PR
= MFI
.getPristineRegs(*MF
);
812 for (unsigned I
: PR
.set_bits()) {
813 for (MCSubRegIterator
SubRegs(I
, TRI
, /*IncludeSelf=*/true);
814 SubRegs
.isValid(); ++SubRegs
)
815 regsLive
.insert(*SubRegs
);
822 lastIndex
= Indexes
->getMBBStartIdx(MBB
);
825 // This function gets called for all bundle headers, including normal
826 // stand-alone unbundled instructions.
827 void MachineVerifier::visitMachineBundleBefore(const MachineInstr
*MI
) {
828 if (Indexes
&& Indexes
->hasIndex(*MI
)) {
829 SlotIndex idx
= Indexes
->getInstructionIndex(*MI
);
830 if (!(idx
> lastIndex
)) {
831 report("Instruction index out of order", MI
);
832 errs() << "Last instruction was at " << lastIndex
<< '\n';
837 // Ensure non-terminators don't follow terminators.
838 // Ignore predicated terminators formed by if conversion.
839 // FIXME: If conversion shouldn't need to violate this rule.
840 if (MI
->isTerminator() && !TII
->isPredicated(*MI
)) {
841 if (!FirstTerminator
)
842 FirstTerminator
= MI
;
843 } else if (FirstTerminator
&& !MI
->isDebugEntryValue()) {
844 report("Non-terminator instruction after the first terminator", MI
);
845 errs() << "First terminator was:\t" << *FirstTerminator
;
849 // The operands on an INLINEASM instruction must follow a template.
850 // Verify that the flag operands make sense.
851 void MachineVerifier::verifyInlineAsm(const MachineInstr
*MI
) {
852 // The first two operands on INLINEASM are the asm string and global flags.
853 if (MI
->getNumOperands() < 2) {
854 report("Too few operands on inline asm", MI
);
857 if (!MI
->getOperand(0).isSymbol())
858 report("Asm string must be an external symbol", MI
);
859 if (!MI
->getOperand(1).isImm())
860 report("Asm flags must be an immediate", MI
);
861 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
862 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
863 // and Extra_IsConvergent = 32.
864 if (!isUInt
<6>(MI
->getOperand(1).getImm()))
865 report("Unknown asm flags", &MI
->getOperand(1), 1);
867 static_assert(InlineAsm::MIOp_FirstOperand
== 2, "Asm format changed");
869 unsigned OpNo
= InlineAsm::MIOp_FirstOperand
;
871 for (unsigned e
= MI
->getNumOperands(); OpNo
< e
; OpNo
+= NumOps
) {
872 const MachineOperand
&MO
= MI
->getOperand(OpNo
);
873 // There may be implicit ops after the fixed operands.
876 NumOps
= 1 + InlineAsm::getNumOperandRegisters(MO
.getImm());
879 if (OpNo
> MI
->getNumOperands())
880 report("Missing operands in last group", MI
);
882 // An optional MDNode follows the groups.
883 if (OpNo
< MI
->getNumOperands() && MI
->getOperand(OpNo
).isMetadata())
886 // All trailing operands must be implicit registers.
887 for (unsigned e
= MI
->getNumOperands(); OpNo
< e
; ++OpNo
) {
888 const MachineOperand
&MO
= MI
->getOperand(OpNo
);
889 if (!MO
.isReg() || !MO
.isImplicit())
890 report("Expected implicit register after groups", &MO
, OpNo
);
894 /// Check that types are consistent when two operands need to have the same
895 /// number of vector elements.
896 /// \return true if the types are valid.
897 bool MachineVerifier::verifyVectorElementMatch(LLT Ty0
, LLT Ty1
,
898 const MachineInstr
*MI
) {
899 if (Ty0
.isVector() != Ty1
.isVector()) {
900 report("operand types must be all-vector or all-scalar", MI
);
901 // Generally we try to report as many issues as possible at once, but in
902 // this case it's not clear what should we be comparing the size of the
903 // scalar with: the size of the whole vector or its lane. Instead of
904 // making an arbitrary choice and emitting not so helpful message, let's
905 // avoid the extra noise and stop here.
909 if (Ty0
.isVector() && Ty0
.getNumElements() != Ty1
.getNumElements()) {
910 report("operand types must preserve number of vector elements", MI
);
917 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr
*MI
) {
918 if (isFunctionSelected
)
919 report("Unexpected generic instruction in a Selected function", MI
);
921 const MCInstrDesc
&MCID
= MI
->getDesc();
922 unsigned NumOps
= MI
->getNumOperands();
925 SmallVector
<LLT
, 4> Types
;
926 for (unsigned I
= 0, E
= std::min(MCID
.getNumOperands(), NumOps
);
928 if (!MCID
.OpInfo
[I
].isGenericType())
930 // Generic instructions specify type equality constraints between some of
931 // their operands. Make sure these are consistent.
932 size_t TypeIdx
= MCID
.OpInfo
[I
].getGenericTypeIndex();
933 Types
.resize(std::max(TypeIdx
+ 1, Types
.size()));
935 const MachineOperand
*MO
= &MI
->getOperand(I
);
937 report("generic instruction must use register operands", MI
);
941 LLT OpTy
= MRI
->getType(MO
->getReg());
942 // Don't report a type mismatch if there is no actual mismatch, only a
943 // type missing, to reduce noise:
944 if (OpTy
.isValid()) {
945 // Only the first valid type for a type index will be printed: don't
946 // overwrite it later so it's always clear which type was expected:
947 if (!Types
[TypeIdx
].isValid())
948 Types
[TypeIdx
] = OpTy
;
949 else if (Types
[TypeIdx
] != OpTy
)
950 report("Type mismatch in generic instruction", MO
, I
, OpTy
);
952 // Generic instructions must have types attached to their operands.
953 report("Generic instruction is missing a virtual register type", MO
, I
);
957 // Generic opcodes must not have physical register operands.
958 for (unsigned I
= 0; I
< MI
->getNumOperands(); ++I
) {
959 const MachineOperand
*MO
= &MI
->getOperand(I
);
960 if (MO
->isReg() && Register::isPhysicalRegister(MO
->getReg()))
961 report("Generic instruction cannot have physical register", MO
, I
);
964 // Avoid out of bounds in checks below. This was already reported earlier.
965 if (MI
->getNumOperands() < MCID
.getNumOperands())
969 if (!TII
->verifyInstruction(*MI
, ErrorInfo
))
970 report(ErrorInfo
.data(), MI
);
972 // Verify properties of various specific instruction types
973 switch (MI
->getOpcode()) {
974 case TargetOpcode::G_CONSTANT
:
975 case TargetOpcode::G_FCONSTANT
: {
976 if (MI
->getNumOperands() < MCID
.getNumOperands())
979 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
980 if (DstTy
.isVector())
981 report("Instruction cannot use a vector result type", MI
);
983 if (MI
->getOpcode() == TargetOpcode::G_CONSTANT
) {
984 if (!MI
->getOperand(1).isCImm()) {
985 report("G_CONSTANT operand must be cimm", MI
);
989 const ConstantInt
*CI
= MI
->getOperand(1).getCImm();
990 if (CI
->getBitWidth() != DstTy
.getSizeInBits())
991 report("inconsistent constant size", MI
);
993 if (!MI
->getOperand(1).isFPImm()) {
994 report("G_FCONSTANT operand must be fpimm", MI
);
997 const ConstantFP
*CF
= MI
->getOperand(1).getFPImm();
999 if (APFloat::getSizeInBits(CF
->getValueAPF().getSemantics()) !=
1000 DstTy
.getSizeInBits()) {
1001 report("inconsistent constant size", MI
);
1007 case TargetOpcode::G_LOAD
:
1008 case TargetOpcode::G_STORE
:
1009 case TargetOpcode::G_ZEXTLOAD
:
1010 case TargetOpcode::G_SEXTLOAD
: {
1011 LLT ValTy
= MRI
->getType(MI
->getOperand(0).getReg());
1012 LLT PtrTy
= MRI
->getType(MI
->getOperand(1).getReg());
1013 if (!PtrTy
.isPointer())
1014 report("Generic memory instruction must access a pointer", MI
);
1016 // Generic loads and stores must have a single MachineMemOperand
1017 // describing that access.
1018 if (!MI
->hasOneMemOperand()) {
1019 report("Generic instruction accessing memory must have one mem operand",
1022 const MachineMemOperand
&MMO
= **MI
->memoperands_begin();
1023 if (MI
->getOpcode() == TargetOpcode::G_ZEXTLOAD
||
1024 MI
->getOpcode() == TargetOpcode::G_SEXTLOAD
) {
1025 if (MMO
.getSizeInBits() >= ValTy
.getSizeInBits())
1026 report("Generic extload must have a narrower memory type", MI
);
1027 } else if (MI
->getOpcode() == TargetOpcode::G_LOAD
) {
1028 if (MMO
.getSize() > ValTy
.getSizeInBytes())
1029 report("load memory size cannot exceed result size", MI
);
1030 } else if (MI
->getOpcode() == TargetOpcode::G_STORE
) {
1031 if (ValTy
.getSizeInBytes() < MMO
.getSize())
1032 report("store memory size cannot exceed value size", MI
);
1038 case TargetOpcode::G_PHI
: {
1039 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1040 if (!DstTy
.isValid() ||
1041 !std::all_of(MI
->operands_begin() + 1, MI
->operands_end(),
1042 [this, &DstTy
](const MachineOperand
&MO
) {
1045 LLT Ty
= MRI
->getType(MO
.getReg());
1046 if (!Ty
.isValid() || (Ty
!= DstTy
))
1050 report("Generic Instruction G_PHI has operands with incompatible/missing "
1055 case TargetOpcode::G_BITCAST
: {
1056 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1057 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1058 if (!DstTy
.isValid() || !SrcTy
.isValid())
1061 if (SrcTy
.isPointer() != DstTy
.isPointer())
1062 report("bitcast cannot convert between pointers and other types", MI
);
1064 if (SrcTy
.getSizeInBits() != DstTy
.getSizeInBits())
1065 report("bitcast sizes must match", MI
);
1068 case TargetOpcode::G_INTTOPTR
:
1069 case TargetOpcode::G_PTRTOINT
:
1070 case TargetOpcode::G_ADDRSPACE_CAST
: {
1071 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1072 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1073 if (!DstTy
.isValid() || !SrcTy
.isValid())
1076 verifyVectorElementMatch(DstTy
, SrcTy
, MI
);
1078 DstTy
= DstTy
.getScalarType();
1079 SrcTy
= SrcTy
.getScalarType();
1081 if (MI
->getOpcode() == TargetOpcode::G_INTTOPTR
) {
1082 if (!DstTy
.isPointer())
1083 report("inttoptr result type must be a pointer", MI
);
1084 if (SrcTy
.isPointer())
1085 report("inttoptr source type must not be a pointer", MI
);
1086 } else if (MI
->getOpcode() == TargetOpcode::G_PTRTOINT
) {
1087 if (!SrcTy
.isPointer())
1088 report("ptrtoint source type must be a pointer", MI
);
1089 if (DstTy
.isPointer())
1090 report("ptrtoint result type must not be a pointer", MI
);
1092 assert(MI
->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST
);
1093 if (!SrcTy
.isPointer() || !DstTy
.isPointer())
1094 report("addrspacecast types must be pointers", MI
);
1096 if (SrcTy
.getAddressSpace() == DstTy
.getAddressSpace())
1097 report("addrspacecast must convert different address spaces", MI
);
1103 case TargetOpcode::G_GEP
: {
1104 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1105 LLT PtrTy
= MRI
->getType(MI
->getOperand(1).getReg());
1106 LLT OffsetTy
= MRI
->getType(MI
->getOperand(2).getReg());
1107 if (!DstTy
.isValid() || !PtrTy
.isValid() || !OffsetTy
.isValid())
1110 if (!PtrTy
.getScalarType().isPointer())
1111 report("gep first operand must be a pointer", MI
);
1113 if (OffsetTy
.getScalarType().isPointer())
1114 report("gep offset operand must not be a pointer", MI
);
1116 // TODO: Is the offset allowed to be a scalar with a vector?
1119 case TargetOpcode::G_SEXT
:
1120 case TargetOpcode::G_ZEXT
:
1121 case TargetOpcode::G_ANYEXT
:
1122 case TargetOpcode::G_TRUNC
:
1123 case TargetOpcode::G_FPEXT
:
1124 case TargetOpcode::G_FPTRUNC
: {
1125 // Number of operands and presense of types is already checked (and
1126 // reported in case of any issues), so no need to report them again. As
1127 // we're trying to report as many issues as possible at once, however, the
1128 // instructions aren't guaranteed to have the right number of operands or
1129 // types attached to them at this point
1130 assert(MCID
.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}");
1131 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1132 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1133 if (!DstTy
.isValid() || !SrcTy
.isValid())
1136 LLT DstElTy
= DstTy
.getScalarType();
1137 LLT SrcElTy
= SrcTy
.getScalarType();
1138 if (DstElTy
.isPointer() || SrcElTy
.isPointer())
1139 report("Generic extend/truncate can not operate on pointers", MI
);
1141 verifyVectorElementMatch(DstTy
, SrcTy
, MI
);
1143 unsigned DstSize
= DstElTy
.getSizeInBits();
1144 unsigned SrcSize
= SrcElTy
.getSizeInBits();
1145 switch (MI
->getOpcode()) {
1147 if (DstSize
<= SrcSize
)
1148 report("Generic extend has destination type no larger than source", MI
);
1150 case TargetOpcode::G_TRUNC
:
1151 case TargetOpcode::G_FPTRUNC
:
1152 if (DstSize
>= SrcSize
)
1153 report("Generic truncate has destination type no smaller than source",
1159 case TargetOpcode::G_SELECT
: {
1160 LLT SelTy
= MRI
->getType(MI
->getOperand(0).getReg());
1161 LLT CondTy
= MRI
->getType(MI
->getOperand(1).getReg());
1162 if (!SelTy
.isValid() || !CondTy
.isValid())
1165 // Scalar condition select on a vector is valid.
1166 if (CondTy
.isVector())
1167 verifyVectorElementMatch(SelTy
, CondTy
, MI
);
1170 case TargetOpcode::G_MERGE_VALUES
: {
1171 // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1172 // e.g. s2N = MERGE sN, sN
1173 // Merging multiple scalars into a vector is not allowed, should use
1174 // G_BUILD_VECTOR for that.
1175 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1176 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1177 if (DstTy
.isVector() || SrcTy
.isVector())
1178 report("G_MERGE_VALUES cannot operate on vectors", MI
);
1180 const unsigned NumOps
= MI
->getNumOperands();
1181 if (DstTy
.getSizeInBits() != SrcTy
.getSizeInBits() * (NumOps
- 1))
1182 report("G_MERGE_VALUES result size is inconsistent", MI
);
1184 for (unsigned I
= 2; I
!= NumOps
; ++I
) {
1185 if (MRI
->getType(MI
->getOperand(I
).getReg()) != SrcTy
)
1186 report("G_MERGE_VALUES source types do not match", MI
);
1191 case TargetOpcode::G_UNMERGE_VALUES
: {
1192 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1193 LLT SrcTy
= MRI
->getType(MI
->getOperand(MI
->getNumOperands()-1).getReg());
1194 // For now G_UNMERGE can split vectors.
1195 for (unsigned i
= 0; i
< MI
->getNumOperands()-1; ++i
) {
1196 if (MRI
->getType(MI
->getOperand(i
).getReg()) != DstTy
)
1197 report("G_UNMERGE_VALUES destination types do not match", MI
);
1199 if (SrcTy
.getSizeInBits() !=
1200 (DstTy
.getSizeInBits() * (MI
->getNumOperands() - 1))) {
1201 report("G_UNMERGE_VALUES source operand does not cover dest operands",
1206 case TargetOpcode::G_BUILD_VECTOR
: {
1207 // Source types must be scalars, dest type a vector. Total size of scalars
1208 // must match the dest vector size.
1209 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1210 LLT SrcEltTy
= MRI
->getType(MI
->getOperand(1).getReg());
1211 if (!DstTy
.isVector() || SrcEltTy
.isVector()) {
1212 report("G_BUILD_VECTOR must produce a vector from scalar operands", MI
);
1216 if (DstTy
.getElementType() != SrcEltTy
)
1217 report("G_BUILD_VECTOR result element type must match source type", MI
);
1219 if (DstTy
.getNumElements() != MI
->getNumOperands() - 1)
1220 report("G_BUILD_VECTOR must have an operand for each elemement", MI
);
1222 for (unsigned i
= 2; i
< MI
->getNumOperands(); ++i
) {
1223 if (MRI
->getType(MI
->getOperand(1).getReg()) !=
1224 MRI
->getType(MI
->getOperand(i
).getReg()))
1225 report("G_BUILD_VECTOR source operand types are not homogeneous", MI
);
1230 case TargetOpcode::G_BUILD_VECTOR_TRUNC
: {
1231 // Source types must be scalars, dest type a vector. Scalar types must be
1232 // larger than the dest vector elt type, as this is a truncating operation.
1233 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1234 LLT SrcEltTy
= MRI
->getType(MI
->getOperand(1).getReg());
1235 if (!DstTy
.isVector() || SrcEltTy
.isVector())
1236 report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1238 for (unsigned i
= 2; i
< MI
->getNumOperands(); ++i
) {
1239 if (MRI
->getType(MI
->getOperand(1).getReg()) !=
1240 MRI
->getType(MI
->getOperand(i
).getReg()))
1241 report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1244 if (SrcEltTy
.getSizeInBits() <= DstTy
.getElementType().getSizeInBits())
1245 report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1250 case TargetOpcode::G_CONCAT_VECTORS
: {
1251 // Source types should be vectors, and total size should match the dest
1253 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1254 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1255 if (!DstTy
.isVector() || !SrcTy
.isVector())
1256 report("G_CONCAT_VECTOR requires vector source and destination operands",
1258 for (unsigned i
= 2; i
< MI
->getNumOperands(); ++i
) {
1259 if (MRI
->getType(MI
->getOperand(1).getReg()) !=
1260 MRI
->getType(MI
->getOperand(i
).getReg()))
1261 report("G_CONCAT_VECTOR source operand types are not homogeneous", MI
);
1263 if (DstTy
.getNumElements() !=
1264 SrcTy
.getNumElements() * (MI
->getNumOperands() - 1))
1265 report("G_CONCAT_VECTOR num dest and source elements should match", MI
);
1268 case TargetOpcode::G_ICMP
:
1269 case TargetOpcode::G_FCMP
: {
1270 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1271 LLT SrcTy
= MRI
->getType(MI
->getOperand(2).getReg());
1273 if ((DstTy
.isVector() != SrcTy
.isVector()) ||
1274 (DstTy
.isVector() && DstTy
.getNumElements() != SrcTy
.getNumElements()))
1275 report("Generic vector icmp/fcmp must preserve number of lanes", MI
);
1279 case TargetOpcode::G_EXTRACT
: {
1280 const MachineOperand
&SrcOp
= MI
->getOperand(1);
1281 if (!SrcOp
.isReg()) {
1282 report("extract source must be a register", MI
);
1286 const MachineOperand
&OffsetOp
= MI
->getOperand(2);
1287 if (!OffsetOp
.isImm()) {
1288 report("extract offset must be a constant", MI
);
1292 unsigned DstSize
= MRI
->getType(MI
->getOperand(0).getReg()).getSizeInBits();
1293 unsigned SrcSize
= MRI
->getType(SrcOp
.getReg()).getSizeInBits();
1294 if (SrcSize
== DstSize
)
1295 report("extract source must be larger than result", MI
);
1297 if (DstSize
+ OffsetOp
.getImm() > SrcSize
)
1298 report("extract reads past end of register", MI
);
1301 case TargetOpcode::G_INSERT
: {
1302 const MachineOperand
&SrcOp
= MI
->getOperand(2);
1303 if (!SrcOp
.isReg()) {
1304 report("insert source must be a register", MI
);
1308 const MachineOperand
&OffsetOp
= MI
->getOperand(3);
1309 if (!OffsetOp
.isImm()) {
1310 report("insert offset must be a constant", MI
);
1314 unsigned DstSize
= MRI
->getType(MI
->getOperand(0).getReg()).getSizeInBits();
1315 unsigned SrcSize
= MRI
->getType(SrcOp
.getReg()).getSizeInBits();
1317 if (DstSize
<= SrcSize
)
1318 report("inserted size must be smaller than total register", MI
);
1320 if (SrcSize
+ OffsetOp
.getImm() > DstSize
)
1321 report("insert writes past end of register", MI
);
1325 case TargetOpcode::G_JUMP_TABLE
: {
1326 if (!MI
->getOperand(1).isJTI())
1327 report("G_JUMP_TABLE source operand must be a jump table index", MI
);
1328 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1329 if (!DstTy
.isPointer())
1330 report("G_JUMP_TABLE dest operand must have a pointer type", MI
);
1333 case TargetOpcode::G_BRJT
: {
1334 if (!MRI
->getType(MI
->getOperand(0).getReg()).isPointer())
1335 report("G_BRJT src operand 0 must be a pointer type", MI
);
1337 if (!MI
->getOperand(1).isJTI())
1338 report("G_BRJT src operand 1 must be a jump table index", MI
);
1340 const auto &IdxOp
= MI
->getOperand(2);
1341 if (!IdxOp
.isReg() || MRI
->getType(IdxOp
.getReg()).isPointer())
1342 report("G_BRJT src operand 2 must be a scalar reg type", MI
);
1345 case TargetOpcode::G_INTRINSIC
:
1346 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
: {
1347 // TODO: Should verify number of def and use operands, but the current
1348 // interface requires passing in IR types for mangling.
1349 const MachineOperand
&IntrIDOp
= MI
->getOperand(MI
->getNumExplicitDefs());
1350 if (!IntrIDOp
.isIntrinsicID()) {
1351 report("G_INTRINSIC first src operand must be an intrinsic ID", MI
);
1355 bool NoSideEffects
= MI
->getOpcode() == TargetOpcode::G_INTRINSIC
;
1356 unsigned IntrID
= IntrIDOp
.getIntrinsicID();
1357 if (IntrID
!= 0 && IntrID
< Intrinsic::num_intrinsics
) {
1359 = Intrinsic::getAttributes(MF
->getFunction().getContext(),
1360 static_cast<Intrinsic::ID
>(IntrID
));
1361 bool DeclHasSideEffects
= !Attrs
.hasFnAttribute(Attribute::ReadNone
);
1362 if (NoSideEffects
&& DeclHasSideEffects
) {
1363 report("G_INTRINSIC used with intrinsic that accesses memory", MI
);
1366 if (!NoSideEffects
&& !DeclHasSideEffects
) {
1367 report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI
);
1372 case Intrinsic::memcpy
:
1373 if (MI
->getNumOperands() != 5)
1374 report("Expected memcpy intrinsic to have 5 operands", MI
);
1376 case Intrinsic::memmove
:
1377 if (MI
->getNumOperands() != 5)
1378 report("Expected memmove intrinsic to have 5 operands", MI
);
1380 case Intrinsic::memset
:
1381 if (MI
->getNumOperands() != 5)
1382 report("Expected memset intrinsic to have 5 operands", MI
);
1387 case TargetOpcode::G_SEXT_INREG
: {
1388 if (!MI
->getOperand(2).isImm()) {
1389 report("G_SEXT_INREG expects an immediate operand #2", MI
);
1393 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1394 LLT SrcTy
= MRI
->getType(MI
->getOperand(1).getReg());
1395 verifyVectorElementMatch(DstTy
, SrcTy
, MI
);
1397 int64_t Imm
= MI
->getOperand(2).getImm();
1399 report("G_SEXT_INREG size must be >= 1", MI
);
1400 if (Imm
>= SrcTy
.getScalarSizeInBits())
1401 report("G_SEXT_INREG size must be less than source bit width", MI
);
1404 case TargetOpcode::G_SHUFFLE_VECTOR
: {
1405 const MachineOperand
&MaskOp
= MI
->getOperand(3);
1406 if (!MaskOp
.isShuffleMask()) {
1407 report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI
);
1411 const Constant
*Mask
= MaskOp
.getShuffleMask();
1412 auto *MaskVT
= dyn_cast
<VectorType
>(Mask
->getType());
1413 if (!MaskVT
|| !MaskVT
->getElementType()->isIntegerTy(32)) {
1414 report("Invalid shufflemask constant type", MI
);
1418 if (!Mask
->getAggregateElement(0u)) {
1419 report("Invalid shufflemask constant type", MI
);
1423 LLT DstTy
= MRI
->getType(MI
->getOperand(0).getReg());
1424 LLT Src0Ty
= MRI
->getType(MI
->getOperand(1).getReg());
1425 LLT Src1Ty
= MRI
->getType(MI
->getOperand(2).getReg());
1427 if (Src0Ty
!= Src1Ty
)
1428 report("Source operands must be the same type", MI
);
1430 if (Src0Ty
.getScalarType() != DstTy
.getScalarType())
1431 report("G_SHUFFLE_VECTOR cannot change element type", MI
);
1433 // Don't check that all operands are vector because scalars are used in
1434 // place of 1 element vectors.
1435 int SrcNumElts
= Src0Ty
.isVector() ? Src0Ty
.getNumElements() : 1;
1436 int DstNumElts
= DstTy
.isVector() ? DstTy
.getNumElements() : 1;
1438 SmallVector
<int, 32> MaskIdxes
;
1439 ShuffleVectorInst::getShuffleMask(Mask
, MaskIdxes
);
1441 if (static_cast<int>(MaskIdxes
.size()) != DstNumElts
)
1442 report("Wrong result type for shufflemask", MI
);
1444 for (int Idx
: MaskIdxes
) {
1448 if (Idx
>= 2 * SrcNumElts
)
1449 report("Out of bounds shuffle index", MI
);
1454 case TargetOpcode::G_DYN_STACKALLOC
: {
1455 const MachineOperand
&DstOp
= MI
->getOperand(0);
1456 const MachineOperand
&AllocOp
= MI
->getOperand(1);
1457 const MachineOperand
&AlignOp
= MI
->getOperand(2);
1459 if (!DstOp
.isReg() || !MRI
->getType(DstOp
.getReg()).isPointer()) {
1460 report("dst operand 0 must be a pointer type", MI
);
1464 if (!AllocOp
.isReg() || !MRI
->getType(AllocOp
.getReg()).isScalar()) {
1465 report("src operand 1 must be a scalar reg type", MI
);
1469 if (!AlignOp
.isImm()) {
1470 report("src operand 2 must be an immediate type", MI
);
1480 void MachineVerifier::visitMachineInstrBefore(const MachineInstr
*MI
) {
1481 const MCInstrDesc
&MCID
= MI
->getDesc();
1482 if (MI
->getNumOperands() < MCID
.getNumOperands()) {
1483 report("Too few operands", MI
);
1484 errs() << MCID
.getNumOperands() << " operands expected, but "
1485 << MI
->getNumOperands() << " given.\n";
1489 if (MF
->getProperties().hasProperty(
1490 MachineFunctionProperties::Property::NoPHIs
))
1491 report("Found PHI instruction with NoPHIs property set", MI
);
1494 report("Found PHI instruction after non-PHI", MI
);
1495 } else if (FirstNonPHI
== nullptr)
1498 // Check the tied operands.
1499 if (MI
->isInlineAsm())
1500 verifyInlineAsm(MI
);
1502 // Check the MachineMemOperands for basic consistency.
1503 for (MachineInstr::mmo_iterator I
= MI
->memoperands_begin(),
1504 E
= MI
->memoperands_end();
1506 if ((*I
)->isLoad() && !MI
->mayLoad())
1507 report("Missing mayLoad flag", MI
);
1508 if ((*I
)->isStore() && !MI
->mayStore())
1509 report("Missing mayStore flag", MI
);
1512 // Debug values must not have a slot index.
1513 // Other instructions must have one, unless they are inside a bundle.
1515 bool mapped
= !LiveInts
->isNotInMIMap(*MI
);
1516 if (MI
->isDebugInstr()) {
1518 report("Debug instruction has a slot index", MI
);
1519 } else if (MI
->isInsideBundle()) {
1521 report("Instruction inside bundle has a slot index", MI
);
1524 report("Missing slot index", MI
);
1528 if (isPreISelGenericOpcode(MCID
.getOpcode())) {
1529 verifyPreISelGenericInstruction(MI
);
1533 StringRef ErrorInfo
;
1534 if (!TII
->verifyInstruction(*MI
, ErrorInfo
))
1535 report(ErrorInfo
.data(), MI
);
1537 // Verify properties of various specific instruction types
1538 switch (MI
->getOpcode()) {
1539 case TargetOpcode::COPY
: {
1542 const MachineOperand
&DstOp
= MI
->getOperand(0);
1543 const MachineOperand
&SrcOp
= MI
->getOperand(1);
1544 LLT DstTy
= MRI
->getType(DstOp
.getReg());
1545 LLT SrcTy
= MRI
->getType(SrcOp
.getReg());
1546 if (SrcTy
.isValid() && DstTy
.isValid()) {
1547 // If both types are valid, check that the types are the same.
1548 if (SrcTy
!= DstTy
) {
1549 report("Copy Instruction is illegal with mismatching types", MI
);
1550 errs() << "Def = " << DstTy
<< ", Src = " << SrcTy
<< "\n";
1553 if (SrcTy
.isValid() || DstTy
.isValid()) {
1554 // If one of them have valid types, let's just check they have the same
1556 unsigned SrcSize
= TRI
->getRegSizeInBits(SrcOp
.getReg(), *MRI
);
1557 unsigned DstSize
= TRI
->getRegSizeInBits(DstOp
.getReg(), *MRI
);
1558 assert(SrcSize
&& "Expecting size here");
1559 assert(DstSize
&& "Expecting size here");
1560 if (SrcSize
!= DstSize
)
1561 if (!DstOp
.getSubReg() && !SrcOp
.getSubReg()) {
1562 report("Copy Instruction is illegal with mismatching sizes", MI
);
1563 errs() << "Def Size = " << DstSize
<< ", Src Size = " << SrcSize
1569 case TargetOpcode::STATEPOINT
:
1570 if (!MI
->getOperand(StatepointOpers::IDPos
).isImm() ||
1571 !MI
->getOperand(StatepointOpers::NBytesPos
).isImm() ||
1572 !MI
->getOperand(StatepointOpers::NCallArgsPos
).isImm())
1573 report("meta operands to STATEPOINT not constant!", MI
);
1576 auto VerifyStackMapConstant
= [&](unsigned Offset
) {
1577 if (!MI
->getOperand(Offset
).isImm() ||
1578 MI
->getOperand(Offset
).getImm() != StackMaps::ConstantOp
||
1579 !MI
->getOperand(Offset
+ 1).isImm())
1580 report("stack map constant to STATEPOINT not well formed!", MI
);
1582 const unsigned VarStart
= StatepointOpers(MI
).getVarIdx();
1583 VerifyStackMapConstant(VarStart
+ StatepointOpers::CCOffset
);
1584 VerifyStackMapConstant(VarStart
+ StatepointOpers::FlagsOffset
);
1585 VerifyStackMapConstant(VarStart
+ StatepointOpers::NumDeoptOperandsOffset
);
1587 // TODO: verify we have properly encoded deopt arguments
1593 MachineVerifier::visitMachineOperand(const MachineOperand
*MO
, unsigned MONum
) {
1594 const MachineInstr
*MI
= MO
->getParent();
1595 const MCInstrDesc
&MCID
= MI
->getDesc();
1596 unsigned NumDefs
= MCID
.getNumDefs();
1597 if (MCID
.getOpcode() == TargetOpcode::PATCHPOINT
)
1598 NumDefs
= (MONum
== 0 && MO
->isReg()) ? NumDefs
: 0;
1600 // The first MCID.NumDefs operands must be explicit register defines
1601 if (MONum
< NumDefs
) {
1602 const MCOperandInfo
&MCOI
= MCID
.OpInfo
[MONum
];
1604 report("Explicit definition must be a register", MO
, MONum
);
1605 else if (!MO
->isDef() && !MCOI
.isOptionalDef())
1606 report("Explicit definition marked as use", MO
, MONum
);
1607 else if (MO
->isImplicit())
1608 report("Explicit definition marked as implicit", MO
, MONum
);
1609 } else if (MONum
< MCID
.getNumOperands()) {
1610 const MCOperandInfo
&MCOI
= MCID
.OpInfo
[MONum
];
1611 // Don't check if it's the last operand in a variadic instruction. See,
1612 // e.g., LDM_RET in the arm back end.
1614 !(MI
->isVariadic() && MONum
== MCID
.getNumOperands()-1)) {
1615 if (MO
->isDef() && !MCOI
.isOptionalDef())
1616 report("Explicit operand marked as def", MO
, MONum
);
1617 if (MO
->isImplicit())
1618 report("Explicit operand marked as implicit", MO
, MONum
);
1621 int TiedTo
= MCID
.getOperandConstraint(MONum
, MCOI::TIED_TO
);
1624 report("Tied use must be a register", MO
, MONum
);
1625 else if (!MO
->isTied())
1626 report("Operand should be tied", MO
, MONum
);
1627 else if (unsigned(TiedTo
) != MI
->findTiedOperandIdx(MONum
))
1628 report("Tied def doesn't match MCInstrDesc", MO
, MONum
);
1629 else if (Register::isPhysicalRegister(MO
->getReg())) {
1630 const MachineOperand
&MOTied
= MI
->getOperand(TiedTo
);
1631 if (!MOTied
.isReg())
1632 report("Tied counterpart must be a register", &MOTied
, TiedTo
);
1633 else if (Register::isPhysicalRegister(MOTied
.getReg()) &&
1634 MO
->getReg() != MOTied
.getReg())
1635 report("Tied physical registers must match.", &MOTied
, TiedTo
);
1637 } else if (MO
->isReg() && MO
->isTied())
1638 report("Explicit operand should not be tied", MO
, MONum
);
1640 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1641 if (MO
->isReg() && !MO
->isImplicit() && !MI
->isVariadic() && MO
->getReg())
1642 report("Extra explicit operand on non-variadic instruction", MO
, MONum
);
1645 switch (MO
->getType()) {
1646 case MachineOperand::MO_Register
: {
1647 const Register Reg
= MO
->getReg();
1650 if (MRI
->tracksLiveness() && !MI
->isDebugValue())
1651 checkLiveness(MO
, MONum
);
1653 // Verify the consistency of tied operands.
1655 unsigned OtherIdx
= MI
->findTiedOperandIdx(MONum
);
1656 const MachineOperand
&OtherMO
= MI
->getOperand(OtherIdx
);
1657 if (!OtherMO
.isReg())
1658 report("Must be tied to a register", MO
, MONum
);
1659 if (!OtherMO
.isTied())
1660 report("Missing tie flags on tied operand", MO
, MONum
);
1661 if (MI
->findTiedOperandIdx(OtherIdx
) != MONum
)
1662 report("Inconsistent tie links", MO
, MONum
);
1663 if (MONum
< MCID
.getNumDefs()) {
1664 if (OtherIdx
< MCID
.getNumOperands()) {
1665 if (-1 == MCID
.getOperandConstraint(OtherIdx
, MCOI::TIED_TO
))
1666 report("Explicit def tied to explicit use without tie constraint",
1669 if (!OtherMO
.isImplicit())
1670 report("Explicit def should be tied to implicit use", MO
, MONum
);
1675 // Verify two-address constraints after leaving SSA form.
1677 if (!MRI
->isSSA() && MO
->isUse() &&
1678 MI
->isRegTiedToDefOperand(MONum
, &DefIdx
) &&
1679 Reg
!= MI
->getOperand(DefIdx
).getReg())
1680 report("Two-address instruction operands must be identical", MO
, MONum
);
1682 // Check register classes.
1683 unsigned SubIdx
= MO
->getSubReg();
1685 if (Register::isPhysicalRegister(Reg
)) {
1687 report("Illegal subregister index for physical register", MO
, MONum
);
1690 if (MONum
< MCID
.getNumOperands()) {
1691 if (const TargetRegisterClass
*DRC
=
1692 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
)) {
1693 if (!DRC
->contains(Reg
)) {
1694 report("Illegal physical register for instruction", MO
, MONum
);
1695 errs() << printReg(Reg
, TRI
) << " is not a "
1696 << TRI
->getRegClassName(DRC
) << " register.\n";
1700 if (MO
->isRenamable()) {
1701 if (MRI
->isReserved(Reg
)) {
1702 report("isRenamable set on reserved register", MO
, MONum
);
1706 if (MI
->isDebugValue() && MO
->isUse() && !MO
->isDebug()) {
1707 report("Use-reg is not IsDebug in a DBG_VALUE", MO
, MONum
);
1711 // Virtual register.
1712 const TargetRegisterClass
*RC
= MRI
->getRegClassOrNull(Reg
);
1714 // This is a generic virtual register.
1716 // If we're post-Select, we can't have gvregs anymore.
1717 if (isFunctionSelected
) {
1718 report("Generic virtual register invalid in a Selected function",
1723 // The gvreg must have a type and it must not have a SubIdx.
1724 LLT Ty
= MRI
->getType(Reg
);
1725 if (!Ty
.isValid()) {
1726 report("Generic virtual register must have a valid type", MO
,
1731 const RegisterBank
*RegBank
= MRI
->getRegBankOrNull(Reg
);
1733 // If we're post-RegBankSelect, the gvreg must have a bank.
1734 if (!RegBank
&& isFunctionRegBankSelected
) {
1735 report("Generic virtual register must have a bank in a "
1736 "RegBankSelected function",
1741 // Make sure the register fits into its register bank if any.
1742 if (RegBank
&& Ty
.isValid() &&
1743 RegBank
->getSize() < Ty
.getSizeInBits()) {
1744 report("Register bank is too small for virtual register", MO
,
1746 errs() << "Register bank " << RegBank
->getName() << " too small("
1747 << RegBank
->getSize() << ") to fit " << Ty
.getSizeInBits()
1752 report("Generic virtual register does not allow subregister index", MO
,
1757 // If this is a target specific instruction and this operand
1758 // has register class constraint, the virtual register must
1760 if (!isPreISelGenericOpcode(MCID
.getOpcode()) &&
1761 MONum
< MCID
.getNumOperands() &&
1762 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
)) {
1763 report("Virtual register does not match instruction constraint", MO
,
1765 errs() << "Expect register class "
1766 << TRI
->getRegClassName(
1767 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
))
1768 << " but got nothing\n";
1775 const TargetRegisterClass
*SRC
=
1776 TRI
->getSubClassWithSubReg(RC
, SubIdx
);
1778 report("Invalid subregister index for virtual register", MO
, MONum
);
1779 errs() << "Register class " << TRI
->getRegClassName(RC
)
1780 << " does not support subreg index " << SubIdx
<< "\n";
1784 report("Invalid register class for subregister index", MO
, MONum
);
1785 errs() << "Register class " << TRI
->getRegClassName(RC
)
1786 << " does not fully support subreg index " << SubIdx
<< "\n";
1790 if (MONum
< MCID
.getNumOperands()) {
1791 if (const TargetRegisterClass
*DRC
=
1792 TII
->getRegClass(MCID
, MONum
, TRI
, *MF
)) {
1794 const TargetRegisterClass
*SuperRC
=
1795 TRI
->getLargestLegalSuperClass(RC
, *MF
);
1797 report("No largest legal super class exists.", MO
, MONum
);
1800 DRC
= TRI
->getMatchingSuperRegClass(SuperRC
, DRC
, SubIdx
);
1802 report("No matching super-reg register class.", MO
, MONum
);
1806 if (!RC
->hasSuperClassEq(DRC
)) {
1807 report("Illegal virtual register for instruction", MO
, MONum
);
1808 errs() << "Expected a " << TRI
->getRegClassName(DRC
)
1809 << " register, but got a " << TRI
->getRegClassName(RC
)
1818 case MachineOperand::MO_RegisterMask
:
1819 regMasks
.push_back(MO
->getRegMask());
1822 case MachineOperand::MO_MachineBasicBlock
:
1823 if (MI
->isPHI() && !MO
->getMBB()->isSuccessor(MI
->getParent()))
1824 report("PHI operand is not in the CFG", MO
, MONum
);
1827 case MachineOperand::MO_FrameIndex
:
1828 if (LiveStks
&& LiveStks
->hasInterval(MO
->getIndex()) &&
1829 LiveInts
&& !LiveInts
->isNotInMIMap(*MI
)) {
1830 int FI
= MO
->getIndex();
1831 LiveInterval
&LI
= LiveStks
->getInterval(FI
);
1832 SlotIndex Idx
= LiveInts
->getInstructionIndex(*MI
);
1834 bool stores
= MI
->mayStore();
1835 bool loads
= MI
->mayLoad();
1836 // For a memory-to-memory move, we need to check if the frame
1837 // index is used for storing or loading, by inspecting the
1839 if (stores
&& loads
) {
1840 for (auto *MMO
: MI
->memoperands()) {
1841 const PseudoSourceValue
*PSV
= MMO
->getPseudoValue();
1842 if (PSV
== nullptr) continue;
1843 const FixedStackPseudoSourceValue
*Value
=
1844 dyn_cast
<FixedStackPseudoSourceValue
>(PSV
);
1845 if (Value
== nullptr) continue;
1846 if (Value
->getFrameIndex() != FI
) continue;
1854 if (loads
== stores
)
1855 report("Missing fixed stack memoperand.", MI
);
1857 if (loads
&& !LI
.liveAt(Idx
.getRegSlot(true))) {
1858 report("Instruction loads from dead spill slot", MO
, MONum
);
1859 errs() << "Live stack: " << LI
<< '\n';
1861 if (stores
&& !LI
.liveAt(Idx
.getRegSlot())) {
1862 report("Instruction stores to dead spill slot", MO
, MONum
);
1863 errs() << "Live stack: " << LI
<< '\n';
1873 void MachineVerifier::checkLivenessAtUse(const MachineOperand
*MO
,
1874 unsigned MONum
, SlotIndex UseIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
1875 LaneBitmask LaneMask
) {
1876 LiveQueryResult LRQ
= LR
.Query(UseIdx
);
1877 // Check if we have a segment at the use, note however that we only need one
1878 // live subregister range, the others may be dead.
1879 if (!LRQ
.valueIn() && LaneMask
.none()) {
1880 report("No live segment at use", MO
, MONum
);
1881 report_context_liverange(LR
);
1882 report_context_vreg_regunit(VRegOrUnit
);
1883 report_context(UseIdx
);
1885 if (MO
->isKill() && !LRQ
.isKill()) {
1886 report("Live range continues after kill flag", MO
, MONum
);
1887 report_context_liverange(LR
);
1888 report_context_vreg_regunit(VRegOrUnit
);
1890 report_context_lanemask(LaneMask
);
1891 report_context(UseIdx
);
1895 void MachineVerifier::checkLivenessAtDef(const MachineOperand
*MO
,
1896 unsigned MONum
, SlotIndex DefIdx
, const LiveRange
&LR
, unsigned VRegOrUnit
,
1897 bool SubRangeCheck
, LaneBitmask LaneMask
) {
1898 if (const VNInfo
*VNI
= LR
.getVNInfoAt(DefIdx
)) {
1899 assert(VNI
&& "NULL valno is not allowed");
1900 if (VNI
->def
!= DefIdx
) {
1901 report("Inconsistent valno->def", MO
, MONum
);
1902 report_context_liverange(LR
);
1903 report_context_vreg_regunit(VRegOrUnit
);
1905 report_context_lanemask(LaneMask
);
1906 report_context(*VNI
);
1907 report_context(DefIdx
);
1910 report("No live segment at def", MO
, MONum
);
1911 report_context_liverange(LR
);
1912 report_context_vreg_regunit(VRegOrUnit
);
1914 report_context_lanemask(LaneMask
);
1915 report_context(DefIdx
);
1917 // Check that, if the dead def flag is present, LiveInts agree.
1919 LiveQueryResult LRQ
= LR
.Query(DefIdx
);
1920 if (!LRQ
.isDeadDef()) {
1921 assert(Register::isVirtualRegister(VRegOrUnit
) &&
1922 "Expecting a virtual register.");
1923 // A dead subreg def only tells us that the specific subreg is dead. There
1924 // could be other non-dead defs of other subregs, or we could have other
1925 // parts of the register being live through the instruction. So unless we
1926 // are checking liveness for a subrange it is ok for the live range to
1927 // continue, given that we have a dead def of a subregister.
1928 if (SubRangeCheck
|| MO
->getSubReg() == 0) {
1929 report("Live range continues after dead def flag", MO
, MONum
);
1930 report_context_liverange(LR
);
1931 report_context_vreg_regunit(VRegOrUnit
);
1933 report_context_lanemask(LaneMask
);
1939 void MachineVerifier::checkLiveness(const MachineOperand
*MO
, unsigned MONum
) {
1940 const MachineInstr
*MI
= MO
->getParent();
1941 const unsigned Reg
= MO
->getReg();
1943 // Both use and def operands can read a register.
1944 if (MO
->readsReg()) {
1946 addRegWithSubRegs(regsKilled
, Reg
);
1948 // Check that LiveVars knows this kill.
1949 if (LiveVars
&& Register::isVirtualRegister(Reg
) && MO
->isKill()) {
1950 LiveVariables::VarInfo
&VI
= LiveVars
->getVarInfo(Reg
);
1951 if (!is_contained(VI
.Kills
, MI
))
1952 report("Kill missing from LiveVariables", MO
, MONum
);
1955 // Check LiveInts liveness and kill.
1956 if (LiveInts
&& !LiveInts
->isNotInMIMap(*MI
)) {
1957 SlotIndex UseIdx
= LiveInts
->getInstructionIndex(*MI
);
1958 // Check the cached regunit intervals.
1959 if (Register::isPhysicalRegister(Reg
) && !isReserved(Reg
)) {
1960 for (MCRegUnitIterator
Units(Reg
, TRI
); Units
.isValid(); ++Units
) {
1961 if (MRI
->isReservedRegUnit(*Units
))
1963 if (const LiveRange
*LR
= LiveInts
->getCachedRegUnit(*Units
))
1964 checkLivenessAtUse(MO
, MONum
, UseIdx
, *LR
, *Units
);
1968 if (Register::isVirtualRegister(Reg
)) {
1969 if (LiveInts
->hasInterval(Reg
)) {
1970 // This is a virtual register interval.
1971 const LiveInterval
&LI
= LiveInts
->getInterval(Reg
);
1972 checkLivenessAtUse(MO
, MONum
, UseIdx
, LI
, Reg
);
1974 if (LI
.hasSubRanges() && !MO
->isDef()) {
1975 unsigned SubRegIdx
= MO
->getSubReg();
1976 LaneBitmask MOMask
= SubRegIdx
!= 0
1977 ? TRI
->getSubRegIndexLaneMask(SubRegIdx
)
1978 : MRI
->getMaxLaneMaskForVReg(Reg
);
1979 LaneBitmask LiveInMask
;
1980 for (const LiveInterval::SubRange
&SR
: LI
.subranges()) {
1981 if ((MOMask
& SR
.LaneMask
).none())
1983 checkLivenessAtUse(MO
, MONum
, UseIdx
, SR
, Reg
, SR
.LaneMask
);
1984 LiveQueryResult LRQ
= SR
.Query(UseIdx
);
1986 LiveInMask
|= SR
.LaneMask
;
1988 // At least parts of the register has to be live at the use.
1989 if ((LiveInMask
& MOMask
).none()) {
1990 report("No live subrange at use", MO
, MONum
);
1992 report_context(UseIdx
);
1996 report("Virtual register has no live interval", MO
, MONum
);
2001 // Use of a dead register.
2002 if (!regsLive
.count(Reg
)) {
2003 if (Register::isPhysicalRegister(Reg
)) {
2004 // Reserved registers may be used even when 'dead'.
2005 bool Bad
= !isReserved(Reg
);
2006 // We are fine if just any subregister has a defined value.
2008 for (MCSubRegIterator
SubRegs(Reg
, TRI
); SubRegs
.isValid();
2010 if (regsLive
.count(*SubRegs
)) {
2016 // If there is an additional implicit-use of a super register we stop
2017 // here. By definition we are fine if the super register is not
2018 // (completely) dead, if the complete super register is dead we will
2019 // get a report for its operand.
2021 for (const MachineOperand
&MOP
: MI
->uses()) {
2022 if (!MOP
.isReg() || !MOP
.isImplicit())
2025 if (!Register::isPhysicalRegister(MOP
.getReg()))
2028 for (MCSubRegIterator
SubRegs(MOP
.getReg(), TRI
); SubRegs
.isValid();
2030 if (*SubRegs
== Reg
) {
2038 report("Using an undefined physical register", MO
, MONum
);
2039 } else if (MRI
->def_empty(Reg
)) {
2040 report("Reading virtual register without a def", MO
, MONum
);
2042 BBInfo
&MInfo
= MBBInfoMap
[MI
->getParent()];
2043 // We don't know which virtual registers are live in, so only complain
2044 // if vreg was killed in this MBB. Otherwise keep track of vregs that
2045 // must be live in. PHI instructions are handled separately.
2046 if (MInfo
.regsKilled
.count(Reg
))
2047 report("Using a killed virtual register", MO
, MONum
);
2048 else if (!MI
->isPHI())
2049 MInfo
.vregsLiveIn
.insert(std::make_pair(Reg
, MI
));
2055 // Register defined.
2056 // TODO: verify that earlyclobber ops are not used.
2058 addRegWithSubRegs(regsDead
, Reg
);
2060 addRegWithSubRegs(regsDefined
, Reg
);
2063 if (MRI
->isSSA() && Register::isVirtualRegister(Reg
) &&
2064 std::next(MRI
->def_begin(Reg
)) != MRI
->def_end())
2065 report("Multiple virtual register defs in SSA form", MO
, MONum
);
2067 // Check LiveInts for a live segment, but only for virtual registers.
2068 if (LiveInts
&& !LiveInts
->isNotInMIMap(*MI
)) {
2069 SlotIndex DefIdx
= LiveInts
->getInstructionIndex(*MI
);
2070 DefIdx
= DefIdx
.getRegSlot(MO
->isEarlyClobber());
2072 if (Register::isVirtualRegister(Reg
)) {
2073 if (LiveInts
->hasInterval(Reg
)) {
2074 const LiveInterval
&LI
= LiveInts
->getInterval(Reg
);
2075 checkLivenessAtDef(MO
, MONum
, DefIdx
, LI
, Reg
);
2077 if (LI
.hasSubRanges()) {
2078 unsigned SubRegIdx
= MO
->getSubReg();
2079 LaneBitmask MOMask
= SubRegIdx
!= 0
2080 ? TRI
->getSubRegIndexLaneMask(SubRegIdx
)
2081 : MRI
->getMaxLaneMaskForVReg(Reg
);
2082 for (const LiveInterval::SubRange
&SR
: LI
.subranges()) {
2083 if ((SR
.LaneMask
& MOMask
).none())
2085 checkLivenessAtDef(MO
, MONum
, DefIdx
, SR
, Reg
, true, SR
.LaneMask
);
2089 report("Virtual register has no Live interval", MO
, MONum
);
2096 void MachineVerifier::visitMachineInstrAfter(const MachineInstr
*MI
) {}
2098 // This function gets called after visiting all instructions in a bundle. The
2099 // argument points to the bundle header.
2100 // Normal stand-alone instructions are also considered 'bundles', and this
2101 // function is called for all of them.
2102 void MachineVerifier::visitMachineBundleAfter(const MachineInstr
*MI
) {
2103 BBInfo
&MInfo
= MBBInfoMap
[MI
->getParent()];
2104 set_union(MInfo
.regsKilled
, regsKilled
);
2105 set_subtract(regsLive
, regsKilled
); regsKilled
.clear();
2106 // Kill any masked registers.
2107 while (!regMasks
.empty()) {
2108 const uint32_t *Mask
= regMasks
.pop_back_val();
2109 for (RegSet::iterator I
= regsLive
.begin(), E
= regsLive
.end(); I
!= E
; ++I
)
2110 if (Register::isPhysicalRegister(*I
) &&
2111 MachineOperand::clobbersPhysReg(Mask
, *I
))
2112 regsDead
.push_back(*I
);
2114 set_subtract(regsLive
, regsDead
); regsDead
.clear();
2115 set_union(regsLive
, regsDefined
); regsDefined
.clear();
2119 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock
*MBB
) {
2120 MBBInfoMap
[MBB
].regsLiveOut
= regsLive
;
2124 SlotIndex stop
= Indexes
->getMBBEndIdx(MBB
);
2125 if (!(stop
> lastIndex
)) {
2126 report("Block ends before last instruction index", MBB
);
2127 errs() << "Block ends at " << stop
2128 << " last instruction was at " << lastIndex
<< '\n';
2134 // Calculate the largest possible vregsPassed sets. These are the registers that
2135 // can pass through an MBB live, but may not be live every time. It is assumed
2136 // that all vregsPassed sets are empty before the call.
2137 void MachineVerifier::calcRegsPassed() {
2138 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
2139 // have any vregsPassed.
2140 SmallPtrSet
<const MachineBasicBlock
*, 8> todo
;
2141 for (const auto &MBB
: *MF
) {
2142 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2143 if (!MInfo
.reachable
)
2145 for (MachineBasicBlock::const_succ_iterator SuI
= MBB
.succ_begin(),
2146 SuE
= MBB
.succ_end(); SuI
!= SuE
; ++SuI
) {
2147 BBInfo
&SInfo
= MBBInfoMap
[*SuI
];
2148 if (SInfo
.addPassed(MInfo
.regsLiveOut
))
2153 // Iteratively push vregsPassed to successors. This will converge to the same
2154 // final state regardless of DenseSet iteration order.
2155 while (!todo
.empty()) {
2156 const MachineBasicBlock
*MBB
= *todo
.begin();
2158 BBInfo
&MInfo
= MBBInfoMap
[MBB
];
2159 for (MachineBasicBlock::const_succ_iterator SuI
= MBB
->succ_begin(),
2160 SuE
= MBB
->succ_end(); SuI
!= SuE
; ++SuI
) {
2163 BBInfo
&SInfo
= MBBInfoMap
[*SuI
];
2164 if (SInfo
.addPassed(MInfo
.vregsPassed
))
2170 // Calculate the set of virtual registers that must be passed through each basic
2171 // block in order to satisfy the requirements of successor blocks. This is very
2172 // similar to calcRegsPassed, only backwards.
2173 void MachineVerifier::calcRegsRequired() {
2174 // First push live-in regs to predecessors' vregsRequired.
2175 SmallPtrSet
<const MachineBasicBlock
*, 8> todo
;
2176 for (const auto &MBB
: *MF
) {
2177 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2178 for (MachineBasicBlock::const_pred_iterator PrI
= MBB
.pred_begin(),
2179 PrE
= MBB
.pred_end(); PrI
!= PrE
; ++PrI
) {
2180 BBInfo
&PInfo
= MBBInfoMap
[*PrI
];
2181 if (PInfo
.addRequired(MInfo
.vregsLiveIn
))
2186 // Iteratively push vregsRequired to predecessors. This will converge to the
2187 // same final state regardless of DenseSet iteration order.
2188 while (!todo
.empty()) {
2189 const MachineBasicBlock
*MBB
= *todo
.begin();
2191 BBInfo
&MInfo
= MBBInfoMap
[MBB
];
2192 for (MachineBasicBlock::const_pred_iterator PrI
= MBB
->pred_begin(),
2193 PrE
= MBB
->pred_end(); PrI
!= PrE
; ++PrI
) {
2196 BBInfo
&SInfo
= MBBInfoMap
[*PrI
];
2197 if (SInfo
.addRequired(MInfo
.vregsRequired
))
2203 // Check PHI instructions at the beginning of MBB. It is assumed that
2204 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2205 void MachineVerifier::checkPHIOps(const MachineBasicBlock
&MBB
) {
2206 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2208 SmallPtrSet
<const MachineBasicBlock
*, 8> seen
;
2209 for (const MachineInstr
&Phi
: MBB
) {
2214 const MachineOperand
&MODef
= Phi
.getOperand(0);
2215 if (!MODef
.isReg() || !MODef
.isDef()) {
2216 report("Expected first PHI operand to be a register def", &MODef
, 0);
2219 if (MODef
.isTied() || MODef
.isImplicit() || MODef
.isInternalRead() ||
2220 MODef
.isEarlyClobber() || MODef
.isDebug())
2221 report("Unexpected flag on PHI operand", &MODef
, 0);
2222 Register DefReg
= MODef
.getReg();
2223 if (!Register::isVirtualRegister(DefReg
))
2224 report("Expected first PHI operand to be a virtual register", &MODef
, 0);
2226 for (unsigned I
= 1, E
= Phi
.getNumOperands(); I
!= E
; I
+= 2) {
2227 const MachineOperand
&MO0
= Phi
.getOperand(I
);
2229 report("Expected PHI operand to be a register", &MO0
, I
);
2232 if (MO0
.isImplicit() || MO0
.isInternalRead() || MO0
.isEarlyClobber() ||
2233 MO0
.isDebug() || MO0
.isTied())
2234 report("Unexpected flag on PHI operand", &MO0
, I
);
2236 const MachineOperand
&MO1
= Phi
.getOperand(I
+ 1);
2238 report("Expected PHI operand to be a basic block", &MO1
, I
+ 1);
2242 const MachineBasicBlock
&Pre
= *MO1
.getMBB();
2243 if (!Pre
.isSuccessor(&MBB
)) {
2244 report("PHI input is not a predecessor block", &MO1
, I
+ 1);
2248 if (MInfo
.reachable
) {
2250 BBInfo
&PrInfo
= MBBInfoMap
[&Pre
];
2251 if (!MO0
.isUndef() && PrInfo
.reachable
&&
2252 !PrInfo
.isLiveOut(MO0
.getReg()))
2253 report("PHI operand is not live-out from predecessor", &MO0
, I
);
2257 // Did we see all predecessors?
2258 if (MInfo
.reachable
) {
2259 for (MachineBasicBlock
*Pred
: MBB
.predecessors()) {
2260 if (!seen
.count(Pred
)) {
2261 report("Missing PHI operand", &Phi
);
2262 errs() << printMBBReference(*Pred
)
2263 << " is a predecessor according to the CFG.\n";
2270 void MachineVerifier::visitMachineFunctionAfter() {
2273 for (const MachineBasicBlock
&MBB
: *MF
)
2276 // Now check liveness info if available
2279 // Check for killed virtual registers that should be live out.
2280 for (const auto &MBB
: *MF
) {
2281 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2282 for (RegSet::iterator
2283 I
= MInfo
.vregsRequired
.begin(), E
= MInfo
.vregsRequired
.end(); I
!= E
;
2285 if (MInfo
.regsKilled
.count(*I
)) {
2286 report("Virtual register killed in block, but needed live out.", &MBB
);
2287 errs() << "Virtual register " << printReg(*I
)
2288 << " is used after the block.\n";
2293 BBInfo
&MInfo
= MBBInfoMap
[&MF
->front()];
2294 for (RegSet::iterator
2295 I
= MInfo
.vregsRequired
.begin(), E
= MInfo
.vregsRequired
.end(); I
!= E
;
2297 report("Virtual register defs don't dominate all uses.", MF
);
2298 report_context_vreg(*I
);
2303 verifyLiveVariables();
2305 verifyLiveIntervals();
2307 for (auto CSInfo
: MF
->getCallSitesInfo())
2308 if (!CSInfo
.first
->isCall())
2309 report("Call site info referencing instruction that is not call", MF
);
2312 void MachineVerifier::verifyLiveVariables() {
2313 assert(LiveVars
&& "Don't call verifyLiveVariables without LiveVars");
2314 for (unsigned i
= 0, e
= MRI
->getNumVirtRegs(); i
!= e
; ++i
) {
2315 unsigned Reg
= Register::index2VirtReg(i
);
2316 LiveVariables::VarInfo
&VI
= LiveVars
->getVarInfo(Reg
);
2317 for (const auto &MBB
: *MF
) {
2318 BBInfo
&MInfo
= MBBInfoMap
[&MBB
];
2320 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2321 if (MInfo
.vregsRequired
.count(Reg
)) {
2322 if (!VI
.AliveBlocks
.test(MBB
.getNumber())) {
2323 report("LiveVariables: Block missing from AliveBlocks", &MBB
);
2324 errs() << "Virtual register " << printReg(Reg
)
2325 << " must be live through the block.\n";
2328 if (VI
.AliveBlocks
.test(MBB
.getNumber())) {
2329 report("LiveVariables: Block should not be in AliveBlocks", &MBB
);
2330 errs() << "Virtual register " << printReg(Reg
)
2331 << " is not needed live through the block.\n";
2338 void MachineVerifier::verifyLiveIntervals() {
2339 assert(LiveInts
&& "Don't call verifyLiveIntervals without LiveInts");
2340 for (unsigned i
= 0, e
= MRI
->getNumVirtRegs(); i
!= e
; ++i
) {
2341 unsigned Reg
= Register::index2VirtReg(i
);
2343 // Spilling and splitting may leave unused registers around. Skip them.
2344 if (MRI
->reg_nodbg_empty(Reg
))
2347 if (!LiveInts
->hasInterval(Reg
)) {
2348 report("Missing live interval for virtual register", MF
);
2349 errs() << printReg(Reg
, TRI
) << " still has defs or uses\n";
2353 const LiveInterval
&LI
= LiveInts
->getInterval(Reg
);
2354 assert(Reg
== LI
.reg
&& "Invalid reg to interval mapping");
2355 verifyLiveInterval(LI
);
2358 // Verify all the cached regunit intervals.
2359 for (unsigned i
= 0, e
= TRI
->getNumRegUnits(); i
!= e
; ++i
)
2360 if (const LiveRange
*LR
= LiveInts
->getCachedRegUnit(i
))
2361 verifyLiveRange(*LR
, i
);
2364 void MachineVerifier::verifyLiveRangeValue(const LiveRange
&LR
,
2365 const VNInfo
*VNI
, unsigned Reg
,
2366 LaneBitmask LaneMask
) {
2367 if (VNI
->isUnused())
2370 const VNInfo
*DefVNI
= LR
.getVNInfoAt(VNI
->def
);
2373 report("Value not live at VNInfo def and not marked unused", MF
);
2374 report_context(LR
, Reg
, LaneMask
);
2375 report_context(*VNI
);
2379 if (DefVNI
!= VNI
) {
2380 report("Live segment at def has different VNInfo", MF
);
2381 report_context(LR
, Reg
, LaneMask
);
2382 report_context(*VNI
);
2386 const MachineBasicBlock
*MBB
= LiveInts
->getMBBFromIndex(VNI
->def
);
2388 report("Invalid VNInfo definition index", MF
);
2389 report_context(LR
, Reg
, LaneMask
);
2390 report_context(*VNI
);
2394 if (VNI
->isPHIDef()) {
2395 if (VNI
->def
!= LiveInts
->getMBBStartIdx(MBB
)) {
2396 report("PHIDef VNInfo is not defined at MBB start", MBB
);
2397 report_context(LR
, Reg
, LaneMask
);
2398 report_context(*VNI
);
2404 const MachineInstr
*MI
= LiveInts
->getInstructionFromIndex(VNI
->def
);
2406 report("No instruction at VNInfo def index", MBB
);
2407 report_context(LR
, Reg
, LaneMask
);
2408 report_context(*VNI
);
2413 bool hasDef
= false;
2414 bool isEarlyClobber
= false;
2415 for (ConstMIBundleOperands
MOI(*MI
); MOI
.isValid(); ++MOI
) {
2416 if (!MOI
->isReg() || !MOI
->isDef())
2418 if (Register::isVirtualRegister(Reg
)) {
2419 if (MOI
->getReg() != Reg
)
2422 if (!Register::isPhysicalRegister(MOI
->getReg()) ||
2423 !TRI
->hasRegUnit(MOI
->getReg(), Reg
))
2426 if (LaneMask
.any() &&
2427 (TRI
->getSubRegIndexLaneMask(MOI
->getSubReg()) & LaneMask
).none())
2430 if (MOI
->isEarlyClobber())
2431 isEarlyClobber
= true;
2435 report("Defining instruction does not modify register", MI
);
2436 report_context(LR
, Reg
, LaneMask
);
2437 report_context(*VNI
);
2440 // Early clobber defs begin at USE slots, but other defs must begin at
2442 if (isEarlyClobber
) {
2443 if (!VNI
->def
.isEarlyClobber()) {
2444 report("Early clobber def must be at an early-clobber slot", MBB
);
2445 report_context(LR
, Reg
, LaneMask
);
2446 report_context(*VNI
);
2448 } else if (!VNI
->def
.isRegister()) {
2449 report("Non-PHI, non-early clobber def must be at a register slot", MBB
);
2450 report_context(LR
, Reg
, LaneMask
);
2451 report_context(*VNI
);
2456 void MachineVerifier::verifyLiveRangeSegment(const LiveRange
&LR
,
2457 const LiveRange::const_iterator I
,
2458 unsigned Reg
, LaneBitmask LaneMask
)
2460 const LiveRange::Segment
&S
= *I
;
2461 const VNInfo
*VNI
= S
.valno
;
2462 assert(VNI
&& "Live segment has no valno");
2464 if (VNI
->id
>= LR
.getNumValNums() || VNI
!= LR
.getValNumInfo(VNI
->id
)) {
2465 report("Foreign valno in live segment", MF
);
2466 report_context(LR
, Reg
, LaneMask
);
2468 report_context(*VNI
);
2471 if (VNI
->isUnused()) {
2472 report("Live segment valno is marked unused", MF
);
2473 report_context(LR
, Reg
, LaneMask
);
2477 const MachineBasicBlock
*MBB
= LiveInts
->getMBBFromIndex(S
.start
);
2479 report("Bad start of live segment, no basic block", MF
);
2480 report_context(LR
, Reg
, LaneMask
);
2484 SlotIndex MBBStartIdx
= LiveInts
->getMBBStartIdx(MBB
);
2485 if (S
.start
!= MBBStartIdx
&& S
.start
!= VNI
->def
) {
2486 report("Live segment must begin at MBB entry or valno def", MBB
);
2487 report_context(LR
, Reg
, LaneMask
);
2491 const MachineBasicBlock
*EndMBB
=
2492 LiveInts
->getMBBFromIndex(S
.end
.getPrevSlot());
2494 report("Bad end of live segment, no basic block", MF
);
2495 report_context(LR
, Reg
, LaneMask
);
2500 // No more checks for live-out segments.
2501 if (S
.end
== LiveInts
->getMBBEndIdx(EndMBB
))
2504 // RegUnit intervals are allowed dead phis.
2505 if (!Register::isVirtualRegister(Reg
) && VNI
->isPHIDef() &&
2506 S
.start
== VNI
->def
&& S
.end
== VNI
->def
.getDeadSlot())
2509 // The live segment is ending inside EndMBB
2510 const MachineInstr
*MI
=
2511 LiveInts
->getInstructionFromIndex(S
.end
.getPrevSlot());
2513 report("Live segment doesn't end at a valid instruction", EndMBB
);
2514 report_context(LR
, Reg
, LaneMask
);
2519 // The block slot must refer to a basic block boundary.
2520 if (S
.end
.isBlock()) {
2521 report("Live segment ends at B slot of an instruction", EndMBB
);
2522 report_context(LR
, Reg
, LaneMask
);
2526 if (S
.end
.isDead()) {
2527 // Segment ends on the dead slot.
2528 // That means there must be a dead def.
2529 if (!SlotIndex::isSameInstr(S
.start
, S
.end
)) {
2530 report("Live segment ending at dead slot spans instructions", EndMBB
);
2531 report_context(LR
, Reg
, LaneMask
);
2536 // A live segment can only end at an early-clobber slot if it is being
2537 // redefined by an early-clobber def.
2538 if (S
.end
.isEarlyClobber()) {
2539 if (I
+1 == LR
.end() || (I
+1)->start
!= S
.end
) {
2540 report("Live segment ending at early clobber slot must be "
2541 "redefined by an EC def in the same instruction", EndMBB
);
2542 report_context(LR
, Reg
, LaneMask
);
2547 // The following checks only apply to virtual registers. Physreg liveness
2548 // is too weird to check.
2549 if (Register::isVirtualRegister(Reg
)) {
2550 // A live segment can end with either a redefinition, a kill flag on a
2551 // use, or a dead flag on a def.
2552 bool hasRead
= false;
2553 bool hasSubRegDef
= false;
2554 bool hasDeadDef
= false;
2555 for (ConstMIBundleOperands
MOI(*MI
); MOI
.isValid(); ++MOI
) {
2556 if (!MOI
->isReg() || MOI
->getReg() != Reg
)
2558 unsigned Sub
= MOI
->getSubReg();
2559 LaneBitmask SLM
= Sub
!= 0 ? TRI
->getSubRegIndexLaneMask(Sub
)
2560 : LaneBitmask::getAll();
2563 hasSubRegDef
= true;
2564 // An operand %0:sub0 reads %0:sub1..n. Invert the lane
2565 // mask for subregister defs. Read-undef defs will be handled by
2572 if (LaneMask
.any() && (LaneMask
& SLM
).none())
2574 if (MOI
->readsReg())
2577 if (S
.end
.isDead()) {
2578 // Make sure that the corresponding machine operand for a "dead" live
2579 // range has the dead flag. We cannot perform this check for subregister
2580 // liveranges as partially dead values are allowed.
2581 if (LaneMask
.none() && !hasDeadDef
) {
2582 report("Instruction ending live segment on dead slot has no dead flag",
2584 report_context(LR
, Reg
, LaneMask
);
2589 // When tracking subregister liveness, the main range must start new
2590 // values on partial register writes, even if there is no read.
2591 if (!MRI
->shouldTrackSubRegLiveness(Reg
) || LaneMask
.any() ||
2593 report("Instruction ending live segment doesn't read the register",
2595 report_context(LR
, Reg
, LaneMask
);
2602 // Now check all the basic blocks in this live segment.
2603 MachineFunction::const_iterator MFI
= MBB
->getIterator();
2604 // Is this live segment the beginning of a non-PHIDef VN?
2605 if (S
.start
== VNI
->def
&& !VNI
->isPHIDef()) {
2606 // Not live-in to any blocks.
2613 SmallVector
<SlotIndex
, 4> Undefs
;
2614 if (LaneMask
.any()) {
2615 LiveInterval
&OwnerLI
= LiveInts
->getInterval(Reg
);
2616 OwnerLI
.computeSubRangeUndefs(Undefs
, LaneMask
, *MRI
, *Indexes
);
2620 assert(LiveInts
->isLiveInToMBB(LR
, &*MFI
));
2621 // We don't know how to track physregs into a landing pad.
2622 if (!Register::isVirtualRegister(Reg
) && MFI
->isEHPad()) {
2623 if (&*MFI
== EndMBB
)
2629 // Is VNI a PHI-def in the current block?
2630 bool IsPHI
= VNI
->isPHIDef() &&
2631 VNI
->def
== LiveInts
->getMBBStartIdx(&*MFI
);
2633 // Check that VNI is live-out of all predecessors.
2634 for (MachineBasicBlock::const_pred_iterator PI
= MFI
->pred_begin(),
2635 PE
= MFI
->pred_end(); PI
!= PE
; ++PI
) {
2636 SlotIndex PEnd
= LiveInts
->getMBBEndIdx(*PI
);
2637 const VNInfo
*PVNI
= LR
.getVNInfoBefore(PEnd
);
2639 // All predecessors must have a live-out value. However for a phi
2640 // instruction with subregister intervals
2641 // only one of the subregisters (not necessarily the current one) needs to
2643 if (!PVNI
&& (LaneMask
.none() || !IsPHI
)) {
2644 if (LiveRangeCalc::isJointlyDominated(*PI
, Undefs
, *Indexes
))
2646 report("Register not marked live out of predecessor", *PI
);
2647 report_context(LR
, Reg
, LaneMask
);
2648 report_context(*VNI
);
2649 errs() << " live into " << printMBBReference(*MFI
) << '@'
2650 << LiveInts
->getMBBStartIdx(&*MFI
) << ", not live before "
2655 // Only PHI-defs can take different predecessor values.
2656 if (!IsPHI
&& PVNI
!= VNI
) {
2657 report("Different value live out of predecessor", *PI
);
2658 report_context(LR
, Reg
, LaneMask
);
2659 errs() << "Valno #" << PVNI
->id
<< " live out of "
2660 << printMBBReference(*(*PI
)) << '@' << PEnd
<< "\nValno #"
2661 << VNI
->id
<< " live into " << printMBBReference(*MFI
) << '@'
2662 << LiveInts
->getMBBStartIdx(&*MFI
) << '\n';
2665 if (&*MFI
== EndMBB
)
2671 void MachineVerifier::verifyLiveRange(const LiveRange
&LR
, unsigned Reg
,
2672 LaneBitmask LaneMask
) {
2673 for (const VNInfo
*VNI
: LR
.valnos
)
2674 verifyLiveRangeValue(LR
, VNI
, Reg
, LaneMask
);
2676 for (LiveRange::const_iterator I
= LR
.begin(), E
= LR
.end(); I
!= E
; ++I
)
2677 verifyLiveRangeSegment(LR
, I
, Reg
, LaneMask
);
2680 void MachineVerifier::verifyLiveInterval(const LiveInterval
&LI
) {
2681 unsigned Reg
= LI
.reg
;
2682 assert(Register::isVirtualRegister(Reg
));
2683 verifyLiveRange(LI
, Reg
);
2686 LaneBitmask MaxMask
= MRI
->getMaxLaneMaskForVReg(Reg
);
2687 for (const LiveInterval::SubRange
&SR
: LI
.subranges()) {
2688 if ((Mask
& SR
.LaneMask
).any()) {
2689 report("Lane masks of sub ranges overlap in live interval", MF
);
2692 if ((SR
.LaneMask
& ~MaxMask
).any()) {
2693 report("Subrange lanemask is invalid", MF
);
2697 report("Subrange must not be empty", MF
);
2698 report_context(SR
, LI
.reg
, SR
.LaneMask
);
2700 Mask
|= SR
.LaneMask
;
2701 verifyLiveRange(SR
, LI
.reg
, SR
.LaneMask
);
2702 if (!LI
.covers(SR
)) {
2703 report("A Subrange is not covered by the main range", MF
);
2708 // Check the LI only has one connected component.
2709 ConnectedVNInfoEqClasses
ConEQ(*LiveInts
);
2710 unsigned NumComp
= ConEQ
.Classify(LI
);
2712 report("Multiple connected components in live interval", MF
);
2714 for (unsigned comp
= 0; comp
!= NumComp
; ++comp
) {
2715 errs() << comp
<< ": valnos";
2716 for (LiveInterval::const_vni_iterator I
= LI
.vni_begin(),
2717 E
= LI
.vni_end(); I
!=E
; ++I
)
2718 if (comp
== ConEQ
.getEqClass(*I
))
2719 errs() << ' ' << (*I
)->id
;
2727 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
2728 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
2730 // We use a bool plus an integer to capture the stack state.
2731 struct StackStateOfBB
{
2732 StackStateOfBB() = default;
2733 StackStateOfBB(int EntryVal
, int ExitVal
, bool EntrySetup
, bool ExitSetup
) :
2734 EntryValue(EntryVal
), ExitValue(ExitVal
), EntryIsSetup(EntrySetup
),
2735 ExitIsSetup(ExitSetup
) {}
2737 // Can be negative, which means we are setting up a frame.
2740 bool EntryIsSetup
= false;
2741 bool ExitIsSetup
= false;
2744 } // end anonymous namespace
2746 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
2747 /// by a FrameDestroy <n>, stack adjustments are identical on all
2748 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
2749 void MachineVerifier::verifyStackFrame() {
2750 unsigned FrameSetupOpcode
= TII
->getCallFrameSetupOpcode();
2751 unsigned FrameDestroyOpcode
= TII
->getCallFrameDestroyOpcode();
2752 if (FrameSetupOpcode
== ~0u && FrameDestroyOpcode
== ~0u)
2755 SmallVector
<StackStateOfBB
, 8> SPState
;
2756 SPState
.resize(MF
->getNumBlockIDs());
2757 df_iterator_default_set
<const MachineBasicBlock
*> Reachable
;
2759 // Visit the MBBs in DFS order.
2760 for (df_ext_iterator
<const MachineFunction
*,
2761 df_iterator_default_set
<const MachineBasicBlock
*>>
2762 DFI
= df_ext_begin(MF
, Reachable
), DFE
= df_ext_end(MF
, Reachable
);
2763 DFI
!= DFE
; ++DFI
) {
2764 const MachineBasicBlock
*MBB
= *DFI
;
2766 StackStateOfBB BBState
;
2767 // Check the exit state of the DFS stack predecessor.
2768 if (DFI
.getPathLength() >= 2) {
2769 const MachineBasicBlock
*StackPred
= DFI
.getPath(DFI
.getPathLength() - 2);
2770 assert(Reachable
.count(StackPred
) &&
2771 "DFS stack predecessor is already visited.\n");
2772 BBState
.EntryValue
= SPState
[StackPred
->getNumber()].ExitValue
;
2773 BBState
.EntryIsSetup
= SPState
[StackPred
->getNumber()].ExitIsSetup
;
2774 BBState
.ExitValue
= BBState
.EntryValue
;
2775 BBState
.ExitIsSetup
= BBState
.EntryIsSetup
;
2778 // Update stack state by checking contents of MBB.
2779 for (const auto &I
: *MBB
) {
2780 if (I
.getOpcode() == FrameSetupOpcode
) {
2781 if (BBState
.ExitIsSetup
)
2782 report("FrameSetup is after another FrameSetup", &I
);
2783 BBState
.ExitValue
-= TII
->getFrameTotalSize(I
);
2784 BBState
.ExitIsSetup
= true;
2787 if (I
.getOpcode() == FrameDestroyOpcode
) {
2788 int Size
= TII
->getFrameTotalSize(I
);
2789 if (!BBState
.ExitIsSetup
)
2790 report("FrameDestroy is not after a FrameSetup", &I
);
2791 int AbsSPAdj
= BBState
.ExitValue
< 0 ? -BBState
.ExitValue
:
2793 if (BBState
.ExitIsSetup
&& AbsSPAdj
!= Size
) {
2794 report("FrameDestroy <n> is after FrameSetup <m>", &I
);
2795 errs() << "FrameDestroy <" << Size
<< "> is after FrameSetup <"
2796 << AbsSPAdj
<< ">.\n";
2798 BBState
.ExitValue
+= Size
;
2799 BBState
.ExitIsSetup
= false;
2802 SPState
[MBB
->getNumber()] = BBState
;
2804 // Make sure the exit state of any predecessor is consistent with the entry
2806 for (MachineBasicBlock::const_pred_iterator I
= MBB
->pred_begin(),
2807 E
= MBB
->pred_end(); I
!= E
; ++I
) {
2808 if (Reachable
.count(*I
) &&
2809 (SPState
[(*I
)->getNumber()].ExitValue
!= BBState
.EntryValue
||
2810 SPState
[(*I
)->getNumber()].ExitIsSetup
!= BBState
.EntryIsSetup
)) {
2811 report("The exit stack state of a predecessor is inconsistent.", MBB
);
2812 errs() << "Predecessor " << printMBBReference(*(*I
))
2813 << " has exit state (" << SPState
[(*I
)->getNumber()].ExitValue
2814 << ", " << SPState
[(*I
)->getNumber()].ExitIsSetup
<< "), while "
2815 << printMBBReference(*MBB
) << " has entry state ("
2816 << BBState
.EntryValue
<< ", " << BBState
.EntryIsSetup
<< ").\n";
2820 // Make sure the entry state of any successor is consistent with the exit
2822 for (MachineBasicBlock::const_succ_iterator I
= MBB
->succ_begin(),
2823 E
= MBB
->succ_end(); I
!= E
; ++I
) {
2824 if (Reachable
.count(*I
) &&
2825 (SPState
[(*I
)->getNumber()].EntryValue
!= BBState
.ExitValue
||
2826 SPState
[(*I
)->getNumber()].EntryIsSetup
!= BBState
.ExitIsSetup
)) {
2827 report("The entry stack state of a successor is inconsistent.", MBB
);
2828 errs() << "Successor " << printMBBReference(*(*I
))
2829 << " has entry state (" << SPState
[(*I
)->getNumber()].EntryValue
2830 << ", " << SPState
[(*I
)->getNumber()].EntryIsSetup
<< "), while "
2831 << printMBBReference(*MBB
) << " has exit state ("
2832 << BBState
.ExitValue
<< ", " << BBState
.ExitIsSetup
<< ").\n";
2836 // Make sure a basic block with return ends with zero stack adjustment.
2837 if (!MBB
->empty() && MBB
->back().isReturn()) {
2838 if (BBState
.ExitIsSetup
)
2839 report("A return block ends with a FrameSetup.", MBB
);
2840 if (BBState
.ExitValue
)
2841 report("A return block ends with a nonzero stack adjustment.", MBB
);