lib/MCA/Stages/RetireStage.cpp

   1 //===---------------------- RetireStage.cpp ---------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 ///
  10 /// This file defines the retire stage of an instruction pipeline.
  11 /// The RetireStage represents the process logic that interacts with the
  12 /// simulated RetireControlUnit hardware.
  13 ///
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "llvm/MCA/Stages/RetireStage.h"
  17 #include "llvm/MCA/HWEventListener.h"
  18 #include "llvm/Support/Debug.h"
  19
  20 #define DEBUG_TYPE "llvm-mca"
  21
  22 namespace llvm {
  23 namespace mca {
  24
  25 llvm::Error RetireStage::cycleStart() {
  26   if (RCU.isEmpty())
  27     return llvm::ErrorSuccess();
  28
  29   const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
  30   unsigned NumRetired = 0;
  31   while (!RCU.isEmpty()) {
  32     if (MaxRetirePerCycle != 0 && NumRetired == MaxRetirePerCycle)
  33       break;
  34     const RetireControlUnit::RUToken &Current = RCU.getCurrentToken();
  35     if (!Current.Executed)
  36       break;
  37     notifyInstructionRetired(Current.IR);
  38     RCU.consumeCurrentToken();
  39     NumRetired++;
  40   }
  41
  42   return llvm::ErrorSuccess();
  43 }
  44
  45 llvm::Error RetireStage::execute(InstRef &IR) {
  46   RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
  47   return llvm::ErrorSuccess();
  48 }
  49
  50 void RetireStage::notifyInstructionRetired(const InstRef &IR) const {
  51   LLVM_DEBUG(llvm::dbgs() << "[E] Instruction Retired: #" << IR << '\n');
  52   llvm::SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
  53   const Instruction &Inst = *IR.getInstruction();
  54
  55   // Release the load/store queue entries.
  56   if (Inst.isMemOp())
  57     LSU.onInstructionRetired(IR);
  58
  59   for (const WriteState &WS : Inst.getDefs())
  60     PRF.removeRegisterWrite(WS, FreedRegs);
  61   notifyEvent<HWInstructionEvent>(HWInstructionRetiredEvent(IR, FreedRegs));
  62 }
  63
  64 } // namespace mca
  65 } // namespace llvm