lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing.
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // AArch64 Subtarget features.
  20 //
  21
  22 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  23                                        "Enable ARMv8 FP">;
  24
  25 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  26   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  27
  28 def FeatureSM4 : SubtargetFeature<
  29     "sm4", "HasSM4", "true",
  30     "Enable SM3 and SM4 support", [FeatureNEON]>;
  31
  32 def FeatureSHA2 : SubtargetFeature<
  33     "sha2", "HasSHA2", "true",
  34     "Enable SHA1 and SHA256 support", [FeatureNEON]>;
  35
  36 def FeatureSHA3 : SubtargetFeature<
  37     "sha3", "HasSHA3", "true",
  38     "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
  39
  40 def FeatureAES : SubtargetFeature<
  41     "aes", "HasAES", "true",
  42     "Enable AES support", [FeatureNEON]>;
  43
  44 // Crypto has been split up and any combination is now valid (see the
  45 // crypto defintions above). Also, crypto is now context sensitive:
  46 // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
  47 // Therefore, we rely on Clang, the user interacing tool, to pass on the
  48 // appropriate crypto options. But here in the backend, crypto has very little
  49 // meaning anymore. We kept the Crypto defintion here for backward
  50 // compatibility, and now imply features SHA2 and AES, which was the
  51 // "traditional" meaning of Crypto.
  52 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  53   "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
  54
  55 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  56   "Enable ARMv8 CRC-32 checksum instructions">;
  57
  58 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  59   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  60
  61 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  62   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  63
  64 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
  65   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
  66
  67 def FeaturePAN : SubtargetFeature<
  68     "pan", "HasPAN", "true",
  69     "Enables ARM v8.1 Privileged Access-Never extension">;
  70
  71 def FeatureLOR : SubtargetFeature<
  72     "lor", "HasLOR", "true",
  73     "Enables ARM v8.1 Limited Ordering Regions extension">;
  74
  75 def FeatureVH : SubtargetFeature<
  76     "vh", "HasVH", "true",
  77     "Enables ARM v8.1 Virtual Host extension">;
  78
  79 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  80   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  81
  82 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  83   "Full FP16", [FeatureFPARMv8]>;
  84
  85 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
  86   "Enable FP16 FML instructions", [FeatureFullFP16]>;
  87
  88 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  89   "Enable Statistical Profiling extension">;
  90
  91 def FeaturePAN_RWV : SubtargetFeature<
  92     "pan-rwv", "HasPAN_RWV", "true",
  93     "Enable v8.2 PAN s1e1R and s1e1W Variants",
  94     [FeaturePAN]>;
  95
  96 // UAO PState
  97 def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
  98     "Enable v8.2 UAO PState">;
  99
 100 def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
 101     "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
 102
 103 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
 104   "Enable Scalable Vector Extension (SVE) instructions">;
 105
 106 def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
 107   "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>;
 108
 109 def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
 110   "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
 111
 112 def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
 113   "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
 114
 115 def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
 116   "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
 117
 118 def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
 119   "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
 120
 121 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
 122                                         "Has zero-cycle register moves">;
 123
 124 def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
 125                                         "Has zero-cycle zeroing instructions for generic registers">;
 126
 127 def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
 128                                         "Has zero-cycle zeroing instructions for FP registers">;
 129
 130 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 131                                         "Has zero-cycle zeroing instructions",
 132                                         [FeatureZCZeroingGP, FeatureZCZeroingFP]>;
 133
 134 /// ... but the floating-point version doesn't quite work in rare cases on older
 135 /// CPUs.
 136 def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
 137     "HasZeroCycleZeroingFPWorkaround", "true",
 138     "The zero-cycle floating-point zeroing instruction has a bug">;
 139
 140 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 141                                           "StrictAlign", "true",
 142                                           "Disallow all unaligned memory "
 143                                           "access">;
 144
 145 foreach i = {1-7,9-15,18,20-28} in
 146     def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
 147                                              "Reserve X"#i#", making it unavailable "
 148                                              "as a GPR">;
 149
 150 foreach i = {8-15,18} in
 151     def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
 152          "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
 153
 154 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 155                                     "Use alias analysis during codegen">;
 156
 157 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
 158     "true",
 159     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
 160
 161 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
 162     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
 163     "Prefer likely predicted branches over selects">;
 164
 165 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
 166     "CustomAsCheapAsMove", "true",
 167     "Use custom handling of cheap instructions">;
 168
 169 def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
 170     "ExynosAsCheapAsMove", "true",
 171     "Use Exynos specific handling of cheap instructions",
 172     [FeatureCustomCheapAsMoveHandling]>;
 173
 174 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
 175     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 176
 177 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
 178     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
 179
 180 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
 181     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
 182
 183 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
 184     "true", "STR of Q register with register offset is slow">;
 185
 186 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
 187     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
 188     "true", "Use alternative pattern for sextload convert to f32">;
 189
 190 def FeatureArithmeticBccFusion : SubtargetFeature<
 191     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
 192     "CPU fuses arithmetic+bcc operations">;
 193
 194 def FeatureArithmeticCbzFusion : SubtargetFeature<
 195     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 196     "CPU fuses arithmetic + cbz/cbnz operations">;
 197
 198 def FeatureFuseAddress : SubtargetFeature<
 199     "fuse-address", "HasFuseAddress", "true",
 200     "CPU fuses address generation and memory operations">;
 201
 202 def FeatureFuseAES : SubtargetFeature<
 203     "fuse-aes", "HasFuseAES", "true",
 204     "CPU fuses AES crypto operations">;
 205
 206 def FeatureFuseArithmeticLogic : SubtargetFeature<
 207     "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
 208     "CPU fuses arithmetic and logic operations">;
 209
 210 def FeatureFuseCCSelect : SubtargetFeature<
 211     "fuse-csel", "HasFuseCCSelect", "true",
 212     "CPU fuses conditional select operations">;
 213
 214 def FeatureFuseCryptoEOR : SubtargetFeature<
 215     "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
 216     "CPU fuses AES/PMULL and EOR operations">;
 217
 218 def FeatureFuseLiterals : SubtargetFeature<
 219     "fuse-literals", "HasFuseLiterals", "true",
 220     "CPU fuses literal generation operations">;
 221
 222 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 223     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 224     "Disable latency scheduling heuristic">;
 225
 226 def FeatureForce32BitJumpTables
 227    : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
 228                       "Force jump table entries to be 32-bits wide except at MinSize">;
 229
 230 def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
 231                                    "Enable support for RCPC extension">;
 232
 233 def FeatureUseRSqrt : SubtargetFeature<
 234     "use-reciprocal-square-root", "UseRSqrt", "true",
 235     "Use the reciprocal square root approximation">;
 236
 237 def FeatureDotProd : SubtargetFeature<
 238     "dotprod", "HasDotProd", "true",
 239     "Enable dot product support">;
 240
 241 def FeaturePA : SubtargetFeature<
 242     "pa", "HasPA", "true",
 243     "Enable v8.3-A Pointer Authentication enchancement">;
 244
 245 def FeatureJS : SubtargetFeature<
 246     "jsconv", "HasJS", "true",
 247     "Enable v8.3-A JavaScript FP conversion enchancement",
 248     [FeatureFPARMv8]>;
 249
 250 def FeatureCCIDX : SubtargetFeature<
 251     "ccidx", "HasCCIDX", "true",
 252     "Enable v8.3-A Extend of the CCSIDR number of sets">;
 253
 254 def FeatureComplxNum : SubtargetFeature<
 255     "complxnum", "HasComplxNum", "true",
 256     "Enable v8.3-A Floating-point complex number support",
 257     [FeatureNEON]>;
 258
 259 def FeatureNV : SubtargetFeature<
 260     "nv", "HasNV", "true",
 261     "Enable v8.4-A Nested Virtualization Enchancement">;
 262
 263 def FeatureRASv8_4 : SubtargetFeature<
 264     "rasv8_4", "HasRASv8_4", "true",
 265     "Enable v8.4-A Reliability, Availability and Serviceability extension",
 266     [FeatureRAS]>;
 267
 268 def FeatureMPAM : SubtargetFeature<
 269     "mpam", "HasMPAM", "true",
 270     "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
 271
 272 def FeatureDIT : SubtargetFeature<
 273     "dit", "HasDIT", "true",
 274     "Enable v8.4-A Data Independent Timing instructions">;
 275
 276 def FeatureTRACEV8_4 : SubtargetFeature<
 277     "tracev8.4", "HasTRACEV8_4", "true",
 278     "Enable v8.4-A Trace extension">;
 279
 280 def FeatureAM : SubtargetFeature<
 281     "am", "HasAM", "true",
 282     "Enable v8.4-A Activity Monitors extension">;
 283
 284 def FeatureSEL2 : SubtargetFeature<
 285     "sel2", "HasSEL2", "true",
 286     "Enable v8.4-A Secure Exception Level 2 extension">;
 287
 288 def FeaturePMU : SubtargetFeature<
 289     "pmu", "HasPMU", "true",
 290     "Enable v8.4-A PMU extension">;
 291
 292 def FeatureTLB_RMI : SubtargetFeature<
 293     "tlb-rmi", "HasTLB_RMI", "true",
 294     "Enable v8.4-A TLB Range and Maintenance Instructions">;
 295
 296 def FeatureFMI : SubtargetFeature<
 297     "fmi", "HasFMI", "true",
 298     "Enable v8.4-A Flag Manipulation Instructions">;
 299
 300 // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
 301 def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
 302     "Enable v8.4-A RCPC instructions with Immediate Offsets",
 303     [FeatureRCPC]>;
 304
 305 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 306                                         "NegativeImmediates", "false",
 307                                         "Convert immediates and instructions "
 308                                         "to their negated or complemented "
 309                                         "equivalent when the immediate does "
 310                                         "not fit in the encoding.">;
 311
 312 def FeatureLSLFast : SubtargetFeature<
 313     "lsl-fast", "HasLSLFast", "true",
 314     "CPU has a fastpath logical shift of up to 3 places">;
 315
 316 def FeatureAggressiveFMA :
 317   SubtargetFeature<"aggressive-fma",
 318                    "HasAggressiveFMA",
 319                    "true",
 320                    "Enable Aggressive FMA for floating-point.">;
 321
 322 def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
 323   "Enable alternative NZCV format for floating point comparisons">;
 324
 325 def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
 326   "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
 327   "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
 328
 329 def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
 330   "true", "Enable architectural speculation restriction" >;
 331
 332 def FeatureSB : SubtargetFeature<"sb", "HasSB",
 333   "true", "Enable v8.5 Speculation Barrier" >;
 334
 335 def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
 336   "true", "Enable Speculative Store Bypass Safe bit" >;
 337
 338 def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
 339   "Enable v8.5a execution and data prediction invalidation instructions" >;
 340
 341 def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
 342     "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
 343
 344 def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
 345     "true", "Enable Branch Target Identification" >;
 346
 347 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
 348     "true", "Enable Random Number generation instructions" >;
 349
 350 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
 351     "true", "Enable Memory Tagging Extension" >;
 352
 353 def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
 354     "true", "Enable Trace Buffer Extension">;
 355
 356 def FeatureETE : SubtargetFeature<"ete", "HasETE",
 357     "true", "Enable Embedded Trace Extension",
 358     [FeatureTRBE]>;
 359
 360 def FeatureTME : SubtargetFeature<"tme", "HasTME",
 361     "true", "Enable Transactional Memory Extension" >;
 362
 363 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
 364     "AllowTaggedGlobals",
 365     "true", "Use an instruction sequence for taking the address of a global "
 366     "that allows a memory tag in the upper address bits">;
 367
 368 //===----------------------------------------------------------------------===//
 369 // Architectures.
 370 //
 371
 372 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 373   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
 374   FeaturePAN, FeatureLOR, FeatureVH]>;
 375
 376 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 377   "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
 378   FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
 379
 380 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 381   "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
 382   FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
 383
 384 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 385   "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
 386   FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
 387   FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
 388   FeatureFMI, FeatureRCPC_IMMO]>;
 389
 390 def HasV8_5aOps : SubtargetFeature<
 391   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
 392   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
 393    FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
 394    FeatureBranchTargetId]
 395 >;
 396
 397 //===----------------------------------------------------------------------===//
 398 // Register File Description
 399 //===----------------------------------------------------------------------===//
 400
 401 include "AArch64RegisterInfo.td"
 402 include "AArch64RegisterBanks.td"
 403 include "AArch64CallingConvention.td"
 404
 405 //===----------------------------------------------------------------------===//
 406 // Instruction Descriptions
 407 //===----------------------------------------------------------------------===//
 408
 409 include "AArch64Schedule.td"
 410 include "AArch64InstrInfo.td"
 411 include "AArch64SchedPredicates.td"
 412 include "AArch64SchedPredExynos.td"
 413 include "AArch64Combine.td"
 414
 415 def AArch64InstrInfo : InstrInfo;
 416
 417 //===----------------------------------------------------------------------===//
 418 // Named operands for MRS/MSR/TLBI/...
 419 //===----------------------------------------------------------------------===//
 420
 421 include "AArch64SystemOperands.td"
 422
 423 //===----------------------------------------------------------------------===//
 424 // Access to privileged registers
 425 //===----------------------------------------------------------------------===//
 426
 427 foreach i = 1-3 in
 428 def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
 429   "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
 430
 431 //===----------------------------------------------------------------------===//
 432 // AArch64 Processors supported.
 433 //
 434
 435 //===----------------------------------------------------------------------===//
 436 // Unsupported features to disable for scheduling models
 437 //===----------------------------------------------------------------------===//
 438
 439 class AArch64Unsupported { list<Predicate> F; }
 440
 441 def SVEUnsupported : AArch64Unsupported {
 442   let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
 443            HasSVE2BitPerm];
 444 }
 445
 446 include "AArch64SchedA53.td"
 447 include "AArch64SchedA57.td"
 448 include "AArch64SchedCyclone.td"
 449 include "AArch64SchedFalkor.td"
 450 include "AArch64SchedKryo.td"
 451 include "AArch64SchedExynosM1.td"
 452 include "AArch64SchedExynosM3.td"
 453 include "AArch64SchedExynosM4.td"
 454 include "AArch64SchedThunderX.td"
 455 include "AArch64SchedThunderX2T99.td"
 456
 457 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 458                                    "Cortex-A35 ARM processors", [
 459                                    FeatureCRC,
 460                                    FeatureCrypto,
 461                                    FeatureFPARMv8,
 462                                    FeatureNEON,
 463                                    FeaturePerfMon
 464                                    ]>;
 465
 466 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 467                                    "Cortex-A53 ARM processors", [
 468                                    FeatureBalanceFPOps,
 469                                    FeatureCRC,
 470                                    FeatureCrypto,
 471                                    FeatureCustomCheapAsMoveHandling,
 472                                    FeatureFPARMv8,
 473                                    FeatureFuseAES,
 474                                    FeatureNEON,
 475                                    FeaturePerfMon,
 476                                    FeaturePostRAScheduler,
 477                                    FeatureUseAA
 478                                    ]>;
 479
 480 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 481                                    "Cortex-A55 ARM processors", [
 482                                    HasV8_2aOps,
 483                                    FeatureCrypto,
 484                                    FeatureFPARMv8,
 485                                    FeatureFuseAES,
 486                                    FeatureNEON,
 487                                    FeatureFullFP16,
 488                                    FeatureDotProd,
 489                                    FeatureRCPC,
 490                                    FeaturePerfMon
 491                                    ]>;
 492
 493 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 494                                    "Cortex-A57 ARM processors", [
 495                                    FeatureBalanceFPOps,
 496                                    FeatureCRC,
 497                                    FeatureCrypto,
 498                                    FeatureCustomCheapAsMoveHandling,
 499                                    FeatureFPARMv8,
 500                                    FeatureFuseAES,
 501                                    FeatureFuseLiterals,
 502                                    FeatureNEON,
 503                                    FeaturePerfMon,
 504                                    FeaturePostRAScheduler,
 505                                    FeaturePredictableSelectIsExpensive
 506                                    ]>;
 507
 508 def ProcA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
 509                                    "Cortex-A65 ARM processors", [
 510                                    HasV8_2aOps,
 511                                    FeatureCrypto,
 512                                    FeatureDotProd,
 513                                    FeatureFPARMv8,
 514                                    FeatureFullFP16,
 515                                    FeatureNEON,
 516                                    FeatureRAS,
 517                                    FeatureRCPC,
 518                                    FeatureSSBS,
 519                                    ]>;
 520
 521 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 522                                    "Cortex-A72 ARM processors", [
 523                                    FeatureCRC,
 524                                    FeatureCrypto,
 525                                    FeatureFPARMv8,
 526                                    FeatureFuseAES,
 527                                    FeatureNEON,
 528                                    FeaturePerfMon
 529                                    ]>;
 530
 531 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 532                                    "Cortex-A73 ARM processors", [
 533                                    FeatureCRC,
 534                                    FeatureCrypto,
 535                                    FeatureFPARMv8,
 536                                    FeatureFuseAES,
 537                                    FeatureNEON,
 538                                    FeaturePerfMon
 539                                    ]>;
 540
 541 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 542                                    "Cortex-A75 ARM processors", [
 543                                    HasV8_2aOps,
 544                                    FeatureCrypto,
 545                                    FeatureFPARMv8,
 546                                    FeatureFuseAES,
 547                                    FeatureNEON,
 548                                    FeatureFullFP16,
 549                                    FeatureDotProd,
 550                                    FeatureRCPC,
 551                                    FeaturePerfMon
 552                                    ]>;
 553
 554 def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
 555                                    "Cortex-A76 ARM processors", [
 556                                     HasV8_2aOps,
 557                                     FeatureFPARMv8,
 558                                     FeatureNEON,
 559                                     FeatureRCPC,
 560                                     FeatureCrypto,
 561                                     FeatureFullFP16,
 562                                     FeatureDotProd,
 563                                     FeatureSSBS
 564                                     ]>;
 565
 566 // Note that cyclone does not fuse AES instructions, but newer apple chips do
 567 // perform the fusion and cyclone is used by default when targetting apple OSes.
 568 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 569                                    "Cyclone", [
 570                                    FeatureAlternateSExtLoadCVTF32Pattern,
 571                                    FeatureArithmeticBccFusion,
 572                                    FeatureArithmeticCbzFusion,
 573                                    FeatureCrypto,
 574                                    FeatureDisableLatencySchedHeuristic,
 575                                    FeatureFPARMv8,
 576                                    FeatureFuseAES,
 577                                    FeatureFuseCryptoEOR,
 578                                    FeatureNEON,
 579                                    FeaturePerfMon,
 580                                    FeatureZCRegMove,
 581                                    FeatureZCZeroing,
 582                                    FeatureZCZeroingFPWorkaround
 583                                    ]>;
 584
 585 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 586                                     "Samsung Exynos-M1 processors",
 587                                     [FeatureSlowPaired128,
 588                                      FeatureCRC,
 589                                      FeatureCrypto,
 590                                      FeatureExynosCheapAsMoveHandling,
 591                                      FeatureForce32BitJumpTables,
 592                                      FeatureFuseAES,
 593                                      FeaturePerfMon,
 594                                      FeaturePostRAScheduler,
 595                                      FeatureSlowMisaligned128Store,
 596                                      FeatureUseRSqrt,
 597                                      FeatureZCZeroingFP]>;
 598
 599 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 600                                     "Samsung Exynos-M2 processors",
 601                                     [FeatureSlowPaired128,
 602                                      FeatureCRC,
 603                                      FeatureCrypto,
 604                                      FeatureExynosCheapAsMoveHandling,
 605                                      FeatureForce32BitJumpTables,
 606                                      FeatureFuseAES,
 607                                      FeaturePerfMon,
 608                                      FeaturePostRAScheduler,
 609                                      FeatureSlowMisaligned128Store,
 610                                      FeatureZCZeroingFP]>;
 611
 612 def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
 613                                     "Samsung Exynos-M3 processors",
 614                                     [FeatureCRC,
 615                                      FeatureCrypto,
 616                                      FeatureExynosCheapAsMoveHandling,
 617                                      FeatureForce32BitJumpTables,
 618                                      FeatureFuseAddress,
 619                                      FeatureFuseAES,
 620                                      FeatureFuseCCSelect,
 621                                      FeatureFuseLiterals,
 622                                      FeatureLSLFast,
 623                                      FeaturePerfMon,
 624                                      FeaturePostRAScheduler,
 625                                      FeaturePredictableSelectIsExpensive,
 626                                      FeatureZCZeroingFP]>;
 627
 628 def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
 629                                     "Samsung Exynos-M4 processors",
 630                                     [HasV8_2aOps,
 631                                      FeatureArithmeticBccFusion,
 632                                      FeatureArithmeticCbzFusion,
 633                                      FeatureCrypto,
 634                                      FeatureDotProd,
 635                                      FeatureExynosCheapAsMoveHandling,
 636                                      FeatureForce32BitJumpTables,
 637                                      FeatureFullFP16,
 638                                      FeatureFuseAddress,
 639                                      FeatureFuseAES,
 640                                      FeatureFuseArithmeticLogic,
 641                                      FeatureFuseCCSelect,
 642                                      FeatureFuseLiterals,
 643                                      FeatureLSLFast,
 644                                      FeaturePerfMon,
 645                                      FeaturePostRAScheduler,
 646                                      FeatureZCZeroing]>;
 647
 648 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 649                                    "Qualcomm Kryo processors", [
 650                                    FeatureCRC,
 651                                    FeatureCrypto,
 652                                    FeatureCustomCheapAsMoveHandling,
 653                                    FeatureFPARMv8,
 654                                    FeatureNEON,
 655                                    FeaturePerfMon,
 656                                    FeaturePostRAScheduler,
 657                                    FeaturePredictableSelectIsExpensive,
 658                                    FeatureZCZeroing,
 659                                    FeatureLSLFast
 660                                    ]>;
 661
 662 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 663                                    "Qualcomm Falkor processors", [
 664                                    FeatureCRC,
 665                                    FeatureCrypto,
 666                                    FeatureCustomCheapAsMoveHandling,
 667                                    FeatureFPARMv8,
 668                                    FeatureNEON,
 669                                    FeaturePerfMon,
 670                                    FeaturePostRAScheduler,
 671                                    FeaturePredictableSelectIsExpensive,
 672                                    FeatureRDM,
 673                                    FeatureZCZeroing,
 674                                    FeatureLSLFast,
 675                                    FeatureSlowSTRQro
 676                                    ]>;
 677
 678 def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
 679                                       "NeoverseE1",
 680                                       "Neoverse E1 ARM processors", [
 681                                       HasV8_2aOps,
 682                                       FeatureCrypto,
 683                                       FeatureDotProd,
 684                                       FeatureFPARMv8,
 685                                       FeatureFullFP16,
 686                                       FeatureNEON,
 687                                       FeatureRCPC,
 688                                       FeatureSSBS,
 689                                       ]>;
 690
 691 def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
 692                                       "NeoverseN1",
 693                                       "Neoverse N1 ARM processors", [
 694                                       HasV8_2aOps,
 695                                       FeatureCrypto,
 696                                       FeatureDotProd,
 697                                       FeatureFPARMv8,
 698                                       FeatureFullFP16,
 699                                       FeatureNEON,
 700                                       FeatureRCPC,
 701                                       FeatureSPE,
 702                                       FeatureSSBS,
 703                                       ]>;
 704
 705 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
 706                                    "Qualcomm Saphira processors", [
 707                                    FeatureCrypto,
 708                                    FeatureCustomCheapAsMoveHandling,
 709                                    FeatureFPARMv8,
 710                                    FeatureNEON,
 711                                    FeatureSPE,
 712                                    FeaturePerfMon,
 713                                    FeaturePostRAScheduler,
 714                                    FeaturePredictableSelectIsExpensive,
 715                                    FeatureZCZeroing,
 716                                    FeatureLSLFast,
 717                                    HasV8_4aOps]>;
 718
 719 def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
 720                                          "ThunderX2T99",
 721                                          "Cavium ThunderX2 processors", [
 722                                           FeatureAggressiveFMA,
 723                                           FeatureCRC,
 724                                           FeatureCrypto,
 725                                           FeatureFPARMv8,
 726                                           FeatureArithmeticBccFusion,
 727                                           FeatureNEON,
 728                                           FeaturePostRAScheduler,
 729                                           FeaturePredictableSelectIsExpensive,
 730                                           FeatureLSE,
 731                                           HasV8_1aOps]>;
 732
 733 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
 734                                     "Cavium ThunderX processors", [
 735                                     FeatureCRC,
 736                                     FeatureCrypto,
 737                                     FeatureFPARMv8,
 738                                     FeaturePerfMon,
 739                                     FeaturePostRAScheduler,
 740                                     FeaturePredictableSelectIsExpensive,
 741                                     FeatureNEON]>;
 742
 743 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
 744                                        "ThunderXT88",
 745                                        "Cavium ThunderX processors", [
 746                                        FeatureCRC,
 747                                        FeatureCrypto,
 748                                        FeatureFPARMv8,
 749                                        FeaturePerfMon,
 750                                        FeaturePostRAScheduler,
 751                                        FeaturePredictableSelectIsExpensive,
 752                                        FeatureNEON]>;
 753
 754 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
 755                                        "ThunderXT81",
 756                                        "Cavium ThunderX processors", [
 757                                        FeatureCRC,
 758                                        FeatureCrypto,
 759                                        FeatureFPARMv8,
 760                                        FeaturePerfMon,
 761                                        FeaturePostRAScheduler,
 762                                        FeaturePredictableSelectIsExpensive,
 763                                        FeatureNEON]>;
 764
 765 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
 766                                        "ThunderXT83",
 767                                        "Cavium ThunderX processors", [
 768                                        FeatureCRC,
 769                                        FeatureCrypto,
 770                                        FeatureFPARMv8,
 771                                        FeaturePerfMon,
 772                                        FeaturePostRAScheduler,
 773                                        FeaturePredictableSelectIsExpensive,
 774                                        FeatureNEON]>;
 775
 776 def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
 777                                   "HiSilicon TS-V110 processors", [
 778                                   HasV8_2aOps,
 779                                   FeatureCrypto,
 780                                   FeatureCustomCheapAsMoveHandling,
 781                                   FeatureFPARMv8,
 782                                   FeatureFuseAES,
 783                                   FeatureNEON,
 784                                   FeaturePerfMon,
 785                                   FeaturePostRAScheduler,
 786                                   FeatureSPE,
 787                                   FeatureFullFP16,
 788                                   FeatureFP16FML,
 789                                   FeatureDotProd]>;
 790
 791 def : ProcessorModel<"generic", NoSchedModel, [
 792                      FeatureFPARMv8,
 793                      FeatureFuseAES,
 794                      FeatureNEON,
 795                      FeaturePerfMon,
 796                      FeaturePostRAScheduler,
 797 // ETE and TRBE are future architecture extensions. We temporariliy enable them
 798 // by default for users targeting generic AArch64, until it is decided in which
 799 // armv8.x-a architecture revision they will end up. The extensions do not
 800 // affect code generated by the compiler and can be used only by explicitly
 801 // mentioning the new system register names in assembly.
 802                      FeatureETE
 803                      ]>;
 804
 805 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 806 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 807 def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
 808 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 809 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
 810 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
 811 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 812 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 813 def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
 814 def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
 815 def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
 816 def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
 817 def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
 818 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 819 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 820 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 821 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
 822 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
 823 def : ProcessorModel<"exynos-m5", ExynosM4Model, [ProcExynosM4]>;
 824 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 825 def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
 826 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 827 // Cavium ThunderX/ThunderX T8X  Processors
 828 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
 829 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
 830 def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
 831 def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
 832 // Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
 833 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
 834 // FIXME: HiSilicon TSV110 is currently modeled as a Cortex-A57.
 835 def : ProcessorModel<"tsv110", CortexA57Model, [ProcTSV110]>;
 836
 837 // Alias for the latest Apple processor model supported by LLVM.
 838 def : ProcessorModel<"apple-latest", CycloneModel, [ProcCyclone]>;
 839
 840 //===----------------------------------------------------------------------===//
 841 // Assembly parser
 842 //===----------------------------------------------------------------------===//
 843
 844 def GenericAsmParserVariant : AsmParserVariant {
 845   int Variant = 0;
 846   string Name = "generic";
 847   string BreakCharacters = ".";
 848   string TokenizingCharacters = "[]*!/";
 849 }
 850
 851 def AppleAsmParserVariant : AsmParserVariant {
 852   int Variant = 1;
 853   string Name = "apple-neon";
 854   string BreakCharacters = ".";
 855   string TokenizingCharacters = "[]*!/";
 856 }
 857
 858 //===----------------------------------------------------------------------===//
 859 // Assembly printer
 860 //===----------------------------------------------------------------------===//
 861 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 862 // AsmWriter bits get associated with the correct class.
 863 def GenericAsmWriter : AsmWriter {
 864   string AsmWriterClassName  = "InstPrinter";
 865   int PassSubtarget = 1;
 866   int Variant = 0;
 867   bit isMCAsmWriter = 1;
 868 }
 869
 870 def AppleAsmWriter : AsmWriter {
 871   let AsmWriterClassName = "AppleInstPrinter";
 872   int PassSubtarget = 1;
 873   int Variant = 1;
 874   int isMCAsmWriter = 1;
 875 }
 876
 877 //===----------------------------------------------------------------------===//
 878 // Target Declaration
 879 //===----------------------------------------------------------------------===//
 880
 881 def AArch64 : Target {
 882   let InstructionSet = AArch64InstrInfo;
 883   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 884   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 885   let AllowRegisterRenaming = 1;
 886 }
 887
 888 //===----------------------------------------------------------------------===//
 889 // Pfm Counters
 890 //===----------------------------------------------------------------------===//
 891
 892 include "AArch64PfmCounters.td"