lib/Target/AArch64/AArch64LegalizerInfo.h

   1 //===- AArch64LegalizerInfo --------------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the Machinelegalizer class for
  10 /// AArch64.
  11 /// \todo This should be generated by TableGen.
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H
  15 #define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H
  16
  17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
  18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  19
  20 namespace llvm {
  21
  22 class LLVMContext;
  23 class AArch64Subtarget;
  24
  25 /// This class provides the information for the target register banks.
  26 class AArch64LegalizerInfo : public LegalizerInfo {
  27 public:
  28   AArch64LegalizerInfo(const AArch64Subtarget &ST);
  29
  30   bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
  31                       MachineIRBuilder &MIRBuilder,
  32                       GISelChangeObserver &Observer) const override;
  33
  34   bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
  35                          MachineIRBuilder &MIRBuilder) const override;
  36
  37 private:
  38   bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
  39                      MachineIRBuilder &MIRBuilder) const;
  40   bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
  41                          MachineIRBuilder &MIRBuilder,
  42                          GISelChangeObserver &Observer) const;
  43   bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
  44                            MachineIRBuilder &MIRBuilder,
  45                            GISelChangeObserver &Observer) const;
  46 };
  47 } // End llvm namespace.
  48 #endif