lib/Target/AArch64/AArch64RegisterInfo.h

   1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl --*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the AArch64 implementation of the MRegisterInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
  14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERINFO_H
  15
  16 #define GET_REGINFO_HEADER
  17 #include "AArch64GenRegisterInfo.inc"
  18
  19 namespace llvm {
  20
  21 class MachineFunction;
  22 class RegScavenger;
  23 class TargetRegisterClass;
  24 class Triple;
  25
  26 class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
  27   const Triple &TT;
  28
  29 public:
  30   AArch64RegisterInfo(const Triple &TT);
  31
  32   // FIXME: This should be tablegen'd like getDwarfRegNum is
  33   int getSEHRegNum(unsigned i) const {
  34     return getEncodingValue(i);
  35   }
  36
  37   bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
  38   bool isAnyArgRegReserved(const MachineFunction &MF) const;
  39   void emitReservedArgRegCallError(const MachineFunction &MF) const;
  40
  41   void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const;
  42   void UpdateCustomCallPreservedMask(MachineFunction &MF,
  43                                      const uint32_t **Mask) const;
  44
  45   /// Code Generation virtual methods...
  46   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  47   const MCPhysReg *
  48   getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
  49   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
  50                                        CallingConv::ID) const override;
  51
  52   unsigned getCSRFirstUseCost() const override {
  53     // The cost will be compared against BlockFrequency where entry has the
  54     // value of 1 << 14. A value of 5 will choose to spill or split really
  55     // cold path instead of using a callee-saved register.
  56     return 5;
  57   }
  58
  59   const TargetRegisterClass *
  60   getSubClassWithSubReg(const TargetRegisterClass *RC,
  61                         unsigned Idx) const override;
  62
  63   // Calls involved in thread-local variable lookup save more registers than
  64   // normal calls, so they need a different mask to represent this.
  65   const uint32_t *getTLSCallPreservedMask() const;
  66
  67   // Funclets on ARM64 Windows don't preserve any registers.
  68   const uint32_t *getNoPreservedMask() const override;
  69
  70   /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
  71   /// case that 'returned' is on an i64 first argument if the calling convention
  72   /// is one that can (partially) model this attribute with a preserved mask
  73   /// (i.e. it is a calling convention that uses the same register for the first
  74   /// i64 argument and an i64 return value)
  75   ///
  76   /// Should return NULL in the case that the calling convention does not have
  77   /// this property
  78   const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
  79                                              CallingConv::ID) const;
  80
  81   /// Stack probing calls preserve different CSRs to the normal CC.
  82   const uint32_t *getWindowsStackProbePreservedMask() const;
  83
  84   BitVector getReservedRegs(const MachineFunction &MF) const override;
  85   bool isAsmClobberable(const MachineFunction &MF,
  86                        unsigned PhysReg) const override;
  87   bool isConstantPhysReg(unsigned PhysReg) const override;
  88   const TargetRegisterClass *
  89   getPointerRegClass(const MachineFunction &MF,
  90                      unsigned Kind = 0) const override;
  91   const TargetRegisterClass *
  92   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
  93
  94   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
  95   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
  96   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
  97
  98   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
  99   bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
 100                           int64_t Offset) const override;
 101   void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
 102                                     int FrameIdx,
 103                                     int64_t Offset) const override;
 104   void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
 105                          int64_t Offset) const override;
 106   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
 107                            unsigned FIOperandNum,
 108                            RegScavenger *RS = nullptr) const override;
 109   bool cannotEliminateFrame(const MachineFunction &MF) const;
 110
 111   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
 112   bool hasBasePointer(const MachineFunction &MF) const;
 113   unsigned getBaseRegister() const;
 114
 115   // Debug information queries.
 116   Register getFrameRegister(const MachineFunction &MF) const override;
 117
 118   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
 119                                MachineFunction &MF) const override;
 120
 121   bool trackLivenessAfterRegAlloc(const MachineFunction&) const override {
 122     return true;
 123   }
 124
 125   unsigned getLocalAddressRegister(const MachineFunction &MF) const;
 126 };
 127
 128 } // end namespace llvm
 129
 130 #endif