1 //=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for ARM Cortex-A57 to support
10 // instruction scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // The Cortex-A57 is a traditional superscalar microprocessor with a
16 // conservative 3-wide in-order stage for decode and dispatch. Combined with the
17 // much wider out-of-order issue stage, this produced a need to carefully
18 // schedule micro-ops so that all three decoded each cycle are successfully
19 // issued as the reservation station(s) simply don't stay occupied for long.
20 // Therefore, IssueWidth is set to the narrower of the two at three, while still
21 // modeling the machine as out-of-order.
23 def CortexA57Model : SchedMachineModel {
24 let IssueWidth = 3; // 3-way decode and dispatch
25 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
26 let LoadLatency = 4; // Optimistic load latency
27 let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
29 // Enable partial & runtime unrolling. The magic number is chosen based on
30 // experiments and benchmarking data.
31 let LoopMicroOpBufferSize = 16;
32 let CompleteModel = 1;
34 list<Predicate> UnsupportedFeatures = SVEUnsupported.F;
37 //===----------------------------------------------------------------------===//
38 // Define each kind of processor resource and number available on Cortex-A57.
39 // Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
40 // micro-ops wait for their operands and then issue out-of-order.
42 def A57UnitB : ProcResource<1>; // Type B micro-ops
43 def A57UnitI : ProcResource<2>; // Type I micro-ops
44 def A57UnitM : ProcResource<1>; // Type M micro-ops
45 def A57UnitL : ProcResource<1>; // Type L micro-ops
46 def A57UnitS : ProcResource<1>; // Type S micro-ops
47 def A57UnitX : ProcResource<1>; // Type X micro-ops
48 def A57UnitW : ProcResource<1>; // Type W micro-ops
49 let SchedModel = CortexA57Model in {
50 def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
53 let SchedModel = CortexA57Model in {
55 //===----------------------------------------------------------------------===//
56 // Define customized scheduler read/write types specific to the Cortex-A57.
58 include "AArch64SchedA57WriteRes.td"
60 //===----------------------------------------------------------------------===//
61 // Map the target-defined scheduler read/write resources and latency for
62 // Cortex-A57. The Cortex-A57 types are directly associated with resources, so
63 // defining the aliases precludes the need for mapping them using WriteRes. The
64 // aliases are sufficient for creating a coarse, working model. As the model
65 // evolves, InstRWs will be used to override some of these SchedAliases.
67 // WARNING: Using SchedAliases is convenient and works well for latency and
68 // resource lookup for instructions. However, this creates an entry in
69 // AArch64WriteLatencyTable with a WriteResourceID of 0, breaking
70 // any SchedReadAdvance since the lookup will fail.
72 def : SchedAlias<WriteImm, A57Write_1cyc_1I>;
73 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
74 def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
75 def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
76 def : SchedAlias<WriteExtr, A57Write_1cyc_1I>;
77 def : SchedAlias<WriteIS, A57Write_1cyc_1I>;
78 def : SchedAlias<WriteID32, A57Write_19cyc_1M>;
79 def : SchedAlias<WriteID64, A57Write_35cyc_1M>;
80 def : WriteRes<WriteIM32, [A57UnitM]> { let Latency = 3; }
81 def : WriteRes<WriteIM64, [A57UnitM]> { let Latency = 5; }
82 def : SchedAlias<WriteBr, A57Write_1cyc_1B>;
83 def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
84 def : SchedAlias<WriteLD, A57Write_4cyc_1L>;
85 def : SchedAlias<WriteST, A57Write_1cyc_1S>;
86 def : SchedAlias<WriteSTP, A57Write_1cyc_1S>;
87 def : SchedAlias<WriteAdr, A57Write_1cyc_1I>;
88 def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
89 def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
90 def : SchedAlias<WriteF, A57Write_3cyc_1V>;
91 def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>;
92 def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>;
93 def : SchedAlias<WriteFCopy, A57Write_5cyc_1L>;
94 def : SchedAlias<WriteFImm, A57Write_3cyc_1V>;
95 def : SchedAlias<WriteFMul, A57Write_5cyc_1V>;
96 def : SchedAlias<WriteFDiv, A57Write_17cyc_1W>;
97 def : SchedAlias<WriteV, A57Write_3cyc_1V>;
98 def : SchedAlias<WriteVLD, A57Write_5cyc_1L>;
99 def : SchedAlias<WriteVST, A57Write_1cyc_1S>;
101 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
103 def : WriteRes<WriteSys, []> { let Latency = 1; }
104 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
105 def : WriteRes<WriteHint, []> { let Latency = 1; }
107 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
109 // Forwarding logic is only modeled for multiply and accumulate
110 def : ReadAdvance<ReadI, 0>;
111 def : ReadAdvance<ReadISReg, 0>;
112 def : ReadAdvance<ReadIEReg, 0>;
113 def : ReadAdvance<ReadIM, 0>;
114 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
115 def : ReadAdvance<ReadID, 0>;
116 def : ReadAdvance<ReadExtrHi, 0>;
117 def : ReadAdvance<ReadAdrBase, 0>;
118 def : ReadAdvance<ReadVLD, 0>;
121 //===----------------------------------------------------------------------===//
122 // Specialize the coarse model by associating instruction groups with the
123 // subtarget-defined types. As the modeled is refined, this will override most
124 // of the above ShchedAlias mappings.
127 // -----------------------------------------------------------------------------
129 def : InstRW<[WriteI], (instrs COPY)>;
132 // Branch Instructions
133 // -----------------------------------------------------------------------------
135 def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
136 def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
139 // Shifted Register with Shift == 0
140 // ----------------------------------------------------------------------------
142 def A57WriteISReg : SchedWriteVariant<[
143 SchedVar<RegShiftedPred, [WriteISReg]>,
144 SchedVar<NoSchedPred, [WriteI]>]>;
145 def : InstRW<[A57WriteISReg], (instregex ".*rs$")>;
148 // Divide and Multiply Instructions
149 // -----------------------------------------------------------------------------
152 def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
155 // Miscellaneous Data-Processing Instructions
156 // -----------------------------------------------------------------------------
158 def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
159 def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
160 def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
163 // Cryptography Extensions
164 // -----------------------------------------------------------------------------
166 def A57ReadAES : SchedReadAdvance<3, [A57Write_3cyc_1W]>;
167 def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>;
168 def : InstRW<[A57Write_3cyc_1W, A57ReadAES], (instregex "^AESI?MC")>;
169 def : InstRW<[A57Write_6cyc_2V], (instregex "^SHA1SU0")>;
170 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA1(H|SU1)")>;
171 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA1[CMP]")>;
172 def : InstRW<[A57Write_3cyc_1W], (instregex "^SHA256SU0")>;
173 def : InstRW<[A57Write_6cyc_2W], (instregex "^SHA256(H|H2|SU1)")>;
174 def : InstRW<[A57Write_3cyc_1W], (instregex "^CRC32")>;
178 // -----------------------------------------------------------------------------
180 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>;
181 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
182 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>;
183 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>;
185 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>;
186 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
187 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>;
188 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>;
189 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
190 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
192 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
193 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
194 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
195 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
196 def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
197 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
198 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
199 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
200 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
201 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
202 def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
203 def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
204 def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
205 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
206 def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
207 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
209 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>;
210 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
211 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>;
212 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>;
213 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>;
214 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>;
216 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>;
217 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>;
218 def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>;
219 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>;
220 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
221 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
223 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>;
224 def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
225 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>;
226 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
227 def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>;
228 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>;
230 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>;
231 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
232 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>;
233 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>;
234 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>;
235 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>;
237 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>;
238 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>;
239 def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>;
240 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>;
241 def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>;
242 def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>;
243 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>;
244 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
246 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>;
247 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
248 def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>;
249 def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
250 def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>;
251 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
253 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>;
254 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
255 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>;
256 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>;
257 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>;
258 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
260 def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>;
261 def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>;
262 def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>;
263 def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>;
264 def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>;
265 def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>;
266 def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>;
267 def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
269 def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>;
270 def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
271 def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>;
272 def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
273 def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>;
274 def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
277 // -----------------------------------------------------------------------------
279 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>;
280 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>;
281 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>;
282 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
284 def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
285 def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
286 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
287 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
288 def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
289 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
290 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
291 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
292 def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
293 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
294 def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
295 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
296 def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
297 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
298 def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
299 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
301 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>;
302 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
303 def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>;
304 def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
306 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>;
307 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
308 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>;
309 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
310 def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>;
311 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>;
313 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>;
314 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>;
315 def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>;
316 def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
317 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>;
318 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
320 def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
321 def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
322 def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>;
323 def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
324 def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>;
325 def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
327 def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>;
328 def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>;
329 def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>;
330 def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
331 def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>;
332 def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>;
334 def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>;
335 def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
336 def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>;
337 def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
338 def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>;
339 def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
342 // -----------------------------------------------------------------------------
344 // Reference for forms in this group
345 // D form - v8i8, v4i16, v2i32
346 // Q form - v16i8, v8i16, v4i32
347 // D form - v1i8, v1i16, v1i32, v1i64
348 // Q form - v16i8, v8i16, v4i32, v2i64
349 // D form - v8i8_v8i16, v4i16_v4i32, v2i32_v2i64
350 // Q form - v16i8_v8i16, v8i16_v4i32, v4i32_v2i64
352 // ASIMD absolute diff accum, D-form
353 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
354 // ASIMD absolute diff accum, Q-form
355 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
356 // ASIMD absolute diff accum long
357 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABAL")>;
359 // ASIMD arith, reduce, 4H/4S
360 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
361 // ASIMD arith, reduce, 8B/8H
362 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
363 // ASIMD arith, reduce, 16B
364 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>;
366 // ASIMD max/min, reduce, 4H/4S
367 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU](MIN|MAX)V(v4i16|v4i32)v$")>;
368 // ASIMD max/min, reduce, 8B/8H
369 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
370 // ASIMD max/min, reduce, 16B
371 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU](MIN|MAX)Vv16i8v$")>;
373 // ASIMD multiply, D-form
374 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
375 // ASIMD multiply, Q-form
376 def : InstRW<[A57Write_6cyc_2W], (instregex "^(P?MUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
378 // ASIMD multiply accumulate, D-form
379 def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
380 // ASIMD multiply accumulate, Q-form
381 def : InstRW<[A57Write_6cyc_2W], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
383 // ASIMD multiply accumulate long
384 // ASIMD multiply accumulate saturating long
385 def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
386 def A57ReadIVMA4 : SchedReadAdvance<4, [A57WriteIVMA]>;
387 def : InstRW<[A57WriteIVMA, A57ReadIVMA4], (instregex "^(S|U|SQD)ML[AS]L")>;
389 // ASIMD multiply long
390 def : InstRW<[A57Write_5cyc_1W], (instregex "^(S|U|SQD)MULL")>;
391 def : InstRW<[A57Write_5cyc_1W], (instregex "^PMULL(v8i8|v16i8)")>;
392 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
394 // ASIMD pairwise add and accumulate
395 // ASIMD shift accumulate
396 def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
397 def A57ReadIVA3 : SchedReadAdvance<3, [A57WriteIVA]>;
398 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^[SU]ADALP")>;
399 def : InstRW<[A57WriteIVA, A57ReadIVA3], (instregex "^(S|SR|U|UR)SRA")>;
401 // ASIMD shift by immed, complex
402 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?(Q|R){1,2}SHR")>;
403 def : InstRW<[A57Write_4cyc_1X], (instregex "^SQSHLU")>;
406 // ASIMD shift by register, basic, Q-form
407 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
409 // ASIMD shift by register, complex, D-form
410 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
412 // ASIMD shift by register, complex, Q-form
413 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i32|v2i64)")>;
416 // Vector - Floating Point
417 // -----------------------------------------------------------------------------
419 // Reference for forms in this group
421 // Q form - v4f32, v2f64
423 // D form - v1i32, v1i64
425 // Q form - v4i32, v2i64
427 // ASIMD FP arith, normal, D-form
428 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FABD|FADD|FSUB)(v2f32|32|64|v2i32p)")>;
429 // ASIMD FP arith, normal, Q-form
430 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
432 // ASIMD FP arith, pairwise, D-form
433 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
434 // ASIMD FP arith, pairwise, Q-form
435 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
437 // ASIMD FP compare, D-form
438 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
439 // ASIMD FP compare, Q-form
440 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
442 // ASIMD FP convert, long and narrow
443 def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
444 // ASIMD FP convert, other, D-form
445 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
446 // ASIMD FP convert, other, Q-form
447 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
449 // ASIMD FP divide, D-form, F32
450 def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>;
451 // ASIMD FP divide, Q-form, F32
452 def : InstRW<[A57Write_34cyc_2W], (instregex "FDIVv4f32")>;
453 // ASIMD FP divide, Q-form, F64
454 def : InstRW<[A57Write_64cyc_2W], (instregex "FDIVv2f64")>;
456 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
457 // ASIMD FP square root, D-form, F32
458 def : InstRW<[A57Write_17cyc_1W], (instregex "FSQRTv2f32")>;
459 // ASIMD FP square root, Q-form, F32
460 def : InstRW<[A57Write_34cyc_2W], (instregex "FSQRTv4f32")>;
461 // ASIMD FP square root, Q-form, F64
462 def : InstRW<[A57Write_64cyc_2W], (instregex "FSQRTv2f64")>;
464 // ASIMD FP max/min, normal, D-form
465 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
466 // ASIMD FP max/min, normal, Q-form
467 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
468 // ASIMD FP max/min, pairwise, D-form
469 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
470 // ASIMD FP max/min, pairwise, Q-form
471 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
472 // ASIMD FP max/min, reduce
473 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
475 // ASIMD FP multiply, D-form, FZ
476 def : InstRW<[A57Write_5cyc_1V], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
477 // ASIMD FP multiply, Q-form, FZ
478 def : InstRW<[A57Write_5cyc_2V], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
480 // ASIMD FP multiply accumulate, D-form, FZ
481 // ASIMD FP multiply accumulate, Q-form, FZ
482 def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
483 def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; }
484 def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>;
485 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
486 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
488 // ASIMD FP round, D-form
489 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT[AIMNPXZ](v2f32)")>;
490 // ASIMD FP round, Q-form
491 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
494 // Vector - Miscellaneous
495 // -----------------------------------------------------------------------------
497 // Reference for forms in this group
498 // D form - v8i8, v4i16, v2i32
499 // Q form - v16i8, v8i16, v4i32
500 // D form - v1i8, v1i16, v1i32, v1i64
501 // Q form - v16i8, v8i16, v4i32, v2i64
503 // ASIMD bitwise insert, Q-form
504 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL)v16i8")>;
506 // ASIMD duplicate, gen reg, D-form and Q-form
507 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^CPY")>;
508 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUPv.+gpr")>;
510 // ASIMD move, saturating
511 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]QXTU?N")>;
513 // ASIMD reciprocal estimate, D-form
514 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f32|v1i32|v2i32|v1i64)")>;
515 // ASIMD reciprocal estimate, Q-form
516 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FU](RECP|RSQRT)(E|X)(v2f64|v4f32|v4i32)")>;
518 // ASIMD reciprocal step, D-form, FZ
519 def : InstRW<[A57Write_9cyc_1V], (instregex "^F(RECP|RSQRT)S(v2f32|v1i32|v2i32|v1i64|32|64)")>;
520 // ASIMD reciprocal step, Q-form, FZ
521 def : InstRW<[A57Write_9cyc_2V], (instregex "^F(RECP|RSQRT)S(v2f64|v4f32|v4i32)")>;
523 // ASIMD table lookup, D-form
524 def : InstRW<[A57Write_3cyc_1V], (instregex "^TB[LX]v8i8One")>;
525 def : InstRW<[A57Write_6cyc_2V], (instregex "^TB[LX]v8i8Two")>;
526 def : InstRW<[A57Write_9cyc_3V], (instregex "^TB[LX]v8i8Three")>;
527 def : InstRW<[A57Write_12cyc_4V], (instregex "^TB[LX]v8i8Four")>;
528 // ASIMD table lookup, Q-form
529 def : InstRW<[A57Write_6cyc_3V], (instregex "^TB[LX]v16i8One")>;
530 def : InstRW<[A57Write_9cyc_5V], (instregex "^TB[LX]v16i8Two")>;
531 def : InstRW<[A57Write_12cyc_7V], (instregex "^TB[LX]v16i8Three")>;
532 def : InstRW<[A57Write_15cyc_9V], (instregex "^TB[LX]v16i8Four")>;
534 // ASIMD transfer, element to gen reg
535 def : InstRW<[A57Write_6cyc_1I_1L], (instregex "^[SU]MOVv")>;
537 // ASIMD transfer, gen reg to element
538 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^INSv")>;
540 // ASIMD unzip/zip, Q-form
541 def : InstRW<[A57Write_6cyc_3V], (instregex "^(UZP|ZIP)(1|2)(v16i8|v8i16|v4i32|v2i64)")>;
545 // -----------------------------------------------------------------------------
547 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(ADD|SUB)[DS]rr")>;
549 def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
550 def A57ReadFPMA5 : SchedReadAdvance<5, [A57WriteFPMA]>;
551 def A57ReadFPM : SchedReadAdvance<0>;
552 def : InstRW<[A57WriteFPMA, A57ReadFPM, A57ReadFPM, A57ReadFPMA5], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
554 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
555 def : InstRW<[A57Write_10cyc_1L_1V], (instregex "^[SU]CVTF")>;
557 def : InstRW<[A57Write_32cyc_1W], (instrs FDIVDrr)>;
558 def : InstRW<[A57Write_17cyc_1W], (instrs FDIVSrr)>;
560 def : InstRW<[A57Write_5cyc_1V], (instregex "^F(MAX|MIN).+rr")>;
562 def : InstRW<[A57Write_5cyc_1V], (instregex "^FRINT.+r")>;
564 def : InstRW<[A57Write_32cyc_1W], (instrs FSQRTDr)>;
565 def : InstRW<[A57Write_17cyc_1W], (instrs FSQRTSr)>;
567 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPDi)>;
568 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDNPQi)>;
569 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDNPSi)>;
570 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPDi)>;
571 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpost)>;
572 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPDpre)>;
573 def : InstRW<[A57Write_6cyc_2L, WriteLDHi], (instrs LDPQi)>;
574 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpost)>;
575 def : InstRW<[A57Write_6cyc_2L, WriteLDHi, WriteAdr], (instrs LDPQpre)>;
576 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi], (instrs LDPSWi)>;
577 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpost)>;
578 def : InstRW<[A57Write_5cyc_1I_2L, WriteLDHi, WriteAdr], (instrs LDPSWpre)>;
579 def : InstRW<[A57Write_5cyc_1L, WriteLDHi], (instrs LDPSi)>;
580 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpost)>;
581 def : InstRW<[A57Write_5cyc_1L, WriteLDHi, WriteAdr], (instrs LDPSpre)>;
582 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
583 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRBpre)>;
584 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroW)>;
585 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRBroX)>;
586 def : InstRW<[A57Write_5cyc_1L], (instrs LDRBui)>;
587 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDl)>;
588 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
589 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRDpre)>;
590 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroW)>;
591 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRDroX)>;
592 def : InstRW<[A57Write_5cyc_1L], (instrs LDRDui)>;
593 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroW)>;
594 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRHHroX)>;
595 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
596 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRHpre)>;
597 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroW)>;
598 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRHroX)>;
599 def : InstRW<[A57Write_5cyc_1L], (instrs LDRHui)>;
600 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQl)>;
601 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
602 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRQpre)>;
603 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroW)>;
604 def : InstRW<[A57Write_6cyc_1I_1L, ReadAdrBase], (instrs LDRQroX)>;
605 def : InstRW<[A57Write_5cyc_1L], (instrs LDRQui)>;
606 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroW)>;
607 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHWroX)>;
608 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroW)>;
609 def : InstRW<[A57Write_5cyc_1I_1L, ReadAdrBase], (instrs LDRSHXroX)>;
610 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSl)>;
611 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
612 def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instrs LDRSpre)>;
613 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroW)>;
614 def : InstRW<[A57Write_5cyc_1L, ReadAdrBase], (instrs LDRSroX)>;
615 def : InstRW<[A57Write_5cyc_1L], (instrs LDRSui)>;
616 def : InstRW<[A57Write_5cyc_1L], (instrs LDURBi)>;
617 def : InstRW<[A57Write_5cyc_1L], (instrs LDURDi)>;
618 def : InstRW<[A57Write_5cyc_1L], (instrs LDURHi)>;
619 def : InstRW<[A57Write_5cyc_1L], (instrs LDURQi)>;
620 def : InstRW<[A57Write_5cyc_1L], (instrs LDURSi)>;
622 def : InstRW<[A57Write_2cyc_2S], (instrs STNPDi)>;
623 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STNPQi)>;
624 def : InstRW<[A57Write_2cyc_2S], (instrs STNPXi)>;
625 def : InstRW<[A57Write_2cyc_2S], (instrs STPDi)>;
626 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpost)>;
627 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPDpre)>;
628 def : InstRW<[A57Write_4cyc_1I_4S], (instrs STPQi)>;
629 def : InstRW<[WriteAdr, A57Write_4cyc_1I_4S], (instrs STPQpost)>;
630 def : InstRW<[WriteAdr, A57Write_4cyc_2I_4S], (instrs STPQpre)>;
631 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpost)>;
632 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPSpre)>;
633 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpost)>;
634 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STPWpre)>;
635 def : InstRW<[A57Write_2cyc_2S], (instrs STPXi)>;
636 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpost)>;
637 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STPXpre)>;
638 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpost)>;
639 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBBpre)>;
640 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRBpost)>;
641 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRBpre)>;
642 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroW)>;
643 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRBroX)>;
644 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRDpost)>;
645 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRDpre)>;
646 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpost)>;
647 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHHpre)>;
648 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroW)>;
649 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHHroX)>;
650 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRHpost)>;
651 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRHpre)>;
652 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroW)>;
653 def : InstRW<[A57Write_3cyc_1I_1S, ReadAdrBase], (instrs STRHroX)>;
654 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQpost)>;
655 def : InstRW<[WriteAdr, A57Write_2cyc_1I_2S], (instrs STRQpre)>;
656 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroW)>;
657 def : InstRW<[A57Write_2cyc_1I_2S, ReadAdrBase], (instrs STRQroX)>;
658 def : InstRW<[A57Write_2cyc_1I_2S], (instrs STRQui)>;
659 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRSpost)>;
660 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S], (instrs STRSpre)>;
661 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpost)>;
662 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRWpre)>;
663 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpost)>;
664 def : InstRW<[WriteAdr, A57Write_1cyc_1I_1S, ReadAdrBase], (instrs STRXpre)>;
665 def : InstRW<[A57Write_2cyc_2S], (instrs STURQi)>;
667 } // SchedModel = CortexA57Model