1 //=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the machine model for the Samsung Exynos M3 to support
10 // instruction scheduling and other instruction cost heuristics.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide
16 // in-order stage for decode and dispatch and a wider issue stage.
17 // The execution units and loads and stores are out-of-order.
19 def ExynosM3Model : SchedMachineModel {
20 let IssueWidth = 6; // Up to 6 uops per cycle.
21 let MicroOpBufferSize = 228; // ROB size.
22 let LoopMicroOpBufferSize = 40; // Based on the instruction queue size.
23 let LoadLatency = 4; // Optimistic load cases.
24 let MispredictPenalty = 16; // Minimum branch misprediction penalty.
25 let CompleteModel = 1; // Use the default model otherwise.
27 list<Predicate> UnsupportedFeatures = SVEUnsupported.F;
30 //===----------------------------------------------------------------------===//
31 // Define each kind of processor resource and number available on the Exynos-M3,
32 // which has 12 pipelines, each with its own queue with out-of-order dispatch.
34 let SchedModel = ExynosM3Model in {
36 def M3UnitA : ProcResource<2>; // Simple integer
37 def M3UnitC : ProcResource<2>; // Simple and complex integer
38 def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized)
39 def M3UnitB : ProcResource<2>; // Branch
40 def M3UnitL : ProcResource<2>; // Load
41 def M3UnitS : ProcResource<1>; // Store
42 def M3PipeF0 : ProcResource<1>; // FP #0
43 let Super = M3PipeF0 in {
44 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication
45 def M3UnitFADD0 : ProcResource<1>; // Simple FP
46 def M3UnitFCVT0 : ProcResource<1>; // FP conversion
47 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized)
48 def M3UnitNALU0 : ProcResource<1>; // Simple vector
49 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea
50 def M3UnitNSHT0 : ProcResource<1>; // Vector shifting
51 def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling
53 def M3PipeF1 : ProcResource<1>; // FP #1
54 let Super = M3PipeF1 in {
55 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication
56 def M3UnitFADD1 : ProcResource<1>; // Simple FP
57 def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized)
58 def M3UnitFCVT1 : ProcResource<1>; // FP conversion
59 def M3UnitFST0 : ProcResource<1>; // FP store
60 def M3UnitNALU1 : ProcResource<1>; // Simple vector
61 def M3UnitNCRY0 : ProcResource<1>; // Cryptographic
62 def M3UnitNMUL : ProcResource<1>; // Vector multiplication
63 def M3UnitNSHT1 : ProcResource<1>; // Vector shifting
64 def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling
66 def M3PipeF2 : ProcResource<1>; // FP #2
67 let Super = M3PipeF2 in {
68 def M3UnitFMAC2 : ProcResource<1>; // FP multiplication
69 def M3UnitFADD2 : ProcResource<1>; // Simple FP
70 def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized)
71 def M3UnitFST1 : ProcResource<1>; // FP store
72 def M3UnitNALU2 : ProcResource<1>; // Simple vector
73 def M3UnitNCRY1 : ProcResource<1>; // Cryptographic
74 def M3UnitNSHT2 : ProcResource<1>; // Vector shifting
75 def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling
79 def M3UnitALU : ProcResGroup<[M3UnitA,
81 def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0,
84 def M3UnitFADD : ProcResGroup<[M3UnitFADD0,
87 def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0,
89 def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0,
91 def M3UnitFST : ProcResGroup<[M3UnitFST0,
93 def M3UnitNALU : ProcResGroup<[M3UnitNALU0,
96 def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0,
98 def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0,
101 def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
105 //===----------------------------------------------------------------------===//
106 // Coarse scheduling model.
108 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
109 let NumMicroOps = 1; }
110 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
111 let NumMicroOps = 0; }
113 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
114 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
115 let ResourceCycles = [2]; }
116 def M3WriteAB : SchedWriteRes<[M3UnitALU,
117 M3UnitC]> { let Latency = 1;
118 let NumMicroOps = 2; }
119 def M3WriteAC : SchedWriteRes<[M3UnitALU,
121 M3UnitC]> { let Latency = 2;
122 let NumMicroOps = 3; }
123 def M3WriteAD : SchedWriteRes<[M3UnitALU,
124 M3UnitC]> { let Latency = 2;
125 let NumMicroOps = 2; }
126 def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; }
127 def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; }
128 def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
129 SchedVar<ExynosArithPred, [M3WriteA1]>,
130 SchedVar<ExynosLogicPred, [M3WriteA1]>,
131 SchedVar<NoSchedPred, [M3WriteAA]>]>;
132 def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>,
133 SchedVar<NoSchedPred, [M3WriteAA]>]>;
134 def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>,
135 SchedVar<NoSchedPred, [M3WriteAA]>]>;
136 def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
137 SchedVar<ExynosLogicPred, [M3WriteA1]>,
138 SchedVar<NoSchedPred, [M3WriteAA]>]>;
139 def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
140 SchedVar<NoSchedPred, [M3WriteAA]>]>;
142 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
143 def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,
144 SchedVar<NoSchedPred, [M3WriteAB]>]>;
146 def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
147 def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
148 def M3WriteLA : SchedWriteRes<[M3UnitL,
149 M3UnitL]> { let Latency = 5;
150 let NumMicroOps = 1; }
151 def M3WriteLB : SchedWriteRes<[M3UnitA,
152 M3UnitL]> { let Latency = 5;
153 let NumMicroOps = 2; }
154 def M3WriteLC : SchedWriteRes<[M3UnitA,
156 M3UnitL]> { let Latency = 5;
157 let NumMicroOps = 2; }
158 def M3WriteLD : SchedWriteRes<[M3UnitA,
159 M3UnitL]> { let Latency = 4;
160 let NumMicroOps = 2; }
161 def M3WriteLE : SchedWriteRes<[M3UnitA,
162 M3UnitL]> { let Latency = 6;
163 let NumMicroOps = 2; }
164 def M3WriteLH : SchedWriteRes<[]> { let Latency = 5;
165 let NumMicroOps = 0; }
166 def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>,
167 SchedVar<NoSchedPred, [M3WriteL4]>]>;
169 def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; }
170 def M3WriteSA : SchedWriteRes<[M3UnitA,
172 M3UnitFST]> { let Latency = 3;
173 let NumMicroOps = 2; }
174 def M3WriteSB : SchedWriteRes<[M3UnitA,
175 M3UnitS]> { let Latency = 2;
176 let NumMicroOps = 2; }
178 def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>,
179 SchedVar<NoSchedPred, [ReadDefault]>]>;
181 // Branch instructions.
182 def : SchedAlias<WriteBr, M3WriteZ0>;
183 def : SchedAlias<WriteBrReg, M3WriteC1>;
185 // Arithmetic and logical integer instructions.
186 def : SchedAlias<WriteI, M3WriteA1>;
187 def : SchedAlias<WriteISReg, M3WriteA1>;
188 def : SchedAlias<WriteIEReg, M3WriteA1>;
189 def : SchedAlias<WriteIS, M3WriteA1>;
191 // Move instructions.
192 def : SchedAlias<WriteImm, M3WriteA1>;
194 // Divide and multiply instructions.
195 def : WriteRes<WriteID32, [M3UnitC,
196 M3UnitD]> { let Latency = 12;
197 let ResourceCycles = [1, 12]; }
198 def : WriteRes<WriteID64, [M3UnitC,
199 M3UnitD]> { let Latency = 21;
200 let ResourceCycles = [1, 21]; }
201 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
202 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
203 let ResourceCycles = [2]; }
205 // Miscellaneous instructions.
206 def : SchedAlias<WriteExtr, M3WriteAY>;
209 def : SchedAlias<WriteAdr, M3WriteZ1>;
210 def : SchedAlias<ReadAdrBase, M3ReadAdrBase>;
212 // Load instructions.
213 def : SchedAlias<WriteLD, M3WriteL4>;
214 def : WriteRes<WriteLDHi, []> { let Latency = 4;
215 let NumMicroOps = 0; }
216 def : SchedAlias<WriteLDIdx, M3WriteLB>;
218 // Store instructions.
219 def : SchedAlias<WriteST, M3WriteS1>;
220 def : SchedAlias<WriteSTP, M3WriteS1>;
221 def : SchedAlias<WriteSTX, M3WriteS1>;
222 def : SchedAlias<WriteSTIdx, M3WriteSB>;
224 // FP data instructions.
225 def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; }
226 def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; }
227 def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12;
228 let ResourceCycles = [12]; }
229 def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; }
231 // FP miscellaneous instructions.
232 def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; }
233 def : WriteRes<WriteFImm, [M3UnitNALU]> { let Latency = 1; }
234 def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; }
236 // FP load instructions.
237 def : SchedAlias<WriteVLD, M3WriteL5>;
239 // FP store instructions.
240 def : WriteRes<WriteVST, [M3UnitS,
241 M3UnitFST]> { let Latency = 1;
242 let NumMicroOps = 1; }
244 // ASIMD FP instructions.
245 def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; }
247 // Other miscellaneous instructions.
248 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
249 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
250 def : WriteRes<WriteHint, []> { let Latency = 1; }
251 def : WriteRes<WriteSys, []> { let Latency = 1; }
253 //===----------------------------------------------------------------------===//
254 // Generic fast forwarding.
256 // TODO: Add FP register forwarding rules.
258 def : ReadAdvance<ReadI, 0>;
259 def : ReadAdvance<ReadISReg, 0>;
260 def : ReadAdvance<ReadIEReg, 0>;
261 def : ReadAdvance<ReadIM, 0>;
262 // TODO: The forwarding for 32 bits actually saves 2 cycles.
263 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
264 def : ReadAdvance<ReadID, 0>;
265 def : ReadAdvance<ReadExtrHi, 0>;
266 def : ReadAdvance<ReadAdrBase, 0>;
267 def : ReadAdvance<ReadVLD, 0>;
269 //===----------------------------------------------------------------------===//
270 // Finer scheduling model.
272 def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF,
273 M3UnitFADD]> { let Latency = 3;
274 let NumMicroOps = 2; }
275 def M3WriteNEONB : SchedWriteRes<[M3UnitNALU,
276 M3UnitFST]> { let Latency = 10;
277 let NumMicroOps = 2; }
278 def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF,
279 M3UnitFST]> { let Latency = 6;
280 let NumMicroOps = 2; }
281 def M3WriteNEONH : SchedWriteRes<[M3UnitNALU,
282 M3UnitS]> { let Latency = 5;
283 let NumMicroOps = 2; }
284 def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF,
285 M3UnitS]> { let Latency = 5;
286 let NumMicroOps = 2; }
287 def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0,
288 M3UnitFDIV1]> { let Latency = 7;
290 let ResourceCycles = [8, 8]; }
291 def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0,
292 M3UnitFDIV1]> { let Latency = 12;
294 let ResourceCycles = [13, 13]; }
295 def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR,
296 M3UnitFSQR]> { let Latency = 18;
298 let ResourceCycles = [19, 19]; }
299 def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR,
300 M3UnitFSQR]> { let Latency = 25;
302 let ResourceCycles = [26, 26]; }
303 def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC,
304 M3UnitNMSC]> { let Latency = 5;
305 let NumMicroOps = 2; }
306 def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; }
307 def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; }
308 def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; }
309 def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
310 def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
311 def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; }
312 def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7;
313 let ResourceCycles = [8]; }
314 def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12;
315 let ResourceCycles = [13]; }
316 def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; }
317 def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; }
318 def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; }
319 def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18;
320 let ResourceCycles = [19]; }
321 def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25;
322 let ResourceCycles = [26]; }
323 def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; }
324 def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
325 def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
326 def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; }
327 def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; }
328 def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; }
329 def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; }
330 def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; }
331 def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; }
332 def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; }
333 def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; }
334 def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; }
335 def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; }
336 def M3WriteVLDA : SchedWriteRes<[M3UnitL,
337 M3UnitL]> { let Latency = 5;
338 let NumMicroOps = 2; }
339 def M3WriteVLDB : SchedWriteRes<[M3UnitL,
341 M3UnitL]> { let Latency = 6;
342 let NumMicroOps = 3; }
343 def M3WriteVLDC : SchedWriteRes<[M3UnitL,
346 M3UnitL]> { let Latency = 6;
347 let NumMicroOps = 4; }
348 def M3WriteVLDD : SchedWriteRes<[M3UnitL,
349 M3UnitNALU]> { let Latency = 7;
351 let ResourceCycles = [2, 1]; }
352 def M3WriteVLDE : SchedWriteRes<[M3UnitL,
353 M3UnitNALU]> { let Latency = 6;
355 let ResourceCycles = [2, 1]; }
356 def M3WriteVLDF : SchedWriteRes<[M3UnitL,
357 M3UnitL]> { let Latency = 10;
359 let ResourceCycles = [5, 5]; }
360 def M3WriteVLDG : SchedWriteRes<[M3UnitL,
362 M3UnitNALU]> { let Latency = 7;
364 let ResourceCycles = [2, 1, 1]; }
365 def M3WriteVLDH : SchedWriteRes<[M3UnitL,
367 M3UnitNALU]> { let Latency = 6;
369 let ResourceCycles = [2, 1, 1]; }
370 def M3WriteVLDI : SchedWriteRes<[M3UnitL,
372 M3UnitL]> { let Latency = 12;
374 let ResourceCycles = [6, 6, 6]; }
375 def M3WriteVLDJ : SchedWriteRes<[M3UnitL,
378 M3UnitNALU]> { let Latency = 7;
380 let ResourceCycles = [2, 1, 1, 1]; }
381 def M3WriteVLDK : SchedWriteRes<[M3UnitL,
385 M3UnitNALU]> { let Latency = 9;
387 let ResourceCycles = [4, 1, 1, 1, 1]; }
388 def M3WriteVLDL : SchedWriteRes<[M3UnitL,
392 M3UnitNALU]> { let Latency = 6;
394 let ResourceCycles = [6, 1, 1, 6, 1]; }
395 def M3WriteVLDM : SchedWriteRes<[M3UnitL,
400 M3UnitNALU]> { let Latency = 7;
402 let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
403 def M3WriteVLDN : SchedWriteRes<[M3UnitL,
406 M3UnitL]> { let Latency = 14;
408 let ResourceCycles = [6, 6, 6, 6]; }
409 def M3WriteVSTA : WriteSequence<[WriteVST], 2>;
410 def M3WriteVSTB : WriteSequence<[WriteVST], 3>;
411 def M3WriteVSTC : WriteSequence<[WriteVST], 4>;
412 def M3WriteVSTD : SchedWriteRes<[M3UnitS,
415 M3UnitFST]> { let Latency = 7;
417 let ResourceCycles = [1, 3, 1, 3]; }
418 def M3WriteVSTE : SchedWriteRes<[M3UnitS,
423 M3UnitFST]> { let Latency = 8;
425 let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
426 def M3WriteVSTF : SchedWriteRes<[M3UnitNALU,
432 M3UnitFST]> { let Latency = 15;
434 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
435 def M3WriteVSTG : SchedWriteRes<[M3UnitNALU,
443 M3UnitFST]> { let Latency = 16;
445 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
446 def M3WriteVSTH : SchedWriteRes<[M3UnitNALU,
450 M3UnitFST]> { let Latency = 14;
452 let ResourceCycles = [1, 3, 3, 1, 3]; }
453 def M3WriteVSTI : SchedWriteRes<[M3UnitNALU,
461 M3UnitFST]> { let Latency = 17;
463 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
466 def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; }
467 def M3WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>,
468 SchedVar<NoSchedPred, [M3WriteZ0]>]>;
469 def M3WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>,
470 SchedVar<NoSchedPred, [M3WriteNALU1]>]>;
473 def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>;
474 def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4,
476 def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>;
478 // Branch instructions
479 def : InstRW<[M3WriteB1], (instrs Bcc)>;
480 def : InstRW<[M3WriteA1], (instrs BL)>;
481 def : InstRW<[M3WriteBX], (instrs BLR)>;
482 def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>;
483 def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>;
485 // Arithmetic and logical integer instructions.
486 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
487 def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>;
488 def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>;
489 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>;
490 def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>;
491 def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>;
493 // Move instructions.
494 def : InstRW<[M3WriteCOPY], (instrs COPY)>;
495 def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>;
496 def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>;
498 // Divide and multiply instructions.
500 // Miscellaneous instructions.
502 // Load instructions.
503 def : InstRW<[M3WriteLD,
505 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>;
506 def : InstRW<[M3WriteLB,
507 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
508 def : InstRW<[M3WriteLX,
509 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
510 def : InstRW<[M3WriteLB,
511 ReadAdrBase], (instrs PRFMroW)>;
512 def : InstRW<[M3WriteLX,
513 ReadAdrBase], (instrs PRFMroX)>;
515 // Store instructions.
516 def : InstRW<[M3WriteSB,
517 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
518 def : InstRW<[WriteST,
519 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
521 // FP data instructions.
522 def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>;
523 def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>;
524 def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>;
525 def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>;
526 def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>;
527 def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>;
528 def : InstRW<[M3WriteFMAC4,
529 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
530 def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>;
531 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>;
532 def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>;
533 def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>;
534 def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>;
536 // FP miscellaneous instructions.
537 def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>;
538 def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>;
539 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>;
540 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>;
541 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>;
542 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>;
543 def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>;
544 def : InstRW<[M3WriteFMAC4,
545 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
546 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>;
547 def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>;
548 def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>;
550 // FP load instructions.
551 def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
552 def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>;
553 def : InstRW<[WriteVLD,
554 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
555 def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
556 def : InstRW<[M3WriteLE,
557 ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
558 def : InstRW<[WriteVLD,
559 ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
560 def : InstRW<[M3WriteLE,
561 ReadAdrBase], (instregex "^LDRQro[WX]")>;
562 def : InstRW<[WriteVLD,
563 M3WriteLH], (instregex "^LDN?P[DS]i")>;
564 def : InstRW<[M3WriteLA,
565 M3WriteLH], (instregex "^LDN?PQi")>;
566 def : InstRW<[M3WriteLB,
568 WriteAdr], (instregex "^LDP[DS](post|pre)")>;
569 def : InstRW<[M3WriteLC,
571 WriteAdr], (instregex "^LDPQ(post|pre)")>;
573 // FP store instructions.
574 def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>;
575 def : InstRW<[WriteVST,
576 WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>;
577 def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>;
578 def : InstRW<[M3WriteSA,
579 ReadAdrBase], (instregex "^STR[BDHS]roW")>;
580 def : InstRW<[WriteVST,
581 ReadAdrBase], (instregex "^STR[BDHS]roX")>;
582 def : InstRW<[M3WriteSA,
583 ReadAdrBase], (instregex "^STRQro[WX]")>;
584 def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>;
585 def : InstRW<[WriteVST,
586 WriteAdr], (instregex "^STP[DS](post|pre)")>;
587 def : InstRW<[M3WriteSA,
588 WriteAdr], (instregex "^STPQ(post|pre)")>;
590 // ASIMD instructions.
591 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>;
592 def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>;
593 def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>;
594 def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>;
595 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>;
596 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>;
597 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>;
598 def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>;
599 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>;
600 def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>;
601 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>;
602 def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
603 def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>;
604 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
605 def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
606 def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
607 def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>;
608 def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>;
609 def : InstRW<[M3WriteNMUL3,
610 M3ReadNMUL], (instregex "^ML[AS]v")>;
611 def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>;
612 def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>;
613 def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>;
614 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>;
615 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>;
616 def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>;
617 def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>;
618 def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>;
619 def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>;
620 def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
621 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>;
622 def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>;
624 // ASIMD FP instructions.
625 def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>;
626 def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>;
627 def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>;
628 def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
629 def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>;
630 def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>;
631 def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>;
632 def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>;
633 def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>;
634 def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>;
635 def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>;
636 def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
637 def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>;
638 def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>;
639 def : InstRW<[M3WriteFMAC4,
640 M3ReadFMAC], (instregex "^FML[AS]v.f")>;
641 def : InstRW<[M3WriteFMAC5,
642 M3ReadFMAC], (instregex "^FML[AS]v.i")>;
643 def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>;
644 def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>;
645 def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>;
646 def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>;
647 def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>;
649 // ASIMD miscellaneous instructions.
650 def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>;
651 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>;
652 def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>;
653 def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>;
654 def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>;
655 def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>;
656 def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>;
657 def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>;
658 def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>;
659 def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>;
660 def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
661 def : InstRW<[M3WriteFMAC4,
662 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>;
663 def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>;
664 def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>;
665 def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>;
666 def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>;
667 def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>;
669 // ASIMD load instructions.
670 def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
671 def : InstRW<[M3WriteL5,
672 M3WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>;
673 def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
674 def : InstRW<[M3WriteL5,
675 M3WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>;
677 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
678 def : InstRW<[M3WriteVLDA,
679 M3WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>;
680 def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
681 def : InstRW<[M3WriteVLDA,
682 M3WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>;
684 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
685 def : InstRW<[M3WriteVLDB,
686 M3WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>;
687 def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
688 def : InstRW<[M3WriteVLDB,
689 M3WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>;
691 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
692 def : InstRW<[M3WriteVLDC,
693 M3WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>;
694 def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
695 def : InstRW<[M3WriteVLDC,
696 M3WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>;
698 def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>;
699 def : InstRW<[M3WriteVLDD,
700 M3WriteA1], (instregex "LD1i(8|16|32)_POST")>;
701 def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>;
702 def : InstRW<[M3WriteVLDE,
703 M3WriteA1], (instregex "LD1i(64)_POST")>;
705 def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
706 def : InstRW<[M3WriteL5,
707 M3WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>;
708 def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
709 def : InstRW<[M3WriteL5,
710 M3WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>;
712 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>;
713 def : InstRW<[M3WriteVLDF,
714 M3WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST")>;
715 def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
716 def : InstRW<[M3WriteVLDF,
717 M3WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>;
719 def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>;
720 def : InstRW<[M3WriteVLDG,
721 M3WriteA1], (instregex "LD2i(8|16|32)_POST")>;
722 def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>;
723 def : InstRW<[M3WriteVLDH,
724 M3WriteA1], (instregex "LD2i(64)_POST")>;
726 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
727 def : InstRW<[M3WriteVLDA,
728 M3WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>;
729 def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
730 def : InstRW<[M3WriteVLDA,
731 M3WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>;
733 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>;
734 def : InstRW<[M3WriteVLDI,
735 M3WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST")>;
736 def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
737 def : InstRW<[M3WriteVLDI,
738 M3WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>;
740 def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>;
741 def : InstRW<[M3WriteVLDJ,
742 M3WriteA1], (instregex "LD3i(8|16|32)_POST")>;
743 def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>;
744 def : InstRW<[M3WriteVLDL,
745 M3WriteA1], (instregex "LD3i(64)_POST")>;
747 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
748 def : InstRW<[M3WriteVLDB,
749 M3WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>;
750 def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
751 def : InstRW<[M3WriteVLDB,
752 M3WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>;
754 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>;
755 def : InstRW<[M3WriteVLDN,
756 M3WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST")>;
757 def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
758 def : InstRW<[M3WriteVLDN,
759 M3WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>;
761 def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>;
762 def : InstRW<[M3WriteVLDK,
763 M3WriteA1], (instregex "LD4i(8|16|32)_POST")>;
764 def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>;
765 def : InstRW<[M3WriteVLDM,
766 M3WriteA1], (instregex "LD4i(64)_POST")>;
768 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
769 def : InstRW<[M3WriteVLDC,
770 M3WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>;
771 def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
772 def : InstRW<[M3WriteVLDC,
773 M3WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>;
775 // ASIMD store instructions.
776 def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
777 def : InstRW<[WriteVST,
778 WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>;
779 def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
780 def : InstRW<[WriteVST,
781 WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>;
783 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
784 def : InstRW<[M3WriteVSTA,
785 WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>;
786 def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
787 def : InstRW<[M3WriteVSTA,
788 WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>;
790 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
791 def : InstRW<[M3WriteVSTB,
792 WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>;
793 def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
794 def : InstRW<[M3WriteVSTB,
795 WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>;
797 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
798 def : InstRW<[M3WriteVSTC,
799 WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>;
800 def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
801 def : InstRW<[M3WriteVSTC,
802 WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>;
804 def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>;
805 def : InstRW<[M3WriteVSTD,
806 WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>;
808 def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>;
809 def : InstRW<[M3WriteVSTD,
810 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>;
811 def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
812 def : InstRW<[M3WriteVSTE,
813 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>;
815 def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>;
816 def : InstRW<[M3WriteVSTD,
817 WriteAdr], (instregex "ST2i(8|16|32)_POST")>;
818 def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>;
819 def : InstRW<[M3WriteVSTD,
820 WriteAdr], (instregex "ST2i(64)_POST")>;
822 def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>;
823 def : InstRW<[M3WriteVSTF,
824 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>;
825 def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
826 def : InstRW<[M3WriteVSTG,
827 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>;
829 def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>;
830 def : InstRW<[M3WriteVSTH,
831 WriteAdr], (instregex "ST3i(8|16|32)_POST")>;
832 def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>;
833 def : InstRW<[M3WriteVSTF,
834 WriteAdr], (instregex "ST3i(64)_POST")>;
836 def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>;
837 def : InstRW<[M3WriteVSTF,
838 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>;
839 def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>;
840 def : InstRW<[M3WriteVSTI,
841 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>;
843 def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>;
844 def : InstRW<[M3WriteVSTF,
845 WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>;
847 // Cryptography instructions.
848 def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>;
849 def : InstRW<[M3WriteAES,
850 M3ReadAES], (instregex "^AESI?MC")>;
852 def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>;
854 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>;
855 def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>;
856 def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>;
859 def : InstRW<[M3WriteC2], (instregex "^CRC32")>;
861 } // SchedModel = ExynosM3Model