1 //=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
11 //===----------------------------------------------------------------------===//
13 def SVEPatternOperand : AsmOperandClass {
14 let Name = "SVEPattern";
15 let ParserMethod = "tryParseSVEPattern";
16 let PredicateMethod = "isSVEPattern";
17 let RenderMethod = "addImmOperands";
18 let DiagnosticType = "InvalidSVEPattern";
21 def sve_pred_enum : Operand<i32>, ImmLeaf<i32, [{
22 return (((uint32_t)Imm) < 32);
25 let PrintMethod = "printSVEPattern";
26 let ParserMatchClass = SVEPatternOperand;
29 def SVEPrefetchOperand : AsmOperandClass {
30 let Name = "SVEPrefetch";
31 let ParserMethod = "tryParsePrefetch<true>";
32 let PredicateMethod = "isPrefetch";
33 let RenderMethod = "addPrefetchOperands";
36 def sve_prfop : Operand<i32>, ImmLeaf<i32, [{
37 return (((uint32_t)Imm) <= 15);
39 let PrintMethod = "printPrefetchOp<true>";
40 let ParserMatchClass = SVEPrefetchOperand;
43 class SVELogicalImmOperand<int Width> : AsmOperandClass {
44 let Name = "SVELogicalImm" # Width;
45 let DiagnosticType = "LogicalSecondSource";
46 let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
47 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
50 def sve_logical_imm8 : Operand<i64> {
51 let ParserMatchClass = SVELogicalImmOperand<8>;
52 let PrintMethod = "printLogicalImm<int8_t>";
54 let MCOperandPredicate = [{
57 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
58 return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val);
62 def sve_logical_imm16 : Operand<i64> {
63 let ParserMatchClass = SVELogicalImmOperand<16>;
64 let PrintMethod = "printLogicalImm<int16_t>";
66 let MCOperandPredicate = [{
69 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
70 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
74 def sve_logical_imm32 : Operand<i64> {
75 let ParserMatchClass = SVELogicalImmOperand<32>;
76 let PrintMethod = "printLogicalImm<int32_t>";
78 let MCOperandPredicate = [{
81 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
82 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val);
86 class SVEPreferredLogicalImmOperand<int Width> : AsmOperandClass {
87 let Name = "SVEPreferredLogicalImm" # Width;
88 let PredicateMethod = "isSVEPreferredLogicalImm<int" # Width # "_t>";
89 let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
92 def sve_preferred_logical_imm16 : Operand<i64> {
93 let ParserMatchClass = SVEPreferredLogicalImmOperand<16>;
94 let PrintMethod = "printSVELogicalImm<int16_t>";
96 let MCOperandPredicate = [{
99 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
100 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) &&
101 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
105 def sve_preferred_logical_imm32 : Operand<i64> {
106 let ParserMatchClass = SVEPreferredLogicalImmOperand<32>;
107 let PrintMethod = "printSVELogicalImm<int32_t>";
109 let MCOperandPredicate = [{
112 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
113 return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) &&
114 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
118 def sve_preferred_logical_imm64 : Operand<i64> {
119 let ParserMatchClass = SVEPreferredLogicalImmOperand<64>;
120 let PrintMethod = "printSVELogicalImm<int64_t>";
122 let MCOperandPredicate = [{
125 int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
126 return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) &&
127 AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
131 class SVELogicalImmNotOperand<int Width> : AsmOperandClass {
132 let Name = "SVELogicalImm" # Width # "Not";
133 let DiagnosticType = "LogicalSecondSource";
134 let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
135 let RenderMethod = "addLogicalImmNotOperands<int" # Width # "_t>";
138 def sve_logical_imm8_not : Operand<i64> {
139 let ParserMatchClass = SVELogicalImmNotOperand<8>;
142 def sve_logical_imm16_not : Operand<i64> {
143 let ParserMatchClass = SVELogicalImmNotOperand<16>;
146 def sve_logical_imm32_not : Operand<i64> {
147 let ParserMatchClass = SVELogicalImmNotOperand<32>;
150 class SVEShiftedImmOperand<int ElementWidth, string Infix, string Predicate>
152 let Name = "SVE" # Infix # "Imm" # ElementWidth;
153 let DiagnosticType = "Invalid" # Name;
154 let RenderMethod = "addImmWithOptionalShiftOperands<8>";
155 let ParserMethod = "tryParseImmWithOptionalShift";
156 let PredicateMethod = Predicate;
159 def SVECpyImmOperand8 : SVEShiftedImmOperand<8, "Cpy", "isSVECpyImm<int8_t>">;
160 def SVECpyImmOperand16 : SVEShiftedImmOperand<16, "Cpy", "isSVECpyImm<int16_t>">;
161 def SVECpyImmOperand32 : SVEShiftedImmOperand<32, "Cpy", "isSVECpyImm<int32_t>">;
162 def SVECpyImmOperand64 : SVEShiftedImmOperand<64, "Cpy", "isSVECpyImm<int64_t>">;
164 def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm<int8_t>">;
165 def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm<int16_t>">;
166 def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm<int32_t>">;
167 def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm<int64_t>">;
169 class imm8_opt_lsl<int ElementWidth, string printType,
170 AsmOperandClass OpndClass, code Predicate>
171 : Operand<i32>, ImmLeaf<i32, Predicate> {
172 let EncoderMethod = "getImm8OptLsl";
173 let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">";
174 let PrintMethod = "printImm8OptLsl<" # printType # ">";
175 let ParserMatchClass = OpndClass;
176 let MIOperandInfo = (ops i32imm, i32imm);
179 def cpy_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "int8_t", SVECpyImmOperand8, [{
180 return AArch64_AM::isSVECpyImm<int8_t>(Imm);
182 def cpy_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "int16_t", SVECpyImmOperand16, [{
183 return AArch64_AM::isSVECpyImm<int16_t>(Imm);
185 def cpy_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "int32_t", SVECpyImmOperand32, [{
186 return AArch64_AM::isSVECpyImm<int32_t>(Imm);
188 def cpy_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "int64_t", SVECpyImmOperand64, [{
189 return AArch64_AM::isSVECpyImm<int64_t>(Imm);
192 def addsub_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "uint8_t", SVEAddSubImmOperand8, [{
193 return AArch64_AM::isSVEAddSubImm<int8_t>(Imm);
195 def addsub_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "uint16_t", SVEAddSubImmOperand16, [{
196 return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
198 def addsub_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "uint32_t", SVEAddSubImmOperand32, [{
199 return AArch64_AM::isSVEAddSubImm<int32_t>(Imm);
201 def addsub_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "uint64_t", SVEAddSubImmOperand64, [{
202 return AArch64_AM::isSVEAddSubImm<int64_t>(Imm);
205 class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass {
206 let Name = "SVEExactFPImmOperand" # Suffix;
207 let DiagnosticType = "Invalid" # Name;
208 let ParserMethod = "tryParseFPImm<false>";
209 let PredicateMethod = "isExactFPImm<" # ValA # ", " # ValB # ">";
210 let RenderMethod = "addExactFPImmOperands<" # ValA # ", " # ValB # ">";
213 class SVEExactFPImmOperand<string Suffix, string ValA, string ValB> : Operand<i32> {
214 let PrintMethod = "printExactFPImm<" # ValA # ", " # ValB # ">";
215 let ParserMatchClass = SVEExactFPImm<Suffix, ValA, ValB>;
218 def sve_fpimm_half_one
219 : SVEExactFPImmOperand<"HalfOne", "AArch64ExactFPImm::half",
220 "AArch64ExactFPImm::one">;
221 def sve_fpimm_half_two
222 : SVEExactFPImmOperand<"HalfTwo", "AArch64ExactFPImm::half",
223 "AArch64ExactFPImm::two">;
224 def sve_fpimm_zero_one
225 : SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero",
226 "AArch64ExactFPImm::one">;
228 def sve_incdec_imm : Operand<i32>, ImmLeaf<i32, [{
229 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
231 let ParserMatchClass = Imm1_16Operand;
232 let EncoderMethod = "getSVEIncDecImm";
233 let DecoderMethod = "DecodeSVEIncDecImm";
236 //===----------------------------------------------------------------------===//
237 // SVE PTrue - These are used extensively throughout the pattern matching so
238 // it's important we define them first.
239 //===----------------------------------------------------------------------===//
241 class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty>
242 : I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern),
243 asm, "\t$Pd, $pattern",
248 let Inst{31-24} = 0b00100101;
249 let Inst{23-22} = sz8_64;
250 let Inst{21-19} = 0b011;
251 let Inst{18-17} = opc{2-1};
252 let Inst{16} = opc{0};
253 let Inst{15-10} = 0b111000;
254 let Inst{9-5} = pattern;
258 let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
261 multiclass sve_int_ptrue<bits<3> opc, string asm> {
262 def _B : sve_int_ptrue<0b00, opc, asm, PPR8>;
263 def _H : sve_int_ptrue<0b01, opc, asm, PPR16>;
264 def _S : sve_int_ptrue<0b10, opc, asm, PPR32>;
265 def _D : sve_int_ptrue<0b11, opc, asm, PPR64>;
267 def : InstAlias<asm # "\t$Pd",
268 (!cast<Instruction>(NAME # _B) PPR8:$Pd, 0b11111), 1>;
269 def : InstAlias<asm # "\t$Pd",
270 (!cast<Instruction>(NAME # _H) PPR16:$Pd, 0b11111), 1>;
271 def : InstAlias<asm # "\t$Pd",
272 (!cast<Instruction>(NAME # _S) PPR32:$Pd, 0b11111), 1>;
273 def : InstAlias<asm # "\t$Pd",
274 (!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>;
277 let Predicates = [HasSVE] in {
278 defm PTRUE : sve_int_ptrue<0b000, "ptrue">;
279 defm PTRUES : sve_int_ptrue<0b001, "ptrues">;
282 //===----------------------------------------------------------------------===//
283 // SVE pattern match helpers.
284 //===----------------------------------------------------------------------===//
286 class SVE_1_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
288 : Pat<(vtd (op vt1:$Op1)),
291 class SVE_3_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
292 ValueType vt2, ValueType vt3, Instruction inst>
293 : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)),
294 (inst $Op1, $Op2, $Op3)>;
296 //===----------------------------------------------------------------------===//
297 // SVE Predicate Misc Group
298 //===----------------------------------------------------------------------===//
300 class sve_int_pfalse<bits<6> opc, string asm>
301 : I<(outs PPR8:$Pd), (ins),
306 let Inst{31-24} = 0b00100101;
307 let Inst{23-22} = opc{5-4};
308 let Inst{21-19} = 0b011;
309 let Inst{18-16} = opc{3-1};
310 let Inst{15-10} = 0b111001;
311 let Inst{9} = opc{0};
312 let Inst{8-4} = 0b00000;
316 class sve_int_ptest<bits<6> opc, string asm>
317 : I<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
323 let Inst{31-24} = 0b00100101;
324 let Inst{23-22} = opc{5-4};
325 let Inst{21-19} = 0b010;
326 let Inst{18-16} = opc{3-1};
327 let Inst{15-14} = 0b11;
328 let Inst{13-10} = Pg;
329 let Inst{9} = opc{0};
331 let Inst{4-0} = 0b00000;
336 class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm,
338 : I<(outs pprty:$Pdn), (ins PPRAny:$Pg, pprty:$_Pdn),
339 asm, "\t$Pdn, $Pg, $_Pdn",
344 let Inst{31-24} = 0b00100101;
345 let Inst{23-22} = sz8_64;
346 let Inst{21-19} = 0b011;
347 let Inst{18-16} = opc{4-2};
348 let Inst{15-11} = 0b11000;
349 let Inst{10-9} = opc{1-0};
354 let Constraints = "$Pdn = $_Pdn";
358 multiclass sve_int_pfirst<bits<5> opc, string asm> {
359 def : sve_int_pfirst_next<0b01, opc, asm, PPR8>;
362 multiclass sve_int_pnext<bits<5> opc, string asm> {
363 def _B : sve_int_pfirst_next<0b00, opc, asm, PPR8>;
364 def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>;
365 def _S : sve_int_pfirst_next<0b10, opc, asm, PPR32>;
366 def _D : sve_int_pfirst_next<0b11, opc, asm, PPR64>;
369 //===----------------------------------------------------------------------===//
370 // SVE Predicate Count Group
371 //===----------------------------------------------------------------------===//
373 class sve_int_count_r<bits<2> sz8_64, bits<5> opc, string asm,
374 RegisterOperand dty, PPRRegOp pprty, RegisterOperand sty>
375 : I<(outs dty:$Rdn), (ins pprty:$Pg, sty:$_Rdn),
381 let Inst{31-24} = 0b00100101;
382 let Inst{23-22} = sz8_64;
383 let Inst{21-19} = 0b101;
384 let Inst{18-16} = opc{4-2};
385 let Inst{15-11} = 0b10001;
386 let Inst{10-9} = opc{1-0};
390 // Signed 32bit forms require their GPR operand printed.
391 let AsmString = !if(!eq(opc{4,2-0}, 0b0000),
392 !strconcat(asm, "\t$Rdn, $Pg, $_Rdn"),
393 !strconcat(asm, "\t$Rdn, $Pg"));
394 let Constraints = "$Rdn = $_Rdn";
397 multiclass sve_int_count_r_s32<bits<5> opc, string asm> {
398 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64as32>;
399 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>;
400 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64as32>;
401 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64as32>;
404 multiclass sve_int_count_r_u32<bits<5> opc, string asm> {
405 def _B : sve_int_count_r<0b00, opc, asm, GPR32z, PPR8, GPR32z>;
406 def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>;
407 def _S : sve_int_count_r<0b10, opc, asm, GPR32z, PPR32, GPR32z>;
408 def _D : sve_int_count_r<0b11, opc, asm, GPR32z, PPR64, GPR32z>;
411 multiclass sve_int_count_r_x64<bits<5> opc, string asm> {
412 def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>;
413 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>;
414 def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>;
415 def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>;
418 class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
419 ZPRRegOp zprty, PPRRegOp pprty>
420 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, pprty:$Pm),
426 let Inst{31-24} = 0b00100101;
427 let Inst{23-22} = sz8_64;
428 let Inst{21-19} = 0b101;
429 let Inst{18-16} = opc{4-2};
430 let Inst{15-11} = 0b10000;
431 let Inst{10-9} = opc{1-0};
435 let Constraints = "$Zdn = $_Zdn";
436 let DestructiveInstType = Destructive;
437 let ElementSize = ElementSizeNone;
440 multiclass sve_int_count_v<bits<5> opc, string asm> {
441 def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
442 def _S : sve_int_count_v<0b10, opc, asm, ZPR32, PPR32>;
443 def _D : sve_int_count_v<0b11, opc, asm, ZPR64, PPR64>;
445 def : InstAlias<asm # "\t$Zdn, $Pm",
446 (!cast<Instruction>(NAME # "_H") ZPR16:$Zdn, PPRAny:$Pm), 0>;
447 def : InstAlias<asm # "\t$Zdn, $Pm",
448 (!cast<Instruction>(NAME # "_S") ZPR32:$Zdn, PPRAny:$Pm), 0>;
449 def : InstAlias<asm # "\t$Zdn, $Pm",
450 (!cast<Instruction>(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>;
453 class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,
455 : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
456 asm, "\t$Rd, $Pg, $Pn",
462 let Inst{31-24} = 0b00100101;
463 let Inst{23-22} = sz8_64;
464 let Inst{21-19} = 0b100;
465 let Inst{18-16} = opc{3-1};
466 let Inst{15-14} = 0b10;
467 let Inst{13-10} = Pg;
468 let Inst{9} = opc{0};
473 multiclass sve_int_pcount_pred<bits<4> opc, string asm> {
474 def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>;
475 def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
476 def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>;
477 def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>;
480 //===----------------------------------------------------------------------===//
481 // SVE Element Count Group
482 //===----------------------------------------------------------------------===//
484 class sve_int_count<bits<3> opc, string asm>
485 : I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
486 asm, "\t$Rd, $pattern, mul $imm4",
492 let Inst{31-24} = 0b00000100;
493 let Inst{23-22} = opc{2-1};
494 let Inst{21-20} = 0b10;
495 let Inst{19-16} = imm4;
496 let Inst{15-11} = 0b11100;
497 let Inst{10} = opc{0};
498 let Inst{9-5} = pattern;
502 multiclass sve_int_count<bits<3> opc, string asm> {
503 def NAME : sve_int_count<opc, asm>;
505 def : InstAlias<asm # "\t$Rd, $pattern",
506 (!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>;
507 def : InstAlias<asm # "\t$Rd",
508 (!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>;
511 class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
512 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
513 asm, "\t$Zdn, $pattern, mul $imm4",
519 let Inst{31-24} = 0b00000100;
520 let Inst{23-22} = opc{4-3};
522 let Inst{20} = opc{2};
523 let Inst{19-16} = imm4;
524 let Inst{15-12} = 0b1100;
525 let Inst{11-10} = opc{1-0};
526 let Inst{9-5} = pattern;
529 let Constraints = "$Zdn = $_Zdn";
530 let DestructiveInstType = Destructive;
531 let ElementSize = ElementSizeNone;
534 multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> {
535 def NAME : sve_int_countvlv<opc, asm, zprty>;
537 def : InstAlias<asm # "\t$Zdn, $pattern",
538 (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>;
539 def : InstAlias<asm # "\t$Zdn",
540 (!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>;
543 class sve_int_pred_pattern_a<bits<3> opc, string asm>
544 : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
545 asm, "\t$Rdn, $pattern, mul $imm4",
551 let Inst{31-24} = 0b00000100;
552 let Inst{23-22} = opc{2-1};
553 let Inst{21-20} = 0b11;
554 let Inst{19-16} = imm4;
555 let Inst{15-11} = 0b11100;
556 let Inst{10} = opc{0};
557 let Inst{9-5} = pattern;
560 let Constraints = "$Rdn = $_Rdn";
563 multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> {
564 def NAME : sve_int_pred_pattern_a<opc, asm>;
566 def : InstAlias<asm # "\t$Rdn, $pattern",
567 (!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, 1), 1>;
568 def : InstAlias<asm # "\t$Rdn",
569 (!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>;
572 class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt,
574 : I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
575 asm, "\t$Rdn, $pattern, mul $imm4",
581 let Inst{31-24} = 0b00000100;
582 let Inst{23-22} = opc{4-3};
584 let Inst{20} = opc{2};
585 let Inst{19-16} = imm4;
586 let Inst{15-12} = 0b1111;
587 let Inst{11-10} = opc{1-0};
588 let Inst{9-5} = pattern;
591 // Signed 32bit forms require their GPR operand printed.
592 let AsmString = !if(!eq(opc{2,0}, 0b00),
593 !strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"),
594 !strconcat(asm, "\t$Rdn, $pattern, mul $imm4"));
596 let Constraints = "$Rdn = $_Rdn";
599 multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> {
600 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>;
602 def : InstAlias<asm # "\t$Rd, $Rn, $pattern",
603 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>;
604 def : InstAlias<asm # "\t$Rd, $Rn",
605 (!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>;
608 multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> {
609 def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>;
611 def : InstAlias<asm # "\t$Rdn, $pattern",
612 (!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
613 def : InstAlias<asm # "\t$Rdn",
614 (!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>;
617 multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
618 def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
620 def : InstAlias<asm # "\t$Rdn, $pattern",
621 (!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
622 def : InstAlias<asm # "\t$Rdn",
623 (!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>;
627 //===----------------------------------------------------------------------===//
628 // SVE Permute - Cross Lane Group
629 //===----------------------------------------------------------------------===//
631 class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
632 ValueType vt, RegisterClass srcRegType,
633 SDPatternOperator op>
634 : I<(outs zprty:$Zd), (ins srcRegType:$Rn),
637 [(set (vt zprty:$Zd), (op srcRegType:$Rn))]>, Sched<[]> {
640 let Inst{31-24} = 0b00000101;
641 let Inst{23-22} = sz8_64;
642 let Inst{21-10} = 0b100000001110;
647 multiclass sve_int_perm_dup_r<string asm, SDPatternOperator op> {
648 def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, nxv16i8, GPR32sp, op>;
649 def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, nxv8i16, GPR32sp, op>;
650 def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, nxv4i32, GPR32sp, op>;
651 def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, nxv2i64, GPR64sp, op>;
653 def : InstAlias<"mov $Zd, $Rn",
654 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>;
655 def : InstAlias<"mov $Zd, $Rn",
656 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>;
657 def : InstAlias<"mov $Zd, $Rn",
658 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>;
659 def : InstAlias<"mov $Zd, $Rn",
660 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>;
663 class sve_int_perm_dup_i<bits<5> tsz, Operand immtype, string asm,
665 : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$idx),
666 asm, "\t$Zd, $Zn$idx",
672 let Inst{31-24} = 0b00000101;
673 let Inst{23-22} = {?,?}; // imm3h
675 let Inst{20-16} = tsz;
676 let Inst{15-10} = 0b001000;
681 multiclass sve_int_perm_dup_i<string asm> {
682 def _B : sve_int_perm_dup_i<{?,?,?,?,1}, sve_elm_idx_extdup_b, asm, ZPR8> {
683 let Inst{23-22} = idx{5-4};
684 let Inst{20-17} = idx{3-0};
686 def _H : sve_int_perm_dup_i<{?,?,?,1,0}, sve_elm_idx_extdup_h, asm, ZPR16> {
687 let Inst{23-22} = idx{4-3};
688 let Inst{20-18} = idx{2-0};
690 def _S : sve_int_perm_dup_i<{?,?,1,0,0}, sve_elm_idx_extdup_s, asm, ZPR32> {
691 let Inst{23-22} = idx{3-2};
692 let Inst{20-19} = idx{1-0};
694 def _D : sve_int_perm_dup_i<{?,1,0,0,0}, sve_elm_idx_extdup_d, asm, ZPR64> {
695 let Inst{23-22} = idx{2-1};
696 let Inst{20} = idx{0};
698 def _Q : sve_int_perm_dup_i<{1,0,0,0,0}, sve_elm_idx_extdup_q, asm, ZPR128> {
699 let Inst{23-22} = idx{1-0};
702 def : InstAlias<"mov $Zd, $Zn$idx",
703 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx), 1>;
704 def : InstAlias<"mov $Zd, $Zn$idx",
705 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx), 1>;
706 def : InstAlias<"mov $Zd, $Zn$idx",
707 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx), 1>;
708 def : InstAlias<"mov $Zd, $Zn$idx",
709 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx), 1>;
710 def : InstAlias<"mov $Zd, $Zn$idx",
711 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx), 1>;
712 def : InstAlias<"mov $Zd, $Bn",
713 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, FPR8asZPR:$Bn, 0), 2>;
714 def : InstAlias<"mov $Zd, $Hn",
715 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, FPR16asZPR:$Hn, 0), 2>;
716 def : InstAlias<"mov $Zd, $Sn",
717 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>;
718 def : InstAlias<"mov $Zd, $Dn",
719 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, FPR64asZPR:$Dn, 0), 2>;
720 def : InstAlias<"mov $Zd, $Qn",
721 (!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
724 class sve_int_perm_tbl<bits<2> sz8_64, bits<2> opc, string asm,
725 ZPRRegOp zprty, RegisterOperand VecList>
726 : I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm),
727 asm, "\t$Zd, $Zn, $Zm",
733 let Inst{31-24} = 0b00000101;
734 let Inst{23-22} = sz8_64;
736 let Inst{20-16} = Zm;
737 let Inst{15-13} = 0b001;
738 let Inst{12-11} = opc;
744 multiclass sve_int_perm_tbl<string asm> {
745 def _B : sve_int_perm_tbl<0b00, 0b10, asm, ZPR8, Z_b>;
746 def _H : sve_int_perm_tbl<0b01, 0b10, asm, ZPR16, Z_h>;
747 def _S : sve_int_perm_tbl<0b10, 0b10, asm, ZPR32, Z_s>;
748 def _D : sve_int_perm_tbl<0b11, 0b10, asm, ZPR64, Z_d>;
750 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
751 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>;
752 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
753 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>;
754 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
755 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>;
756 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
757 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
760 multiclass sve2_int_perm_tbl<string asm> {
761 def _B : sve_int_perm_tbl<0b00, 0b01, asm, ZPR8, ZZ_b>;
762 def _H : sve_int_perm_tbl<0b01, 0b01, asm, ZPR16, ZZ_h>;
763 def _S : sve_int_perm_tbl<0b10, 0b01, asm, ZPR32, ZZ_s>;
764 def _D : sve_int_perm_tbl<0b11, 0b01, asm, ZPR64, ZZ_d>;
767 class sve2_int_perm_tbx<bits<2> sz8_64, string asm, ZPRRegOp zprty>
768 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, zprty:$Zm),
769 asm, "\t$Zd, $Zn, $Zm",
775 let Inst{31-24} = 0b00000101;
776 let Inst{23-22} = sz8_64;
778 let Inst{20-16} = Zm;
779 let Inst{15-10} = 0b001011;
783 let Constraints = "$Zd = $_Zd";
786 multiclass sve2_int_perm_tbx<string asm> {
787 def _B : sve2_int_perm_tbx<0b00, asm, ZPR8>;
788 def _H : sve2_int_perm_tbx<0b01, asm, ZPR16>;
789 def _S : sve2_int_perm_tbx<0b10, asm, ZPR32>;
790 def _D : sve2_int_perm_tbx<0b11, asm, ZPR64>;
793 class sve_int_perm_reverse_z<bits<2> sz8_64, string asm, ZPRRegOp zprty>
794 : I<(outs zprty:$Zd), (ins zprty:$Zn),
800 let Inst{31-24} = 0b00000101;
801 let Inst{23-22} = sz8_64;
802 let Inst{21-10} = 0b111000001110;
807 multiclass sve_int_perm_reverse_z<string asm> {
808 def _B : sve_int_perm_reverse_z<0b00, asm, ZPR8>;
809 def _H : sve_int_perm_reverse_z<0b01, asm, ZPR16>;
810 def _S : sve_int_perm_reverse_z<0b10, asm, ZPR32>;
811 def _D : sve_int_perm_reverse_z<0b11, asm, ZPR64>;
814 class sve_int_perm_reverse_p<bits<2> sz8_64, string asm, PPRRegOp pprty>
815 : I<(outs pprty:$Pd), (ins pprty:$Pn),
821 let Inst{31-24} = 0b00000101;
822 let Inst{23-22} = sz8_64;
823 let Inst{21-9} = 0b1101000100000;
829 multiclass sve_int_perm_reverse_p<string asm> {
830 def _B : sve_int_perm_reverse_p<0b00, asm, PPR8>;
831 def _H : sve_int_perm_reverse_p<0b01, asm, PPR16>;
832 def _S : sve_int_perm_reverse_p<0b10, asm, PPR32>;
833 def _D : sve_int_perm_reverse_p<0b11, asm, PPR64>;
836 class sve_int_perm_unpk<bits<2> sz16_64, bits<2> opc, string asm,
837 ZPRRegOp zprty1, ZPRRegOp zprty2>
838 : I<(outs zprty1:$Zd), (ins zprty2:$Zn),
843 let Inst{31-24} = 0b00000101;
844 let Inst{23-22} = sz16_64;
845 let Inst{21-18} = 0b1100;
846 let Inst{17-16} = opc;
847 let Inst{15-10} = 0b001110;
852 multiclass sve_int_perm_unpk<bits<2> opc, string asm, SDPatternOperator op> {
853 def _H : sve_int_perm_unpk<0b01, opc, asm, ZPR16, ZPR8>;
854 def _S : sve_int_perm_unpk<0b10, opc, asm, ZPR32, ZPR16>;
855 def _D : sve_int_perm_unpk<0b11, opc, asm, ZPR64, ZPR32>;
857 def : SVE_1_Op_Pat<nxv8i16, op, nxv16i8, !cast<Instruction>(NAME # _H)>;
858 def : SVE_1_Op_Pat<nxv4i32, op, nxv8i16, !cast<Instruction>(NAME # _S)>;
859 def : SVE_1_Op_Pat<nxv2i64, op, nxv4i32, !cast<Instruction>(NAME # _D)>;
862 class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty,
863 RegisterClass srcRegType>
864 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
870 let Inst{31-24} = 0b00000101;
871 let Inst{23-22} = sz8_64;
872 let Inst{21-10} = 0b100100001110;
876 let Constraints = "$Zdn = $_Zdn";
877 let DestructiveInstType = Destructive;
878 let ElementSize = ElementSizeNone;
881 multiclass sve_int_perm_insrs<string asm> {
882 def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>;
883 def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>;
884 def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>;
885 def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
888 class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty,
889 RegisterClass srcRegType>
890 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm),
896 let Inst{31-24} = 0b00000101;
897 let Inst{23-22} = sz8_64;
898 let Inst{21-10} = 0b110100001110;
902 let Constraints = "$Zdn = $_Zdn";
903 let DestructiveInstType = Destructive;
904 let ElementSize = ElementSizeNone;
907 multiclass sve_int_perm_insrv<string asm> {
908 def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>;
909 def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>;
910 def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>;
911 def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
914 //===----------------------------------------------------------------------===//
915 // SVE Permute - Extract Group
916 //===----------------------------------------------------------------------===//
918 class sve_int_perm_extract_i<string asm>
919 : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8),
920 asm, "\t$Zdn, $_Zdn, $Zm, $imm8",
925 let Inst{31-21} = 0b00000101001;
926 let Inst{20-16} = imm8{7-3};
927 let Inst{15-13} = 0b000;
928 let Inst{12-10} = imm8{2-0};
932 let Constraints = "$Zdn = $_Zdn";
933 let DestructiveInstType = Destructive;
934 let ElementSize = ElementSizeNone;
937 class sve2_int_perm_extract_i_cons<string asm>
938 : I<(outs ZPR8:$Zd), (ins ZZ_b:$Zn, imm0_255:$imm8),
939 asm, "\t$Zd, $Zn, $imm8",
944 let Inst{31-21} = 0b00000101011;
945 let Inst{20-16} = imm8{7-3};
946 let Inst{15-13} = 0b000;
947 let Inst{12-10} = imm8{2-0};
952 //===----------------------------------------------------------------------===//
953 // SVE Vector Select Group
954 //===----------------------------------------------------------------------===//
956 class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty>
957 : I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm),
958 asm, "\t$Zd, $Pg, $Zn, $Zm",
965 let Inst{31-24} = 0b00000101;
966 let Inst{23-22} = sz8_64;
968 let Inst{20-16} = Zm;
969 let Inst{15-14} = 0b11;
970 let Inst{13-10} = Pg;
975 multiclass sve_int_sel_vvv<string asm> {
976 def _B : sve_int_sel_vvv<0b00, asm, ZPR8>;
977 def _H : sve_int_sel_vvv<0b01, asm, ZPR16>;
978 def _S : sve_int_sel_vvv<0b10, asm, ZPR32>;
979 def _D : sve_int_sel_vvv<0b11, asm, ZPR64>;
981 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
982 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>;
983 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
984 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>;
985 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
986 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>;
987 def : InstAlias<"mov $Zd, $Pg/m, $Zn",
988 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>;
992 //===----------------------------------------------------------------------===//
993 // SVE Predicate Logical Operations Group
994 //===----------------------------------------------------------------------===//
996 class sve_int_pred_log<bits<4> opc, string asm>
997 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
998 asm, "\t$Pd, $Pg/z, $Pn, $Pm",
1005 let Inst{31-24} = 0b00100101;
1006 let Inst{23-22} = opc{3-2};
1007 let Inst{21-20} = 0b00;
1008 let Inst{19-16} = Pm;
1009 let Inst{15-14} = 0b01;
1010 let Inst{13-10} = Pg;
1011 let Inst{9} = opc{1};
1013 let Inst{4} = opc{0};
1016 // SEL has no predication qualifier.
1017 let AsmString = !if(!eq(opc, 0b0011),
1018 !strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"),
1019 !strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm"));
1021 let Defs = !if(!eq (opc{2}, 1), [NZCV], []);
1025 //===----------------------------------------------------------------------===//
1026 // SVE Logical Mask Immediate Group
1027 //===----------------------------------------------------------------------===//
1029 class sve_int_log_imm<bits<2> opc, string asm>
1030 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13),
1031 asm, "\t$Zdn, $_Zdn, $imms13",
1032 "", []>, Sched<[]> {
1035 let Inst{31-24} = 0b00000101;
1036 let Inst{23-22} = opc;
1037 let Inst{21-18} = 0b0000;
1038 let Inst{17-5} = imms13;
1039 let Inst{4-0} = Zdn;
1041 let Constraints = "$Zdn = $_Zdn";
1042 let DecoderMethod = "DecodeSVELogicalImmInstruction";
1043 let DestructiveInstType = Destructive;
1044 let ElementSize = ElementSizeNone;
1047 multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> {
1048 def NAME : sve_int_log_imm<opc, asm>;
1050 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1051 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>;
1052 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1053 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>;
1054 def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
1055 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>;
1057 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1058 (!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>;
1059 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1060 (!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>;
1061 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1062 (!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>;
1063 def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
1064 (!cast<Instruction>(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>;
1067 class sve_int_dup_mask_imm<string asm>
1068 : I<(outs ZPR64:$Zd), (ins logical_imm64:$imms),
1069 asm, "\t$Zd, $imms",
1074 let Inst{31-18} = 0b00000101110000;
1075 let Inst{17-5} = imms;
1078 let isReMaterializable = 1;
1079 let DecoderMethod = "DecodeSVELogicalImmInstruction";
1082 multiclass sve_int_dup_mask_imm<string asm> {
1083 def NAME : sve_int_dup_mask_imm<asm>;
1085 def : InstAlias<"dupm $Zd, $imm",
1086 (!cast<Instruction>(NAME) ZPR8:$Zd, sve_logical_imm8:$imm), 4>;
1087 def : InstAlias<"dupm $Zd, $imm",
1088 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_logical_imm16:$imm), 3>;
1089 def : InstAlias<"dupm $Zd, $imm",
1090 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_logical_imm32:$imm), 2>;
1092 // All Zd.b forms have a CPY/DUP equivalent, hence no byte alias here.
1093 def : InstAlias<"mov $Zd, $imm",
1094 (!cast<Instruction>(NAME) ZPR16:$Zd, sve_preferred_logical_imm16:$imm), 7>;
1095 def : InstAlias<"mov $Zd, $imm",
1096 (!cast<Instruction>(NAME) ZPR32:$Zd, sve_preferred_logical_imm32:$imm), 6>;
1097 def : InstAlias<"mov $Zd, $imm",
1098 (!cast<Instruction>(NAME) ZPR64:$Zd, sve_preferred_logical_imm64:$imm), 5>;
1101 //===----------------------------------------------------------------------===//
1102 // SVE Integer Arithmetic - Unpredicated Group.
1103 //===----------------------------------------------------------------------===//
1105 class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
1107 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
1108 asm, "\t$Zd, $Zn, $Zm",
1109 "", []>, Sched<[]> {
1113 let Inst{31-24} = 0b00000100;
1114 let Inst{23-22} = sz8_64;
1116 let Inst{20-16} = Zm;
1117 let Inst{15-13} = 0b000;
1118 let Inst{12-10} = opc;
1123 multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
1124 def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
1125 def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
1126 def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
1127 def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
1130 //===----------------------------------------------------------------------===//
1131 // SVE Floating Point Arithmetic - Predicated Group
1132 //===----------------------------------------------------------------------===//
1134 class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm,
1137 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
1138 asm, "\t$Zdn, $Pg/m, $_Zdn, $i1",
1144 let Inst{31-24} = 0b01100101;
1145 let Inst{23-22} = sz;
1146 let Inst{21-19} = 0b011;
1147 let Inst{18-16} = opc;
1148 let Inst{15-13} = 0b100;
1149 let Inst{12-10} = Pg;
1150 let Inst{9-6} = 0b0000;
1152 let Inst{4-0} = Zdn;
1154 let Constraints = "$Zdn = $_Zdn";
1155 let DestructiveInstType = Destructive;
1156 let ElementSize = zprty.ElementSize;
1159 multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
1160 def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>;
1161 def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>;
1162 def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
1165 class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
1167 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
1168 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
1174 let Inst{31-24} = 0b01100101;
1175 let Inst{23-22} = sz;
1176 let Inst{21-20} = 0b00;
1177 let Inst{19-16} = opc;
1178 let Inst{15-13} = 0b100;
1179 let Inst{12-10} = Pg;
1181 let Inst{4-0} = Zdn;
1183 let Constraints = "$Zdn = $_Zdn";
1184 let DestructiveInstType = Destructive;
1185 let ElementSize = zprty.ElementSize;
1188 multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> {
1189 def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
1190 def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
1191 def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
1194 class sve_fp_ftmad<bits<2> sz, string asm, ZPRRegOp zprty>
1195 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, imm0_7:$imm3),
1196 asm, "\t$Zdn, $_Zdn, $Zm, $imm3",
1202 let Inst{31-24} = 0b01100101;
1203 let Inst{23-22} = sz;
1204 let Inst{21-19} = 0b010;
1205 let Inst{18-16} = imm3;
1206 let Inst{15-10} = 0b100000;
1208 let Inst{4-0} = Zdn;
1210 let Constraints = "$Zdn = $_Zdn";
1211 let DestructiveInstType = Destructive;
1212 let ElementSize = ElementSizeNone;
1215 multiclass sve_fp_ftmad<string asm> {
1216 def _H : sve_fp_ftmad<0b01, asm, ZPR16>;
1217 def _S : sve_fp_ftmad<0b10, asm, ZPR32>;
1218 def _D : sve_fp_ftmad<0b11, asm, ZPR64>;
1222 //===----------------------------------------------------------------------===//
1223 // SVE Floating Point Arithmetic - Unpredicated Group
1224 //===----------------------------------------------------------------------===//
1226 class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm,
1228 ValueType vt, ValueType vt2, SDPatternOperator op>
1229 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
1230 asm, "\t$Zd, $Zn, $Zm",
1232 [(set (vt zprty:$Zd), (op (vt zprty:$Zn), (vt2 zprty:$Zm)))]>, Sched<[]> {
1236 let Inst{31-24} = 0b01100101;
1237 let Inst{23-22} = sz;
1239 let Inst{20-16} = Zm;
1240 let Inst{15-13} = 0b000;
1241 let Inst{12-10} = opc;
1246 multiclass sve_fp_3op_u_zd<bits<3> opc, string asm, SDPatternOperator op> {
1247 def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16, nxv8f16, nxv8f16, op>;
1248 def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32, nxv4f32, nxv4f32, op>;
1249 def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64, nxv2f64, nxv2f64, op>;
1252 //===----------------------------------------------------------------------===//
1253 // SVE Floating Point Fused Multiply-Add Group
1254 //===----------------------------------------------------------------------===//
1256 class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty>
1257 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
1258 asm, "\t$Zda, $Pg/m, $Zn, $Zm",
1265 let Inst{31-24} = 0b01100101;
1266 let Inst{23-22} = sz;
1268 let Inst{20-16} = Zm;
1270 let Inst{14-13} = opc;
1271 let Inst{12-10} = Pg;
1273 let Inst{4-0} = Zda;
1275 let Constraints = "$Zda = $_Zda";
1276 let DestructiveInstType = Destructive;
1277 let ElementSize = zprty.ElementSize;
1280 multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm> {
1281 def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>;
1282 def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>;
1283 def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>;
1286 class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm,
1288 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
1289 asm, "\t$Zdn, $Pg/m, $Zm, $Za",
1296 let Inst{31-24} = 0b01100101;
1297 let Inst{23-22} = sz;
1299 let Inst{20-16} = Za;
1301 let Inst{14-13} = opc;
1302 let Inst{12-10} = Pg;
1304 let Inst{4-0} = Zdn;
1306 let Constraints = "$Zdn = $_Zdn";
1307 let DestructiveInstType = Destructive;
1308 let ElementSize = zprty.ElementSize;
1311 multiclass sve_fp_3op_p_zds_b<bits<2> opc, string asm> {
1312 def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>;
1313 def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>;
1314 def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>;
1317 //===----------------------------------------------------------------------===//
1318 // SVE Floating Point Multiply-Add - Indexed Group
1319 //===----------------------------------------------------------------------===//
1321 class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm,
1323 ZPRRegOp zprty2, Operand itype>
1324 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop),
1325 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
1328 let Inst{31-24} = 0b01100100;
1329 let Inst{23-22} = sz;
1331 let Inst{15-11} = 0;
1334 let Inst{4-0} = Zda;
1336 let Constraints = "$Zda = $_Zda";
1337 let DestructiveInstType = Destructive;
1338 let ElementSize = ElementSizeNone;
1341 multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm> {
1342 def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> {
1345 let Inst{22} = iop{2};
1346 let Inst{20-19} = iop{1-0};
1347 let Inst{18-16} = Zm;
1349 def _S : sve_fp_fma_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR3b32, VectorIndexS> {
1352 let Inst{20-19} = iop;
1353 let Inst{18-16} = Zm;
1355 def _D : sve_fp_fma_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR4b64, VectorIndexD> {
1359 let Inst{19-16} = Zm;
1364 //===----------------------------------------------------------------------===//
1365 // SVE Floating Point Multiply - Indexed Group
1366 //===----------------------------------------------------------------------===//
1368 class sve_fp_fmul_by_indexed_elem<bits<2> sz, string asm, ZPRRegOp zprty,
1369 ZPRRegOp zprty2, Operand itype>
1370 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop),
1371 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
1374 let Inst{31-24} = 0b01100100;
1375 let Inst{23-22} = sz;
1377 let Inst{15-10} = 0b001000;
1382 multiclass sve_fp_fmul_by_indexed_elem<string asm> {
1383 def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, asm, ZPR16, ZPR3b16, VectorIndexH> {
1386 let Inst{22} = iop{2};
1387 let Inst{20-19} = iop{1-0};
1388 let Inst{18-16} = Zm;
1390 def _S : sve_fp_fmul_by_indexed_elem<0b10, asm, ZPR32, ZPR3b32, VectorIndexS> {
1393 let Inst{20-19} = iop;
1394 let Inst{18-16} = Zm;
1396 def _D : sve_fp_fmul_by_indexed_elem<0b11, asm, ZPR64, ZPR4b64, VectorIndexD> {
1400 let Inst{19-16} = Zm;
1404 //===----------------------------------------------------------------------===//
1405 // SVE Floating Point Complex Multiply-Add Group
1406 //===----------------------------------------------------------------------===//
1408 class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty>
1409 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
1410 complexrotateop:$imm),
1411 asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm",
1412 "", []>, Sched<[]> {
1418 let Inst{31-24} = 0b01100100;
1419 let Inst{23-22} = sz;
1421 let Inst{20-16} = Zm;
1423 let Inst{14-13} = imm;
1424 let Inst{12-10} = Pg;
1426 let Inst{4-0} = Zda;
1428 let Constraints = "$Zda = $_Zda";
1429 let DestructiveInstType = Destructive;
1430 let ElementSize = zprty.ElementSize;
1433 multiclass sve_fp_fcmla<string asm> {
1434 def _H : sve_fp_fcmla<0b01, asm, ZPR16>;
1435 def _S : sve_fp_fcmla<0b10, asm, ZPR32>;
1436 def _D : sve_fp_fcmla<0b11, asm, ZPR64>;
1439 //===----------------------------------------------------------------------===//
1440 // SVE Floating Point Complex Multiply-Add - Indexed Group
1441 //===----------------------------------------------------------------------===//
1443 class sve_fp_fcmla_by_indexed_elem<bits<2> sz, string asm,
1445 ZPRRegOp zprty2, Operand itype>
1446 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop,
1447 complexrotateop:$imm),
1448 asm, "\t$Zda, $Zn, $Zm$iop, $imm",
1449 "", []>, Sched<[]> {
1453 let Inst{31-24} = 0b01100100;
1454 let Inst{23-22} = sz;
1456 let Inst{15-12} = 0b0001;
1457 let Inst{11-10} = imm;
1459 let Inst{4-0} = Zda;
1461 let Constraints = "$Zda = $_Zda";
1462 let DestructiveInstType = Destructive;
1463 let ElementSize = ElementSizeNone;
1466 multiclass sve_fp_fcmla_by_indexed_elem<string asm> {
1467 def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> {
1470 let Inst{20-19} = iop;
1471 let Inst{18-16} = Zm;
1473 def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD> {
1477 let Inst{19-16} = Zm;
1481 //===----------------------------------------------------------------------===//
1482 // SVE Floating Point Complex Addition Group
1483 //===----------------------------------------------------------------------===//
1485 class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty>
1486 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
1487 complexrotateopodd:$imm),
1488 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm",
1495 let Inst{31-24} = 0b01100100;
1496 let Inst{23-22} = sz;
1497 let Inst{21-17} = 0;
1499 let Inst{15-13} = 0b100;
1500 let Inst{12-10} = Pg;
1502 let Inst{4-0} = Zdn;
1504 let Constraints = "$Zdn = $_Zdn";
1505 let DestructiveInstType = Destructive;
1506 let ElementSize = zprty.ElementSize;
1509 multiclass sve_fp_fcadd<string asm> {
1510 def _H : sve_fp_fcadd<0b01, asm, ZPR16>;
1511 def _S : sve_fp_fcadd<0b10, asm, ZPR32>;
1512 def _D : sve_fp_fcadd<0b11, asm, ZPR64>;
1515 //===----------------------------------------------------------------------===//
1516 // SVE2 Floating Point Convert Group
1517 //===----------------------------------------------------------------------===//
1519 class sve2_fp_convert_precision<bits<4> opc, string asm,
1520 ZPRRegOp zprty1, ZPRRegOp zprty2>
1521 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn),
1522 asm, "\t$Zd, $Pg/m, $Zn",
1528 let Inst{31-24} = 0b01100100;
1529 let Inst{23-22} = opc{3-2};
1530 let Inst{21-18} = 0b0010;
1531 let Inst{17-16} = opc{1-0};
1532 let Inst{15-13} = 0b101;
1533 let Inst{12-10} = Pg;
1537 let Constraints = "$Zd = $_Zd";
1540 multiclass sve2_fp_convert_down_narrow<string asm> {
1541 def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>;
1542 def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>;
1545 multiclass sve2_fp_convert_up_long<string asm> {
1546 def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>;
1547 def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>;
1550 multiclass sve2_fp_convert_down_odd_rounding<string asm> {
1551 def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>;
1554 //===----------------------------------------------------------------------===//
1555 // SVE2 Floating Point Pairwise Group
1556 //===----------------------------------------------------------------------===//
1558 class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm,
1560 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
1561 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
1567 let Inst{31-24} = 0b01100100;
1568 let Inst{23-22} = sz;
1569 let Inst{21-19} = 0b010;
1570 let Inst{18-16} = opc;
1571 let Inst{15-13} = 0b100;
1572 let Inst{12-10} = Pg;
1574 let Inst{4-0} = Zdn;
1576 let Constraints = "$Zdn = $_Zdn";
1577 let DestructiveInstType = Destructive;
1578 let ElementSize = zprty.ElementSize;
1581 multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> {
1582 def _H : sve2_fp_pairwise_pred<0b01, opc, asm, ZPR16>;
1583 def _S : sve2_fp_pairwise_pred<0b10, opc, asm, ZPR32>;
1584 def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>;
1587 //===----------------------------------------------------------------------===//
1588 // SVE2 Floating Point Widening Multiply-Add - Indexed Group
1589 //===----------------------------------------------------------------------===//
1591 class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
1592 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
1594 asm, "\t$Zda, $Zn, $Zm$iop",
1601 let Inst{31-21} = 0b01100100101;
1602 let Inst{20-19} = iop{2-1};
1603 let Inst{18-16} = Zm;
1604 let Inst{15-14} = 0b01;
1605 let Inst{13} = opc{1};
1607 let Inst{11} = iop{0};
1608 let Inst{10} = opc{0};
1610 let Inst{4-0} = Zda;
1612 let Constraints = "$Zda = $_Zda";
1613 let DestructiveInstType = Destructive;
1614 let ElementSize = ElementSizeNone;
1617 //===----------------------------------------------------------------------===//
1618 // SVE2 Floating Point Widening Multiply-Add Group
1619 //===----------------------------------------------------------------------===//
1621 class sve2_fp_mla_long<bits<2> opc, string asm>
1622 : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
1623 asm, "\t$Zda, $Zn, $Zm",
1629 let Inst{31-21} = 0b01100100101;
1630 let Inst{20-16} = Zm;
1631 let Inst{15-14} = 0b10;
1632 let Inst{13} = opc{1};
1633 let Inst{12-11} = 0b00;
1634 let Inst{10} = opc{0};
1636 let Inst{4-0} = Zda;
1638 let Constraints = "$Zda = $_Zda";
1639 let DestructiveInstType = Destructive;
1640 let ElementSize = ElementSizeNone;
1643 //===----------------------------------------------------------------------===//
1644 // SVE Stack Allocation Group
1645 //===----------------------------------------------------------------------===//
1647 class sve_int_arith_vl<bit opc, string asm>
1648 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
1649 asm, "\t$Rd, $Rn, $imm6",
1655 let Inst{31-23} = 0b000001000;
1658 let Inst{20-16} = Rn;
1659 let Inst{15-11} = 0b01010;
1660 let Inst{10-5} = imm6;
1664 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
1665 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
1666 asm, "\t$Rd, $imm6",
1671 let Inst{31-23} = 0b000001001;
1674 let Inst{20-16} = opc2{4-0};
1675 let Inst{15-11} = 0b01010;
1676 let Inst{10-5} = imm6;
1680 //===----------------------------------------------------------------------===//
1681 // SVE Permute - In Lane Group
1682 //===----------------------------------------------------------------------===//
1684 class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm,
1686 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
1687 asm, "\t$Zd, $Zn, $Zm",
1693 let Inst{31-24} = 0b00000101;
1694 let Inst{23-22} = sz8_64;
1696 let Inst{20-16} = Zm;
1697 let Inst{15-13} = 0b011;
1698 let Inst{12-10} = opc;
1703 multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> {
1704 def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>;
1705 def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>;
1706 def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>;
1707 def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>;
1710 //===----------------------------------------------------------------------===//
1711 // SVE Floating Point Unary Operations Group
1712 //===----------------------------------------------------------------------===//
1714 class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype,
1715 RegisterOperand o_zprtype, ElementSizeEnum size>
1716 : I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn),
1717 asm, "\t$Zd, $Pg/m, $Zn",
1723 let Inst{31-24} = 0b01100101;
1724 let Inst{23-22} = opc{6-5};
1726 let Inst{20-16} = opc{4-0};
1727 let Inst{15-13} = 0b101;
1728 let Inst{12-10} = Pg;
1732 let Constraints = "$Zd = $_Zd";
1733 let DestructiveInstType = Destructive;
1734 let ElementSize = size;
1737 multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> {
1738 def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16, ElementSizeH>;
1739 def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32, ElementSizeS>;
1740 def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64, ElementSizeD>;
1743 multiclass sve2_fp_flogb<string asm> {
1744 def _H : sve_fp_2op_p_zd<0b0011010, asm, ZPR16, ZPR16, ElementSizeH>;
1745 def _S : sve_fp_2op_p_zd<0b0011100, asm, ZPR32, ZPR32, ElementSizeS>;
1746 def _D : sve_fp_2op_p_zd<0b0011110, asm, ZPR64, ZPR64, ElementSizeD>;
1749 //===----------------------------------------------------------------------===//
1750 // SVE Floating Point Unary Operations - Unpredicated Group
1751 //===----------------------------------------------------------------------===//
1753 class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm,
1755 : I<(outs zprty:$Zd), (ins zprty:$Zn),
1761 let Inst{31-24} = 0b01100101;
1762 let Inst{23-22} = sz;
1763 let Inst{21-19} = 0b001;
1764 let Inst{18-16} = opc;
1765 let Inst{15-10} = 0b001100;
1770 multiclass sve_fp_2op_u_zd<bits<3> opc, string asm> {
1771 def _H : sve_fp_2op_u_zd<0b01, opc, asm, ZPR16>;
1772 def _S : sve_fp_2op_u_zd<0b10, opc, asm, ZPR32>;
1773 def _D : sve_fp_2op_u_zd<0b11, opc, asm, ZPR64>;
1776 //===----------------------------------------------------------------------===//
1777 // SVE Integer Arithmetic - Binary Predicated Group
1778 //===----------------------------------------------------------------------===//
1780 class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc,
1781 string asm, ZPRRegOp zprty>
1782 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
1783 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
1787 let Inst{31-24} = 0b00000100;
1788 let Inst{23-22} = sz8_64;
1790 let Inst{20-19} = fmt;
1791 let Inst{18-16} = opc;
1792 let Inst{15-13} = 0b000;
1793 let Inst{12-10} = Pg;
1795 let Inst{4-0} = Zdn;
1797 let Constraints = "$Zdn = $_Zdn";
1798 let DestructiveInstType = Destructive;
1799 let ElementSize = zprty.ElementSize;
1802 multiclass sve_int_bin_pred_log<bits<3> opc, string asm> {
1803 def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>;
1804 def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>;
1805 def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>;
1806 def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>;
1809 multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> {
1810 def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>;
1811 def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>;
1812 def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>;
1813 def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
1816 multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> {
1817 def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>;
1818 def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>;
1819 def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>;
1820 def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>;
1823 multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm> {
1824 def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>;
1825 def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>;
1826 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
1827 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
1830 // Special case for divides which are not defined for 8b/16b elements.
1831 multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm> {
1832 def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
1833 def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
1836 //===----------------------------------------------------------------------===//
1837 // SVE Integer Multiply-Add Group
1838 //===----------------------------------------------------------------------===//
1840 class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
1842 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
1843 asm, "\t$Zdn, $Pg/m, $Zm, $Za",
1850 let Inst{31-24} = 0b00000100;
1851 let Inst{23-22} = sz8_64;
1853 let Inst{20-16} = Zm;
1854 let Inst{15-14} = 0b11;
1856 let Inst{12-10} = Pg;
1858 let Inst{4-0} = Zdn;
1860 let Constraints = "$Zdn = $_Zdn";
1861 let DestructiveInstType = Destructive;
1862 let ElementSize = zprty.ElementSize;
1865 multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm> {
1866 def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>;
1867 def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>;
1868 def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>;
1869 def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>;
1872 class sve_int_mlas_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
1874 : I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
1875 asm, "\t$Zda, $Pg/m, $Zn, $Zm",
1882 let Inst{31-24} = 0b00000100;
1883 let Inst{23-22} = sz8_64;
1885 let Inst{20-16} = Zm;
1886 let Inst{15-14} = 0b01;
1888 let Inst{12-10} = Pg;
1890 let Inst{4-0} = Zda;
1892 let Constraints = "$Zda = $_Zda";
1893 let DestructiveInstType = Destructive;
1894 let ElementSize = zprty.ElementSize;
1897 multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm> {
1898 def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>;
1899 def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>;
1900 def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>;
1901 def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>;
1904 //===----------------------------------------------------------------------===//
1905 // SVE2 Integer Multiply-Add - Unpredicated Group
1906 //===----------------------------------------------------------------------===//
1908 class sve2_int_mla<bits<2> sz, bits<5> opc, string asm,
1909 ZPRRegOp zprty1, ZPRRegOp zprty2>
1910 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
1911 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
1915 let Inst{31-24} = 0b01000100;
1916 let Inst{23-22} = sz;
1918 let Inst{20-16} = Zm;
1920 let Inst{14-10} = opc;
1922 let Inst{4-0} = Zda;
1924 let Constraints = "$Zda = $_Zda";
1925 let DestructiveInstType = Destructive;
1926 let ElementSize = ElementSizeNone;
1929 multiclass sve2_int_mla<bit S, string asm> {
1930 def _B : sve2_int_mla<0b00, { 0b1110, S }, asm, ZPR8, ZPR8>;
1931 def _H : sve2_int_mla<0b01, { 0b1110, S }, asm, ZPR16, ZPR16>;
1932 def _S : sve2_int_mla<0b10, { 0b1110, S }, asm, ZPR32, ZPR32>;
1933 def _D : sve2_int_mla<0b11, { 0b1110, S }, asm, ZPR64, ZPR64>;
1936 multiclass sve2_int_mla_long<bits<5> opc, string asm> {
1937 def _H : sve2_int_mla<0b01, opc, asm, ZPR16, ZPR8>;
1938 def _S : sve2_int_mla<0b10, opc, asm, ZPR32, ZPR16>;
1939 def _D : sve2_int_mla<0b11, opc, asm, ZPR64, ZPR32>;
1942 //===----------------------------------------------------------------------===//
1943 // SVE2 Integer Multiply-Add - Indexed Group
1944 //===----------------------------------------------------------------------===//
1946 class sve2_int_mla_by_indexed_elem<bits<2> sz, bits<6> opc, string asm,
1947 ZPRRegOp zprty1, ZPRRegOp zprty2,
1948 ZPRRegOp zprty3, Operand itype>
1949 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
1950 asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
1953 let Inst{31-24} = 0b01000100;
1954 let Inst{23-22} = sz;
1956 let Inst{15-10} = opc;
1958 let Inst{4-0} = Zda;
1960 let Constraints = "$Zda = $_Zda";
1961 let DestructiveInstType = Destructive;
1962 let ElementSize = ElementSizeNone;
1965 multiclass sve2_int_mla_by_indexed_elem<bits<2> opc, bit S, string asm> {
1966 def _H : sve2_int_mla_by_indexed_elem<{0, ?}, { 0b000, opc, S }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> {
1969 let Inst{22} = iop{2};
1970 let Inst{20-19} = iop{1-0};
1971 let Inst{18-16} = Zm;
1973 def _S : sve2_int_mla_by_indexed_elem<0b10, { 0b000, opc, S }, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> {
1976 let Inst{20-19} = iop;
1977 let Inst{18-16} = Zm;
1979 def _D : sve2_int_mla_by_indexed_elem<0b11, { 0b000, opc, S }, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> {
1983 let Inst{19-16} = Zm;
1987 //===----------------------------------------------------------------------===//
1988 // SVE2 Integer Multiply-Add Long - Indexed Group
1989 //===----------------------------------------------------------------------===//
1991 multiclass sve2_int_mla_long_by_indexed_elem<bits<4> opc, string asm> {
1992 def _S : sve2_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
1993 asm, ZPR32, ZPR16, ZPR3b16, VectorIndexH> {
1996 let Inst{20-19} = iop{2-1};
1997 let Inst{18-16} = Zm;
1998 let Inst{11} = iop{0};
2000 def _D : sve2_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
2001 asm, ZPR64, ZPR32, ZPR4b32, VectorIndexS> {
2004 let Inst{20} = iop{1};
2005 let Inst{19-16} = Zm;
2006 let Inst{11} = iop{0};
2010 //===----------------------------------------------------------------------===//
2011 // SVE Integer Dot Product Group
2012 //===----------------------------------------------------------------------===//
2014 class sve_intx_dot<bit sz, bit U, string asm, ZPRRegOp zprty1,
2016 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm), asm,
2017 "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
2021 let Inst{31-23} = 0b010001001;
2024 let Inst{20-16} = Zm;
2025 let Inst{15-11} = 0;
2028 let Inst{4-0} = Zda;
2030 let Constraints = "$Zda = $_Zda";
2031 let DestructiveInstType = Destructive;
2034 multiclass sve_intx_dot<bit opc, string asm, SDPatternOperator op> {
2035 def _S : sve_intx_dot<0b0, opc, asm, ZPR32, ZPR8>;
2036 def _D : sve_intx_dot<0b1, opc, asm, ZPR64, ZPR16>;
2038 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _S)>;
2039 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _D)>;
2042 //===----------------------------------------------------------------------===//
2043 // SVE Integer Dot Product Group - Indexed Group
2044 //===----------------------------------------------------------------------===//
2046 class sve_intx_dot_by_indexed_elem<bit sz, bit U, string asm,
2047 ZPRRegOp zprty1, ZPRRegOp zprty2,
2048 ZPRRegOp zprty3, Operand itype>
2049 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop),
2050 asm, "\t$Zda, $Zn, $Zm$iop",
2051 "", []>, Sched<[]> {
2054 let Inst{31-23} = 0b010001001;
2057 let Inst{15-11} = 0;
2060 let Inst{4-0} = Zda;
2062 let Constraints = "$Zda = $_Zda";
2063 let DestructiveInstType = Destructive;
2066 multiclass sve_intx_dot_by_indexed_elem<bit opc, string asm,
2067 SDPatternOperator op> {
2068 def _S : sve_intx_dot_by_indexed_elem<0b0, opc, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS32b> {
2071 let Inst{20-19} = iop;
2072 let Inst{18-16} = Zm;
2074 def _D : sve_intx_dot_by_indexed_elem<0b1, opc, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD32b> {
2078 let Inst{19-16} = Zm;
2081 def : Pat<(nxv4i32 (op nxv4i32:$Op1, nxv16i8:$Op2, nxv16i8:$Op3, (i32 VectorIndexS32b:$idx))),
2082 (!cast<Instruction>(NAME # _S) $Op1, $Op2, $Op3, VectorIndexS32b:$idx)>;
2083 def : Pat<(nxv2i64 (op nxv2i64:$Op1, nxv8i16:$Op2, nxv8i16:$Op3, (i32 VectorIndexD32b:$idx))),
2084 (!cast<Instruction>(NAME # _D) $Op1, $Op2, $Op3, VectorIndexD32b:$idx)>;
2087 //===----------------------------------------------------------------------===//
2088 // SVE2 Complex Integer Dot Product Group
2089 //===----------------------------------------------------------------------===//
2091 class sve2_complex_int_arith<bits<2> sz, bits<4> opc, string asm,
2092 ZPRRegOp zprty1, ZPRRegOp zprty2>
2093 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm,
2094 complexrotateop:$rot),
2095 asm, "\t$Zda, $Zn, $Zm, $rot", "", []>, Sched<[]> {
2100 let Inst{31-24} = 0b01000100;
2101 let Inst{23-22} = sz;
2103 let Inst{20-16} = Zm;
2104 let Inst{15-12} = opc;
2105 let Inst{11-10} = rot;
2107 let Inst{4-0} = Zda;
2109 let Constraints = "$Zda = $_Zda";
2110 let DestructiveInstType = Destructive;
2111 let ElementSize = ElementSizeNone;
2114 multiclass sve2_cintx_dot<string asm> {
2115 def _S : sve2_complex_int_arith<0b10, 0b0001, asm, ZPR32, ZPR8>;
2116 def _D : sve2_complex_int_arith<0b11, 0b0001, asm, ZPR64, ZPR16>;
2119 //===----------------------------------------------------------------------===//
2120 // SVE2 Complex Multiply-Add Group
2121 //===----------------------------------------------------------------------===//
2123 multiclass sve2_int_cmla<bit opc, string asm> {
2124 def _B : sve2_complex_int_arith<0b00, { 0b001, opc }, asm, ZPR8, ZPR8>;
2125 def _H : sve2_complex_int_arith<0b01, { 0b001, opc }, asm, ZPR16, ZPR16>;
2126 def _S : sve2_complex_int_arith<0b10, { 0b001, opc }, asm, ZPR32, ZPR32>;
2127 def _D : sve2_complex_int_arith<0b11, { 0b001, opc }, asm, ZPR64, ZPR64>;
2130 //===----------------------------------------------------------------------===//
2131 // SVE2 Complex Integer Dot Product - Indexed Group
2132 //===----------------------------------------------------------------------===//
2134 class sve2_complex_int_arith_indexed<bits<2> sz, bits<4> opc, string asm,
2135 ZPRRegOp zprty1, ZPRRegOp zprty2,
2136 ZPRRegOp zprty3, Operand itype>
2137 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty3:$Zm, itype:$iop,
2138 complexrotateop:$rot),
2139 asm, "\t$Zda, $Zn, $Zm$iop, $rot", "", []>, Sched<[]> {
2143 let Inst{31-24} = 0b01000100;
2144 let Inst{23-22} = sz;
2146 let Inst{15-12} = opc;
2147 let Inst{11-10} = rot;
2149 let Inst{4-0} = Zda;
2151 let Constraints = "$Zda = $_Zda";
2152 let DestructiveInstType = Destructive;
2153 let ElementSize = ElementSizeNone;
2156 multiclass sve2_cintx_dot_by_indexed_elem<string asm> {
2157 def _S : sve2_complex_int_arith_indexed<0b10, 0b0100, asm, ZPR32, ZPR8, ZPR3b8, VectorIndexS> {
2160 let Inst{20-19} = iop;
2161 let Inst{18-16} = Zm;
2163 def _D : sve2_complex_int_arith_indexed<0b11, 0b0100, asm, ZPR64, ZPR16, ZPR4b16, VectorIndexD> {
2167 let Inst{19-16} = Zm;
2171 //===----------------------------------------------------------------------===//
2172 // SVE2 Complex Multiply-Add - Indexed Group
2173 //===----------------------------------------------------------------------===//
2175 multiclass sve2_cmla_by_indexed_elem<bit opc, string asm> {
2176 def _H : sve2_complex_int_arith_indexed<0b10, { 0b011, opc }, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexS> {
2179 let Inst{20-19} = iop;
2180 let Inst{18-16} = Zm;
2182 def _S : sve2_complex_int_arith_indexed<0b11, { 0b011, opc }, asm, ZPR32, ZPR32, ZPR4b32, VectorIndexD> {
2186 let Inst{19-16} = Zm;
2190 //===----------------------------------------------------------------------===//
2191 // SVE2 Integer Multiply - Unpredicated Group
2192 //===----------------------------------------------------------------------===//
2194 class sve2_int_mul<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty>
2195 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
2196 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2200 let Inst{31-24} = 0b00000100;
2201 let Inst{23-22} = sz;
2203 let Inst{20-16} = Zm;
2204 let Inst{15-13} = 0b011;
2205 let Inst{12-10} = opc;
2210 multiclass sve2_int_mul<bits<3> opc, string asm> {
2211 def _B : sve2_int_mul<0b00, opc, asm, ZPR8>;
2212 def _H : sve2_int_mul<0b01, opc, asm, ZPR16>;
2213 def _S : sve2_int_mul<0b10, opc, asm, ZPR32>;
2214 def _D : sve2_int_mul<0b11, opc, asm, ZPR64>;
2217 //===----------------------------------------------------------------------===//
2218 // SVE2 Integer Multiply - Indexed Group
2219 //===----------------------------------------------------------------------===//
2221 class sve2_int_mul_by_indexed_elem<bits<2> sz, bits<4> opc, string asm,
2222 ZPRRegOp zprty1, ZPRRegOp zprty2,
2223 ZPRRegOp zprty3, Operand itype>
2224 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm, itype:$iop),
2225 asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
2228 let Inst{31-24} = 0b01000100;
2229 let Inst{23-22} = sz;
2231 let Inst{15-14} = 0b11;
2232 let Inst{13-10} = opc;
2237 multiclass sve2_int_mul_by_indexed_elem<bits<4> opc, string asm> {
2238 def _H : sve2_int_mul_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR16, ZPR3b16, VectorIndexH> {
2241 let Inst{22} = iop{2};
2242 let Inst{20-19} = iop{1-0};
2243 let Inst{18-16} = Zm;
2245 def _S : sve2_int_mul_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR32, ZPR3b32, VectorIndexS> {
2248 let Inst{20-19} = iop;
2249 let Inst{18-16} = Zm;
2251 def _D : sve2_int_mul_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR64, ZPR4b64, VectorIndexD> {
2255 let Inst{19-16} = Zm;
2259 multiclass sve2_int_mul_long_by_indexed_elem<bits<3> opc, string asm> {
2260 def _S : sve2_int_mul_by_indexed_elem<0b10, { opc{2-1}, ?, opc{0} }, asm,
2261 ZPR32, ZPR16, ZPR3b16, VectorIndexH> {
2264 let Inst{20-19} = iop{2-1};
2265 let Inst{18-16} = Zm;
2266 let Inst{11} = iop{0};
2268 def _D : sve2_int_mul_by_indexed_elem<0b11, { opc{2-1}, ?, opc{0} }, asm,
2269 ZPR64, ZPR32, ZPR4b32, VectorIndexS> {
2272 let Inst{20} = iop{1};
2273 let Inst{19-16} = Zm;
2274 let Inst{11} = iop{0};
2278 //===----------------------------------------------------------------------===//
2279 // SVE2 Integer - Predicated Group
2280 //===----------------------------------------------------------------------===//
2282 class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm,
2284 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
2285 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
2289 let Inst{31-24} = 0b01000100;
2290 let Inst{23-22} = sz;
2292 let Inst{20-16} = opc{5-1};
2293 let Inst{15-14} = 0b10;
2294 let Inst{13} = opc{0};
2295 let Inst{12-10} = Pg;
2297 let Inst{4-0} = Zdn;
2299 let Constraints = "$Zdn = $_Zdn";
2300 let DestructiveInstType = Destructive;
2301 let ElementSize = zprty.ElementSize;
2304 multiclass sve2_int_arith_pred<bits<6> opc, string asm> {
2305 def _B : sve2_int_arith_pred<0b00, opc, asm, ZPR8>;
2306 def _H : sve2_int_arith_pred<0b01, opc, asm, ZPR16>;
2307 def _S : sve2_int_arith_pred<0b10, opc, asm, ZPR32>;
2308 def _D : sve2_int_arith_pred<0b11, opc, asm, ZPR64>;
2311 class sve2_int_sadd_long_accum_pairwise<bits<2> sz, bit U, string asm,
2312 ZPRRegOp zprty1, ZPRRegOp zprty2>
2313 : I<(outs zprty1:$Zda), (ins PPR3bAny:$Pg, zprty1:$_Zda, zprty2:$Zn),
2314 asm, "\t$Zda, $Pg/m, $Zn", "", []>, Sched<[]> {
2318 let Inst{31-24} = 0b01000100;
2319 let Inst{23-22} = sz;
2320 let Inst{21-17} = 0b00010;
2322 let Inst{15-13} = 0b101;
2323 let Inst{12-10} = Pg;
2325 let Inst{4-0} = Zda;
2327 let Constraints = "$Zda = $_Zda";
2328 let DestructiveInstType = Destructive;
2329 let ElementSize = zprty1.ElementSize;
2332 multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm> {
2333 def _H : sve2_int_sadd_long_accum_pairwise<0b01, U, asm, ZPR16, ZPR8>;
2334 def _S : sve2_int_sadd_long_accum_pairwise<0b10, U, asm, ZPR32, ZPR16>;
2335 def _D : sve2_int_sadd_long_accum_pairwise<0b11, U, asm, ZPR64, ZPR32>;
2338 class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
2339 string asm, ZPRRegOp zprty>
2340 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
2341 asm, "\t$Zd, $Pg/m, $Zn",
2347 let Inst{31-24} = 0b01000100;
2348 let Inst{23-22} = sz;
2349 let Inst{21-20} = 0b00;
2352 let Inst{17-16} = opc;
2353 let Inst{15-13} = 0b101;
2354 let Inst{12-10} = Pg;
2358 let Constraints = "$Zd = $_Zd";
2359 let DestructiveInstType = Destructive;
2360 let ElementSize = zprty.ElementSize;
2363 multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm> {
2364 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
2367 multiclass sve2_int_un_pred_arit<bits<3> opc, string asm> {
2368 def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>;
2369 def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>;
2370 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
2371 def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>;
2374 //===----------------------------------------------------------------------===//
2375 // SVE2 Widening Integer Arithmetic Group
2376 //===----------------------------------------------------------------------===//
2378 class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm,
2379 ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3>
2380 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm),
2381 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2385 let Inst{31-24} = 0b01000101;
2386 let Inst{23-22} = sz;
2388 let Inst{20-16} = Zm;
2390 let Inst{14-10} = opc;
2395 multiclass sve2_wide_int_arith_long<bits<5> opc, string asm> {
2396 def _H : sve2_wide_int_arith<0b01, opc, asm, ZPR16, ZPR8, ZPR8>;
2397 def _S : sve2_wide_int_arith<0b10, opc, asm, ZPR32, ZPR16, ZPR16>;
2398 def _D : sve2_wide_int_arith<0b11, opc, asm, ZPR64, ZPR32, ZPR32>;
2401 multiclass sve2_wide_int_arith_wide<bits<3> opc, string asm> {
2402 def _H : sve2_wide_int_arith<0b01, { 0b10, opc }, asm, ZPR16, ZPR16, ZPR8>;
2403 def _S : sve2_wide_int_arith<0b10, { 0b10, opc }, asm, ZPR32, ZPR32, ZPR16>;
2404 def _D : sve2_wide_int_arith<0b11, { 0b10, opc }, asm, ZPR64, ZPR64, ZPR32>;
2407 multiclass sve2_pmul_long<bits<1> opc, string asm> {
2408 def _H : sve2_wide_int_arith<0b01, {0b1101, opc}, asm, ZPR16, ZPR8, ZPR8>;
2409 def _D : sve2_wide_int_arith<0b11, {0b1101, opc}, asm, ZPR64, ZPR32, ZPR32>;
2412 //===----------------------------------------------------------------------===//
2414 //===----------------------------------------------------------------------===//
2416 class sve2_misc<bits<2> sz, bits<4> opc, string asm,
2417 ZPRRegOp zprty1, ZPRRegOp zprty2>
2418 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
2419 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2423 let Inst{31-24} = 0b01000101;
2424 let Inst{23-22} = sz;
2426 let Inst{20-16} = Zm;
2427 let Inst{15-14} = 0b10;
2428 let Inst{13-10} = opc;
2433 multiclass sve2_misc_bitwise<bits<4> opc, string asm> {
2434 def _B : sve2_misc<0b00, opc, asm, ZPR8, ZPR8>;
2435 def _H : sve2_misc<0b01, opc, asm, ZPR16, ZPR16>;
2436 def _S : sve2_misc<0b10, opc, asm, ZPR32, ZPR32>;
2437 def _D : sve2_misc<0b11, opc, asm, ZPR64, ZPR64>;
2440 multiclass sve2_misc_int_addsub_long_interleaved<bits<2> opc, string asm> {
2441 def _H : sve2_misc<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
2442 def _S : sve2_misc<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
2443 def _D : sve2_misc<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
2446 class sve2_bitwise_xor_interleaved<bits<2> sz, bits<1> opc, string asm,
2447 ZPRRegOp zprty1, ZPRRegOp zprty2>
2448 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
2449 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2453 let Inst{31-24} = 0b01000101;
2454 let Inst{23-22} = sz;
2456 let Inst{20-16} = Zm;
2457 let Inst{15-11} = 0b10010;
2462 let Constraints = "$Zd = $_Zd";
2463 let DestructiveInstType = Destructive;
2464 let ElementSize = ElementSizeNone;
2467 multiclass sve2_bitwise_xor_interleaved<bit opc, string asm> {
2468 def _B : sve2_bitwise_xor_interleaved<0b00, opc, asm, ZPR8, ZPR8>;
2469 def _H : sve2_bitwise_xor_interleaved<0b01, opc, asm, ZPR16, ZPR16>;
2470 def _S : sve2_bitwise_xor_interleaved<0b10, opc, asm, ZPR32, ZPR32>;
2471 def _D : sve2_bitwise_xor_interleaved<0b11, opc, asm, ZPR64, ZPR64>;
2474 class sve2_bitwise_shift_left_long<bits<3> tsz8_64, bits<2> opc, string asm,
2475 ZPRRegOp zprty1, ZPRRegOp zprty2,
2477 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm),
2478 asm, "\t$Zd, $Zn, $imm",
2479 "", []>, Sched<[]> {
2483 let Inst{31-23} = 0b010001010;
2484 let Inst{22} = tsz8_64{2};
2486 let Inst{20-19} = tsz8_64{1-0};
2487 let Inst{18-16} = imm{2-0}; // imm3
2488 let Inst{15-12} = 0b1010;
2489 let Inst{11-10} = opc;
2494 multiclass sve2_bitwise_shift_left_long<bits<2> opc, string asm> {
2495 def _H : sve2_bitwise_shift_left_long<{0,0,1}, opc, asm,
2496 ZPR16, ZPR8, vecshiftL8>;
2497 def _S : sve2_bitwise_shift_left_long<{0,1,?}, opc, asm,
2498 ZPR32, ZPR16, vecshiftL16> {
2499 let Inst{19} = imm{3};
2501 def _D : sve2_bitwise_shift_left_long<{1,?,?}, opc, asm,
2502 ZPR64, ZPR32, vecshiftL32> {
2503 let Inst{20-19} = imm{4-3};
2507 //===----------------------------------------------------------------------===//
2508 // SVE2 Accumulate Group
2509 //===----------------------------------------------------------------------===//
2511 class sve2_int_bin_shift_imm<bits<4> tsz8_64, bit opc, string asm,
2512 ZPRRegOp zprty, Operand immtype>
2513 : I<(outs zprty:$Zd), (ins zprty:$_Zd, zprty:$Zn, immtype:$imm),
2514 asm, "\t$Zd, $Zn, $imm",
2515 "", []>, Sched<[]> {
2519 let Inst{31-24} = 0b01000101;
2520 let Inst{23-22} = tsz8_64{3-2};
2522 let Inst{20-19} = tsz8_64{1-0};
2523 let Inst{18-16} = imm{2-0}; // imm3
2524 let Inst{15-11} = 0b11110;
2529 let Constraints = "$Zd = $_Zd";
2532 multiclass sve2_int_bin_shift_imm_left<bit opc, string asm> {
2533 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
2534 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
2535 let Inst{19} = imm{3};
2537 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
2538 let Inst{20-19} = imm{4-3};
2540 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
2541 let Inst{22} = imm{5};
2542 let Inst{20-19} = imm{4-3};
2546 multiclass sve2_int_bin_shift_imm_right<bit opc, string asm> {
2547 def _B : sve2_int_bin_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2548 def _H : sve2_int_bin_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
2549 let Inst{19} = imm{3};
2551 def _S : sve2_int_bin_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
2552 let Inst{20-19} = imm{4-3};
2554 def _D : sve2_int_bin_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
2555 let Inst{22} = imm{5};
2556 let Inst{20-19} = imm{4-3};
2560 class sve2_int_bin_accum_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
2561 ZPRRegOp zprty, Operand immtype>
2562 : I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm),
2563 asm, "\t$Zda, $Zn, $imm",
2564 "", []>, Sched<[]> {
2568 let Inst{31-24} = 0b01000101;
2569 let Inst{23-22} = tsz8_64{3-2};
2571 let Inst{20-19} = tsz8_64{1-0};
2572 let Inst{18-16} = imm{2-0}; // imm3
2573 let Inst{15-12} = 0b1110;
2574 let Inst{11-10} = opc;
2576 let Inst{4-0} = Zda;
2578 let Constraints = "$Zda = $_Zda";
2579 let DestructiveInstType = Destructive;
2580 let ElementSize = ElementSizeNone;
2583 multiclass sve2_int_bin_accum_shift_imm_right<bits<2> opc, string asm> {
2584 def _B : sve2_int_bin_accum_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
2585 def _H : sve2_int_bin_accum_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
2586 let Inst{19} = imm{3};
2588 def _S : sve2_int_bin_accum_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
2589 let Inst{20-19} = imm{4-3};
2591 def _D : sve2_int_bin_accum_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
2592 let Inst{22} = imm{5};
2593 let Inst{20-19} = imm{4-3};
2597 class sve2_int_cadd<bits<2> sz, bit opc, string asm, ZPRRegOp zprty>
2598 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$rot),
2599 asm, "\t$Zdn, $_Zdn, $Zm, $rot", "", []>, Sched<[]> {
2603 let Inst{31-24} = 0b01000101;
2604 let Inst{23-22} = sz;
2605 let Inst{21-17} = 0b00000;
2607 let Inst{15-11} = 0b11011;
2610 let Inst{4-0} = Zdn;
2612 let Constraints = "$Zdn = $_Zdn";
2613 let DestructiveInstType = Destructive;
2614 let ElementSize = ElementSizeNone;
2617 multiclass sve2_int_cadd<bit opc, string asm> {
2618 def _B : sve2_int_cadd<0b00, opc, asm, ZPR8>;
2619 def _H : sve2_int_cadd<0b01, opc, asm, ZPR16>;
2620 def _S : sve2_int_cadd<0b10, opc, asm, ZPR32>;
2621 def _D : sve2_int_cadd<0b11, opc, asm, ZPR64>;
2624 class sve2_int_absdiff_accum<bits<2> sz, bits<4> opc, string asm,
2625 ZPRRegOp zprty1, ZPRRegOp zprty2>
2626 : I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
2627 asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
2631 let Inst{31-24} = 0b01000101;
2632 let Inst{23-22} = sz;
2634 let Inst{20-16} = Zm;
2635 let Inst{15-14} = 0b11;
2636 let Inst{13-10} = opc;
2638 let Inst{4-0} = Zda;
2640 let Constraints = "$Zda = $_Zda";
2641 let DestructiveInstType = Destructive;
2642 let ElementSize = ElementSizeNone;
2645 multiclass sve2_int_absdiff_accum<bit opc, string asm> {
2646 def _B : sve2_int_absdiff_accum<0b00, { 0b111, opc }, asm, ZPR8, ZPR8>;
2647 def _H : sve2_int_absdiff_accum<0b01, { 0b111, opc }, asm, ZPR16, ZPR16>;
2648 def _S : sve2_int_absdiff_accum<0b10, { 0b111, opc }, asm, ZPR32, ZPR32>;
2649 def _D : sve2_int_absdiff_accum<0b11, { 0b111, opc }, asm, ZPR64, ZPR64>;
2652 multiclass sve2_int_absdiff_accum_long<bits<2> opc, string asm> {
2653 def _H : sve2_int_absdiff_accum<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
2654 def _S : sve2_int_absdiff_accum<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
2655 def _D : sve2_int_absdiff_accum<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
2658 multiclass sve2_int_addsub_long_carry<bits<2> opc, string asm> {
2659 def _S : sve2_int_absdiff_accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm,
2661 def _D : sve2_int_absdiff_accum<{ opc{1}, 0b1 }, { 0b010, opc{0} }, asm,
2665 //===----------------------------------------------------------------------===//
2666 // SVE2 Narrowing Group
2667 //===----------------------------------------------------------------------===//
2669 class sve2_int_bin_shift_imm_narrow_bottom<bits<3> tsz8_64, bits<3> opc,
2670 string asm, ZPRRegOp zprty1,
2671 ZPRRegOp zprty2, Operand immtype>
2672 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, immtype:$imm),
2673 asm, "\t$Zd, $Zn, $imm",
2674 "", []>, Sched<[]> {
2678 let Inst{31-23} = 0b010001010;
2679 let Inst{22} = tsz8_64{2};
2681 let Inst{20-19} = tsz8_64{1-0};
2682 let Inst{18-16} = imm{2-0}; // imm3
2683 let Inst{15-14} = 0b00;
2684 let Inst{13-11} = opc;
2690 multiclass sve2_int_bin_shift_imm_right_narrow_bottom<bits<3> opc, string asm> {
2691 def _B : sve2_int_bin_shift_imm_narrow_bottom<{0,0,1}, opc, asm, ZPR8, ZPR16,
2693 def _H : sve2_int_bin_shift_imm_narrow_bottom<{0,1,?}, opc, asm, ZPR16, ZPR32,
2695 let Inst{19} = imm{3};
2697 def _S : sve2_int_bin_shift_imm_narrow_bottom<{1,?,?}, opc, asm, ZPR32, ZPR64,
2699 let Inst{20-19} = imm{4-3};
2703 class sve2_int_bin_shift_imm_narrow_top<bits<3> tsz8_64, bits<3> opc,
2704 string asm, ZPRRegOp zprty1,
2705 ZPRRegOp zprty2, Operand immtype>
2706 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, immtype:$imm),
2707 asm, "\t$Zd, $Zn, $imm",
2708 "", []>, Sched<[]> {
2712 let Inst{31-23} = 0b010001010;
2713 let Inst{22} = tsz8_64{2};
2715 let Inst{20-19} = tsz8_64{1-0};
2716 let Inst{18-16} = imm{2-0}; // imm3
2717 let Inst{15-14} = 0b00;
2718 let Inst{13-11} = opc;
2723 let Constraints = "$Zd = $_Zd";
2726 multiclass sve2_int_bin_shift_imm_right_narrow_top<bits<3> opc, string asm> {
2727 def _B : sve2_int_bin_shift_imm_narrow_top<{0,0,1}, opc, asm, ZPR8, ZPR16,
2729 def _H : sve2_int_bin_shift_imm_narrow_top<{0,1,?}, opc, asm, ZPR16, ZPR32,
2731 let Inst{19} = imm{3};
2733 def _S : sve2_int_bin_shift_imm_narrow_top<{1,?,?}, opc, asm, ZPR32, ZPR64,
2735 let Inst{20-19} = imm{4-3};
2739 class sve2_int_addsub_narrow_high_bottom<bits<2> sz, bits<2> opc, string asm,
2740 ZPRRegOp zprty1, ZPRRegOp zprty2>
2741 : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty2:$Zm),
2742 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2746 let Inst{31-24} = 0b01000101;
2747 let Inst{23-22} = sz;
2749 let Inst{20-16} = Zm;
2750 let Inst{15-13} = 0b011;
2751 let Inst{12-11} = opc; // S, R
2752 let Inst{10} = 0b0; // Top
2757 multiclass sve2_int_addsub_narrow_high_bottom<bits<2> opc, string asm> {
2758 def _B : sve2_int_addsub_narrow_high_bottom<0b01, opc, asm, ZPR8, ZPR16>;
2759 def _H : sve2_int_addsub_narrow_high_bottom<0b10, opc, asm, ZPR16, ZPR32>;
2760 def _S : sve2_int_addsub_narrow_high_bottom<0b11, opc, asm, ZPR32, ZPR64>;
2763 class sve2_int_addsub_narrow_high_top<bits<2> sz, bits<2> opc, string asm,
2764 ZPRRegOp zprty1, ZPRRegOp zprty2>
2765 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn, zprty2:$Zm),
2766 asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
2770 let Inst{31-24} = 0b01000101;
2771 let Inst{23-22} = sz;
2773 let Inst{20-16} = Zm;
2774 let Inst{15-13} = 0b011;
2775 let Inst{12-11} = opc; // S, R
2776 let Inst{10} = 0b1; // Top
2780 let Constraints = "$Zd = $_Zd";
2783 multiclass sve2_int_addsub_narrow_high_top<bits<2> opc, string asm> {
2784 def _B : sve2_int_addsub_narrow_high_top<0b01, opc, asm, ZPR8, ZPR16>;
2785 def _H : sve2_int_addsub_narrow_high_top<0b10, opc, asm, ZPR16, ZPR32>;
2786 def _S : sve2_int_addsub_narrow_high_top<0b11, opc, asm, ZPR32, ZPR64>;
2789 class sve2_int_sat_extract_narrow_bottom<bits<3> tsz8_64, bits<2> opc, string asm,
2790 ZPRRegOp zprty1, ZPRRegOp zprty2>
2791 : I<(outs zprty1:$Zd), (ins zprty2:$Zn),
2792 asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
2795 let Inst{31-23} = 0b010001010;
2796 let Inst{22} = tsz8_64{2};
2798 let Inst{20-19} = tsz8_64{1-0};
2799 let Inst{18-13} = 0b000010;
2800 let Inst{12-11} = opc;
2806 multiclass sve2_int_sat_extract_narrow_bottom<bits<2> opc, string asm> {
2807 def _B : sve2_int_sat_extract_narrow_bottom<0b001, opc, asm, ZPR8, ZPR16>;
2808 def _H : sve2_int_sat_extract_narrow_bottom<0b010, opc, asm, ZPR16, ZPR32>;
2809 def _S : sve2_int_sat_extract_narrow_bottom<0b100, opc, asm, ZPR32, ZPR64>;
2812 class sve2_int_sat_extract_narrow_top<bits<3> tsz8_64, bits<2> opc, string asm,
2813 ZPRRegOp zprty1, ZPRRegOp zprty2>
2814 : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, zprty2:$Zn),
2815 asm, "\t$Zd, $Zn", "", []>, Sched<[]> {
2818 let Inst{31-23} = 0b010001010;
2819 let Inst{22} = tsz8_64{2};
2821 let Inst{20-19} = tsz8_64{1-0};
2822 let Inst{18-13} = 0b000010;
2823 let Inst{12-11} = opc;
2828 let Constraints = "$Zd = $_Zd";
2831 multiclass sve2_int_sat_extract_narrow_top<bits<2> opc, string asm> {
2832 def _B : sve2_int_sat_extract_narrow_top<0b001, opc, asm, ZPR8, ZPR16>;
2833 def _H : sve2_int_sat_extract_narrow_top<0b010, opc, asm, ZPR16, ZPR32>;
2834 def _S : sve2_int_sat_extract_narrow_top<0b100, opc, asm, ZPR32, ZPR64>;
2837 //===----------------------------------------------------------------------===//
2838 // SVE Integer Arithmetic - Unary Predicated Group
2839 //===----------------------------------------------------------------------===//
2841 class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
2842 string asm, ZPRRegOp zprty>
2843 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
2844 asm, "\t$Zd, $Pg/m, $Zn",
2850 let Inst{31-24} = 0b00000100;
2851 let Inst{23-22} = sz8_64;
2852 let Inst{21-20} = 0b01;
2853 let Inst{19} = opc{0};
2854 let Inst{18-16} = opc{3-1};
2855 let Inst{15-13} = 0b101;
2856 let Inst{12-10} = Pg;
2860 let Constraints = "$Zd = $_Zd";
2861 let DestructiveInstType = Destructive;
2862 let ElementSize = zprty.ElementSize;
2865 multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm,
2866 SDPatternOperator op> {
2867 def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>;
2868 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
2869 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
2870 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
2872 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
2873 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
2874 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
2875 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
2878 multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm> {
2879 def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
2880 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
2881 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
2884 multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm> {
2885 def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
2886 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
2889 multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm> {
2890 def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
2893 multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm,
2894 SDPatternOperator op> {
2895 def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>;
2896 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
2897 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
2898 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
2900 def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
2901 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
2902 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
2903 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
2905 def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
2906 def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
2907 def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
2910 multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm> {
2911 def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
2912 def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
2913 def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
2916 //===----------------------------------------------------------------------===//
2917 // SVE Integer Wide Immediate - Unpredicated Group
2918 //===----------------------------------------------------------------------===//
2919 class sve_int_dup_imm<bits<2> sz8_64, string asm,
2920 ZPRRegOp zprty, Operand immtype>
2921 : I<(outs zprty:$Zd), (ins immtype:$imm),
2927 let Inst{31-24} = 0b00100101;
2928 let Inst{23-22} = sz8_64;
2929 let Inst{21-14} = 0b11100011;
2930 let Inst{13} = imm{8}; // sh
2931 let Inst{12-5} = imm{7-0}; // imm8
2934 let isReMaterializable = 1;
2937 multiclass sve_int_dup_imm<string asm> {
2938 def _B : sve_int_dup_imm<0b00, asm, ZPR8, cpy_imm8_opt_lsl_i8>;
2939 def _H : sve_int_dup_imm<0b01, asm, ZPR16, cpy_imm8_opt_lsl_i16>;
2940 def _S : sve_int_dup_imm<0b10, asm, ZPR32, cpy_imm8_opt_lsl_i32>;
2941 def _D : sve_int_dup_imm<0b11, asm, ZPR64, cpy_imm8_opt_lsl_i64>;
2943 def : InstAlias<"mov $Zd, $imm",
2944 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm), 1>;
2945 def : InstAlias<"mov $Zd, $imm",
2946 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm), 1>;
2947 def : InstAlias<"mov $Zd, $imm",
2948 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm), 1>;
2949 def : InstAlias<"mov $Zd, $imm",
2950 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm), 1>;
2952 def : InstAlias<"fmov $Zd, #0.0",
2953 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, 0, 0), 1>;
2954 def : InstAlias<"fmov $Zd, #0.0",
2955 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>;
2956 def : InstAlias<"fmov $Zd, #0.0",
2957 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, 0, 0), 1>;
2960 class sve_int_dup_fpimm<bits<2> sz8_64, Operand fpimmtype,
2961 string asm, ZPRRegOp zprty>
2962 : I<(outs zprty:$Zd), (ins fpimmtype:$imm8),
2963 asm, "\t$Zd, $imm8",
2968 let Inst{31-24} = 0b00100101;
2969 let Inst{23-22} = sz8_64;
2970 let Inst{21-14} = 0b11100111;
2972 let Inst{12-5} = imm8;
2975 let isReMaterializable = 1;
2978 multiclass sve_int_dup_fpimm<string asm> {
2979 def _H : sve_int_dup_fpimm<0b01, fpimm16, asm, ZPR16>;
2980 def _S : sve_int_dup_fpimm<0b10, fpimm32, asm, ZPR32>;
2981 def _D : sve_int_dup_fpimm<0b11, fpimm64, asm, ZPR64>;
2983 def : InstAlias<"fmov $Zd, $imm8",
2984 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, fpimm16:$imm8), 1>;
2985 def : InstAlias<"fmov $Zd, $imm8",
2986 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, fpimm32:$imm8), 1>;
2987 def : InstAlias<"fmov $Zd, $imm8",
2988 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, fpimm64:$imm8), 1>;
2991 class sve_int_arith_imm0<bits<2> sz8_64, bits<3> opc, string asm,
2992 ZPRRegOp zprty, Operand immtype>
2993 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
2994 asm, "\t$Zdn, $_Zdn, $imm",
2999 let Inst{31-24} = 0b00100101;
3000 let Inst{23-22} = sz8_64;
3001 let Inst{21-19} = 0b100;
3002 let Inst{18-16} = opc;
3003 let Inst{15-14} = 0b11;
3004 let Inst{13} = imm{8}; // sh
3005 let Inst{12-5} = imm{7-0}; // imm8
3006 let Inst{4-0} = Zdn;
3008 let Constraints = "$Zdn = $_Zdn";
3009 let DestructiveInstType = Destructive;
3010 let ElementSize = ElementSizeNone;
3013 multiclass sve_int_arith_imm0<bits<3> opc, string asm> {
3014 def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>;
3015 def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>;
3016 def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>;
3017 def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>;
3020 class sve_int_arith_imm<bits<2> sz8_64, bits<6> opc, string asm,
3021 ZPRRegOp zprty, Operand immtype>
3022 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
3023 asm, "\t$Zdn, $_Zdn, $imm",
3028 let Inst{31-24} = 0b00100101;
3029 let Inst{23-22} = sz8_64;
3030 let Inst{21-16} = opc;
3031 let Inst{15-13} = 0b110;
3032 let Inst{12-5} = imm;
3033 let Inst{4-0} = Zdn;
3035 let Constraints = "$Zdn = $_Zdn";
3036 let DestructiveInstType = Destructive;
3037 let ElementSize = ElementSizeNone;
3040 multiclass sve_int_arith_imm1<bits<2> opc, string asm, Operand immtype> {
3041 def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, immtype>;
3042 def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, immtype>;
3043 def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, immtype>;
3044 def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, immtype>;
3047 multiclass sve_int_arith_imm2<string asm> {
3048 def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>;
3049 def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>;
3050 def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>;
3051 def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>;
3054 //===----------------------------------------------------------------------===//
3055 // SVE Bitwise Logical - Unpredicated Group
3056 //===----------------------------------------------------------------------===//
3058 class sve_int_bin_cons_log<bits<2> opc, string asm>
3059 : I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm),
3060 asm, "\t$Zd, $Zn, $Zm",
3066 let Inst{31-24} = 0b00000100;
3067 let Inst{23-22} = opc{1-0};
3069 let Inst{20-16} = Zm;
3070 let Inst{15-10} = 0b001100;
3075 multiclass sve_int_bin_cons_log<bits<2> opc, string asm> {
3076 def NAME : sve_int_bin_cons_log<opc, asm>;
3078 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
3079 (!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>;
3080 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
3081 (!cast<Instruction>(NAME) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 1>;
3082 def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
3083 (!cast<Instruction>(NAME) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 1>;
3086 class sve2_int_bitwise_ternary_op_d<bits<3> opc, string asm>
3087 : I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, ZPR64:$Zm, ZPR64:$Zk),
3088 asm, "\t$Zdn, $_Zdn, $Zm, $Zk",
3094 let Inst{31-24} = 0b00000100;
3095 let Inst{23-22} = opc{2-1};
3097 let Inst{20-16} = Zm;
3098 let Inst{15-11} = 0b00111;
3099 let Inst{10} = opc{0};
3101 let Inst{4-0} = Zdn;
3103 let Constraints = "$Zdn = $_Zdn";
3104 let DestructiveInstType = Destructive;
3105 let ElementSize = ElementSizeNone;
3108 multiclass sve2_int_bitwise_ternary_op<bits<3> opc, string asm> {
3109 def NAME : sve2_int_bitwise_ternary_op_d<opc, asm>;
3111 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
3112 (!cast<Instruction>(NAME) ZPR8:$Zdn, ZPR8:$Zm, ZPR8:$Zk), 1>;
3113 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
3114 (!cast<Instruction>(NAME) ZPR16:$Zdn, ZPR16:$Zm, ZPR16:$Zk), 1>;
3115 def : InstAlias<asm # "\t$Zdn, $Zdn, $Zm, $Zk",
3116 (!cast<Instruction>(NAME) ZPR32:$Zdn, ZPR32:$Zm, ZPR32:$Zk), 1>;
3119 class sve2_int_rotate_right_imm<bits<4> tsz8_64, string asm,
3120 ZPRRegOp zprty, Operand immtype>
3121 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, immtype:$imm),
3122 asm, "\t$Zdn, $_Zdn, $Zm, $imm",
3128 let Inst{31-24} = 0b00000100;
3129 let Inst{23-22} = tsz8_64{3-2};
3131 let Inst{20-19} = tsz8_64{1-0};
3132 let Inst{18-16} = imm{2-0}; // imm3
3133 let Inst{15-10} = 0b001101;
3135 let Inst{4-0} = Zdn;
3137 let Constraints = "$Zdn = $_Zdn";
3138 let DestructiveInstType = Destructive;
3139 let ElementSize = ElementSizeNone;
3142 multiclass sve2_int_rotate_right_imm<string asm> {
3143 def _B : sve2_int_rotate_right_imm<{0,0,0,1}, asm, ZPR8, vecshiftR8>;
3144 def _H : sve2_int_rotate_right_imm<{0,0,1,?}, asm, ZPR16, vecshiftR16> {
3145 let Inst{19} = imm{3};
3147 def _S : sve2_int_rotate_right_imm<{0,1,?,?}, asm, ZPR32, vecshiftR32> {
3148 let Inst{20-19} = imm{4-3};
3150 def _D : sve2_int_rotate_right_imm<{1,?,?,?}, asm, ZPR64, vecshiftR64> {
3151 let Inst{22} = imm{5};
3152 let Inst{20-19} = imm{4-3};
3156 //===----------------------------------------------------------------------===//
3157 // SVE Integer Wide Immediate - Predicated Group
3158 //===----------------------------------------------------------------------===//
3160 class sve_int_dup_fpimm_pred<bits<2> sz, Operand fpimmtype,
3161 string asm, ZPRRegOp zprty>
3162 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8),
3163 asm, "\t$Zd, $Pg/m, $imm8",
3169 let Inst{31-24} = 0b00000101;
3170 let Inst{23-22} = sz;
3171 let Inst{21-20} = 0b01;
3172 let Inst{19-16} = Pg;
3173 let Inst{15-13} = 0b110;
3174 let Inst{12-5} = imm8;
3177 let Constraints = "$Zd = $_Zd";
3178 let DestructiveInstType = Destructive;
3179 let ElementSize = zprty.ElementSize;
3182 multiclass sve_int_dup_fpimm_pred<string asm> {
3183 def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>;
3184 def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>;
3185 def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>;
3187 def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
3188 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8), 1>;
3189 def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
3190 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8), 1>;
3191 def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
3192 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8), 1>;
3195 class sve_int_dup_imm_pred<bits<2> sz8_64, bit m, string asm,
3196 ZPRRegOp zprty, string pred_qual, dag iops>
3197 : I<(outs zprty:$Zd), iops,
3198 asm, "\t$Zd, $Pg"#pred_qual#", $imm",
3199 "", []>, Sched<[]> {
3203 let Inst{31-24} = 0b00000101;
3204 let Inst{23-22} = sz8_64;
3205 let Inst{21-20} = 0b01;
3206 let Inst{19-16} = Pg;
3209 let Inst{13} = imm{8}; // sh
3210 let Inst{12-5} = imm{7-0}; // imm8
3213 let DestructiveInstType = Destructive;
3214 let ElementSize = zprty.ElementSize;
3217 multiclass sve_int_dup_imm_pred_merge<string asm> {
3218 let Constraints = "$Zd = $_Zd" in {
3219 def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>;
3220 def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>;
3221 def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>;
3222 def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>;
3225 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3226 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>;
3227 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3228 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>;
3229 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3230 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>;
3231 def : InstAlias<"mov $Zd, $Pg/m, $imm",
3232 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>;
3234 def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
3235 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, 0, 0), 0>;
3236 def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
3237 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, 0, 0), 0>;
3238 def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
3239 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, 0, 0), 0>;
3242 multiclass sve_int_dup_imm_pred_zero<string asm> {
3243 def _B : sve_int_dup_imm_pred<0b00, 0, asm, ZPR8, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>;
3244 def _H : sve_int_dup_imm_pred<0b01, 0, asm, ZPR16, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>;
3245 def _S : sve_int_dup_imm_pred<0b10, 0, asm, ZPR32, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>;
3246 def _D : sve_int_dup_imm_pred<0b11, 0, asm, ZPR64, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>;
3248 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3249 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>;
3250 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3251 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>;
3252 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3253 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>;
3254 def : InstAlias<"mov $Zd, $Pg/z, $imm",
3255 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>;
3258 //===----------------------------------------------------------------------===//
3259 // SVE Integer Compare - Vectors Group
3260 //===----------------------------------------------------------------------===//
3262 class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
3263 PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2>
3264 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm),
3265 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
3272 let Inst{31-24} = 0b00100100;
3273 let Inst{23-22} = sz8_64;
3275 let Inst{20-16} = Zm;
3276 let Inst{15} = opc{2};
3277 let Inst{14} = cmp_1;
3278 let Inst{13} = opc{1};
3279 let Inst{12-10} = Pg;
3281 let Inst{4} = opc{0};
3287 multiclass sve_int_cmp_0<bits<3> opc, string asm> {
3288 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>;
3289 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>;
3290 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>;
3291 def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>;
3294 multiclass sve_int_cmp_0_wide<bits<3> opc, string asm> {
3295 def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
3296 def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
3297 def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
3300 multiclass sve_int_cmp_1_wide<bits<3> opc, string asm> {
3301 def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
3302 def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
3303 def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
3307 //===----------------------------------------------------------------------===//
3308 // SVE Integer Compare - Signed Immediate Group
3309 //===----------------------------------------------------------------------===//
3311 class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
3314 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
3315 asm, "\t$Pd, $Pg/z, $Zn, $imm5",
3322 let Inst{31-24} = 0b00100101;
3323 let Inst{23-22} = sz8_64;
3325 let Inst{20-16} = imm5;
3326 let Inst{15} = opc{2};
3328 let Inst{13} = opc{1};
3329 let Inst{12-10} = Pg;
3331 let Inst{4} = opc{0};
3337 multiclass sve_int_scmp_vi<bits<3> opc, string asm> {
3338 def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>;
3339 def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>;
3340 def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>;
3341 def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>;
3345 //===----------------------------------------------------------------------===//
3346 // SVE Integer Compare - Unsigned Immediate Group
3347 //===----------------------------------------------------------------------===//
3349 class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
3350 ZPRRegOp zprty, Operand immtype>
3351 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
3352 asm, "\t$Pd, $Pg/z, $Zn, $imm7",
3359 let Inst{31-24} = 0b00100100;
3360 let Inst{23-22} = sz8_64;
3362 let Inst{20-14} = imm7;
3363 let Inst{13} = opc{1};
3364 let Inst{12-10} = Pg;
3366 let Inst{4} = opc{0};
3372 multiclass sve_int_ucmp_vi<bits<2> opc, string asm> {
3373 def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>;
3374 def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>;
3375 def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>;
3376 def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127>;
3380 //===----------------------------------------------------------------------===//
3381 // SVE Integer Compare - Scalars Group
3382 //===----------------------------------------------------------------------===//
3384 class sve_int_cterm<bit sz, bit opc, string asm, RegisterClass rt>
3385 : I<(outs), (ins rt:$Rn, rt:$Rm),
3391 let Inst{31-23} = 0b001001011;
3394 let Inst{20-16} = Rm;
3395 let Inst{15-10} = 0b001000;
3398 let Inst{3-0} = 0b0000;
3403 class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm,
3404 RegisterClass gprty, PPRRegOp pprty>
3405 : I<(outs pprty:$Pd), (ins gprty:$Rn, gprty:$Rm),
3406 asm, "\t$Pd, $Rn, $Rm",
3407 "", []>, Sched<[]> {
3411 let Inst{31-24} = 0b00100101;
3412 let Inst{23-22} = sz8_64;
3414 let Inst{20-16} = Rm;
3415 let Inst{15-13} = 0b000;
3416 let Inst{12-10} = opc{3-1};
3418 let Inst{4} = opc{0};
3424 multiclass sve_int_while4_rr<bits<3> opc, string asm> {
3425 def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8>;
3426 def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16>;
3427 def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32>;
3428 def _D : sve_int_while_rr<0b11, { 0, opc }, asm, GPR32, PPR64>;
3431 multiclass sve_int_while8_rr<bits<3> opc, string asm> {
3432 def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>;
3433 def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>;
3434 def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>;
3435 def _D : sve_int_while_rr<0b11, { 1, opc }, asm, GPR64, PPR64>;
3438 class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm,
3440 : I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm),
3441 asm, "\t$Pd, $Rn, $Rm",
3442 "", []>, Sched<[]> {
3446 let Inst{31-24} = 0b00100101;
3447 let Inst{23-22} = sz8_64;
3449 let Inst{20-16} = Rm;
3450 let Inst{15-10} = 0b001100;
3458 multiclass sve2_int_while_rr<bits<1> rw, string asm> {
3459 def _B : sve2_int_while_rr<0b00, rw, asm, PPR8>;
3460 def _H : sve2_int_while_rr<0b01, rw, asm, PPR16>;
3461 def _S : sve2_int_while_rr<0b10, rw, asm, PPR32>;
3462 def _D : sve2_int_while_rr<0b11, rw, asm, PPR64>;
3465 //===----------------------------------------------------------------------===//
3466 // SVE Floating Point Fast Reduction Group
3467 //===----------------------------------------------------------------------===//
3469 class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm,
3470 ZPRRegOp zprty, RegisterClass dstRegClass>
3471 : I<(outs dstRegClass:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
3472 asm, "\t$Vd, $Pg, $Zn",
3478 let Inst{31-24} = 0b01100101;
3479 let Inst{23-22} = sz;
3480 let Inst{21-19} = 0b000;
3481 let Inst{18-16} = opc;
3482 let Inst{15-13} = 0b001;
3483 let Inst{12-10} = Pg;
3488 multiclass sve_fp_fast_red<bits<3> opc, string asm> {
3489 def _H : sve_fp_fast_red<0b01, opc, asm, ZPR16, FPR16>;
3490 def _S : sve_fp_fast_red<0b10, opc, asm, ZPR32, FPR32>;
3491 def _D : sve_fp_fast_red<0b11, opc, asm, ZPR64, FPR64>;
3495 //===----------------------------------------------------------------------===//
3496 // SVE Floating Point Accumulating Reduction Group
3497 //===----------------------------------------------------------------------===//
3499 class sve_fp_2op_p_vd<bits<2> sz, bits<3> opc, string asm,
3500 ZPRRegOp zprty, RegisterClass dstRegClass>
3501 : I<(outs dstRegClass:$Vdn), (ins PPR3bAny:$Pg, dstRegClass:$_Vdn, zprty:$Zm),
3502 asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
3509 let Inst{31-24} = 0b01100101;
3510 let Inst{23-22} = sz;
3511 let Inst{21-19} = 0b011;
3512 let Inst{18-16} = opc;
3513 let Inst{15-13} = 0b001;
3514 let Inst{12-10} = Pg;
3516 let Inst{4-0} = Vdn;
3518 let Constraints = "$Vdn = $_Vdn";
3521 multiclass sve_fp_2op_p_vd<bits<3> opc, string asm> {
3522 def _H : sve_fp_2op_p_vd<0b01, opc, asm, ZPR16, FPR16>;
3523 def _S : sve_fp_2op_p_vd<0b10, opc, asm, ZPR32, FPR32>;
3524 def _D : sve_fp_2op_p_vd<0b11, opc, asm, ZPR64, FPR64>;
3527 //===----------------------------------------------------------------------===//
3528 // SVE Floating Point Compare - Vectors Group
3529 //===----------------------------------------------------------------------===//
3531 class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
3533 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
3534 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
3541 let Inst{31-24} = 0b01100101;
3542 let Inst{23-22} = sz;
3544 let Inst{20-16} = Zm;
3545 let Inst{15} = opc{2};
3547 let Inst{13} = opc{1};
3548 let Inst{12-10} = Pg;
3550 let Inst{4} = opc{0};
3554 multiclass sve_fp_3op_p_pd<bits<3> opc, string asm> {
3555 def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
3556 def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
3557 def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
3561 //===----------------------------------------------------------------------===//
3562 // SVE Floating Point Compare - with Zero Group
3563 //===----------------------------------------------------------------------===//
3565 class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
3567 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn),
3568 asm, "\t$Pd, $Pg/z, $Zn, #0.0",
3574 let Inst{31-24} = 0b01100101;
3575 let Inst{23-22} = sz;
3576 let Inst{21-18} = 0b0100;
3577 let Inst{17-16} = opc{2-1};
3578 let Inst{15-13} = 0b001;
3579 let Inst{12-10} = Pg;
3581 let Inst{4} = opc{0};
3585 multiclass sve_fp_2op_p_pd<bits<3> opc, string asm> {
3586 def _H : sve_fp_2op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
3587 def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
3588 def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
3592 //===----------------------------------------------------------------------===//
3593 //SVE Index Generation Group
3594 //===----------------------------------------------------------------------===//
3596 class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
3598 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
3599 asm, "\t$Zd, $imm5, $imm5b",
3600 "", []>, Sched<[]> {
3604 let Inst{31-24} = 0b00000100;
3605 let Inst{23-22} = sz8_64;
3607 let Inst{20-16} = imm5b;
3608 let Inst{15-10} = 0b010000;
3609 let Inst{9-5} = imm5;
3613 multiclass sve_int_index_ii<string asm> {
3614 def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>;
3615 def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>;
3616 def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
3617 def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
3620 class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty,
3621 RegisterClass srcRegType, Operand imm_ty>
3622 : I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm),
3623 asm, "\t$Zd, $imm5, $Rm",
3624 "", []>, Sched<[]> {
3628 let Inst{31-24} = 0b00000100;
3629 let Inst{23-22} = sz8_64;
3631 let Inst{20-16} = Rm;
3632 let Inst{15-10} = 0b010010;
3633 let Inst{9-5} = imm5;
3637 multiclass sve_int_index_ir<string asm> {
3638 def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>;
3639 def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>;
3640 def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
3641 def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
3644 class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty,
3645 RegisterClass srcRegType, Operand imm_ty>
3646 : I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5),
3647 asm, "\t$Zd, $Rn, $imm5",
3648 "", []>, Sched<[]> {
3652 let Inst{31-24} = 0b00000100;
3653 let Inst{23-22} = sz8_64;
3655 let Inst{20-16} = imm5;
3656 let Inst{15-10} = 0b010001;
3661 multiclass sve_int_index_ri<string asm> {
3662 def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>;
3663 def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>;
3664 def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
3665 def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
3668 class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty,
3669 RegisterClass srcRegType>
3670 : I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm),
3671 asm, "\t$Zd, $Rn, $Rm",
3672 "", []>, Sched<[]> {
3676 let Inst{31-24} = 0b00000100;
3677 let Inst{23-22} = sz8_64;
3679 let Inst{20-16} = Rm;
3680 let Inst{15-10} = 0b010011;
3685 multiclass sve_int_index_rr<string asm> {
3686 def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>;
3687 def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
3688 def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
3689 def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
3692 //===----------------------------------------------------------------------===//
3693 // SVE Bitwise Shift - Predicated Group
3694 //===----------------------------------------------------------------------===//
3695 class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm,
3696 ZPRRegOp zprty, Operand immtype,
3697 ElementSizeEnum size>
3698 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
3699 asm, "\t$Zdn, $Pg/m, $_Zdn, $imm",
3705 let Inst{31-24} = 0b00000100;
3706 let Inst{23-22} = tsz8_64{3-2};
3707 let Inst{21-20} = 0b00;
3708 let Inst{19-16} = opc;
3709 let Inst{15-13} = 0b100;
3710 let Inst{12-10} = Pg;
3711 let Inst{9-8} = tsz8_64{1-0};
3712 let Inst{7-5} = imm{2-0}; // imm3
3713 let Inst{4-0} = Zdn;
3715 let Constraints = "$Zdn = $_Zdn";
3716 let DestructiveInstType = Destructive;
3717 let ElementSize = size;
3720 multiclass sve_int_bin_pred_shift_imm_left<bits<4> opc, string asm> {
3721 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8,
3723 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16,
3725 let Inst{8} = imm{3};
3727 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32,
3729 let Inst{9-8} = imm{4-3};
3731 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64,
3733 let Inst{22} = imm{5};
3734 let Inst{9-8} = imm{4-3};
3738 multiclass sve_int_bin_pred_shift_imm_right<bits<4> opc, string asm> {
3739 def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8,
3741 def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16,
3743 let Inst{8} = imm{3};
3745 def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32,
3747 let Inst{9-8} = imm{4-3};
3749 def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64,
3751 let Inst{22} = imm{5};
3752 let Inst{9-8} = imm{4-3};
3756 class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
3757 string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
3758 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
3759 asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
3765 let Inst{31-24} = 0b00000100;
3766 let Inst{23-22} = sz8_64;
3767 let Inst{21-20} = 0b01;
3768 let Inst{19} = wide;
3769 let Inst{18-16} = opc;
3770 let Inst{15-13} = 0b100;
3771 let Inst{12-10} = Pg;
3773 let Inst{4-0} = Zdn;
3775 let Constraints = "$Zdn = $_Zdn";
3776 let DestructiveInstType = Destructive;
3777 let ElementSize = zprty.ElementSize;
3780 multiclass sve_int_bin_pred_shift<bits<3> opc, string asm> {
3781 def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>;
3782 def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>;
3783 def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>;
3784 def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>;
3787 multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm> {
3788 def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>;
3789 def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>;
3790 def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>;
3793 //===----------------------------------------------------------------------===//
3794 // SVE Shift - Unpredicated Group
3795 //===----------------------------------------------------------------------===//
3797 class sve_int_bin_cons_shift_wide<bits<2> sz8_64, bits<2> opc, string asm,
3799 : I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm),
3800 asm, "\t$Zd, $Zn, $Zm",
3806 let Inst{31-24} = 0b00000100;
3807 let Inst{23-22} = sz8_64;
3809 let Inst{20-16} = Zm;
3810 let Inst{15-12} = 0b1000;
3811 let Inst{11-10} = opc;
3816 multiclass sve_int_bin_cons_shift_wide<bits<2> opc, string asm> {
3817 def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>;
3818 def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>;
3819 def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>;
3822 class sve_int_bin_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
3823 ZPRRegOp zprty, Operand immtype>
3824 : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
3825 asm, "\t$Zd, $Zn, $imm",
3826 "", []>, Sched<[]> {
3830 let Inst{31-24} = 0b00000100;
3831 let Inst{23-22} = tsz8_64{3-2};
3833 let Inst{20-19} = tsz8_64{1-0};
3834 let Inst{18-16} = imm{2-0}; // imm3
3835 let Inst{15-12} = 0b1001;
3836 let Inst{11-10} = opc;
3841 multiclass sve_int_bin_cons_shift_imm_left<bits<2> opc, string asm> {
3842 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
3843 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
3844 let Inst{19} = imm{3};
3846 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
3847 let Inst{20-19} = imm{4-3};
3849 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
3850 let Inst{22} = imm{5};
3851 let Inst{20-19} = imm{4-3};
3855 multiclass sve_int_bin_cons_shift_imm_right<bits<2> opc, string asm> {
3856 def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
3857 def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
3858 let Inst{19} = imm{3};
3860 def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
3861 let Inst{20-19} = imm{4-3};
3863 def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
3864 let Inst{22} = imm{5};
3865 let Inst{20-19} = imm{4-3};
3868 //===----------------------------------------------------------------------===//
3869 // SVE Memory - Store Group
3870 //===----------------------------------------------------------------------===//
3872 class sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
3873 RegisterOperand VecList>
3874 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
3875 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
3882 let Inst{31-25} = 0b1110010;
3883 let Inst{24-23} = msz;
3884 let Inst{22-21} = esz;
3886 let Inst{19-16} = imm4;
3887 let Inst{15-13} = 0b111;
3888 let Inst{12-10} = Pg;
3895 multiclass sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
3896 RegisterOperand listty, ZPRRegOp zprty>
3898 def NAME : sve_mem_cst_si<msz, esz, asm, listty>;
3900 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
3901 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
3902 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
3903 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
3904 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
3905 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
3908 class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
3909 string asm, Operand immtype>
3910 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
3911 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
3918 let Inst{31-25} = 0b1110010;
3919 let Inst{24-23} = sz;
3920 let Inst{22-21} = nregs;
3922 let Inst{19-16} = imm4;
3923 let Inst{15-13} = 0b111;
3924 let Inst{12-10} = Pg;
3931 multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
3932 string asm, Operand immtype> {
3933 def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>;
3935 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
3936 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
3939 class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
3940 string asm, RegisterOperand gprty>
3941 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
3942 asm, "\t$Zt, $Pg, [$Rn, $Rm]",
3949 let Inst{31-25} = 0b1110010;
3950 let Inst{24-23} = sz;
3951 let Inst{22-21} = nregs;
3952 let Inst{20-16} = Rm;
3953 let Inst{15-13} = 0b011;
3954 let Inst{12-10} = Pg;
3961 class sve_mem_cst_ss_base<bits<4> dtype, string asm,
3962 RegisterOperand listty, RegisterOperand gprty>
3963 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
3964 asm, "\t$Zt, $Pg, [$Rn, $Rm]",
3971 let Inst{31-25} = 0b1110010;
3972 let Inst{24-21} = dtype;
3973 let Inst{20-16} = Rm;
3974 let Inst{15-13} = 0b010;
3975 let Inst{12-10} = Pg;
3982 multiclass sve_mem_cst_ss<bits<4> dtype, string asm,
3983 RegisterOperand listty, ZPRRegOp zprty,
3984 RegisterOperand gprty> {
3985 def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>;
3987 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
3988 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
3991 class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList>
3992 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
3993 asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
4000 let Inst{31-25} = 0b1110010;
4001 let Inst{24-23} = msz;
4002 let Inst{22-20} = 0b001;
4003 let Inst{19-16} = imm4;
4004 let Inst{15-13} = 0b111;
4005 let Inst{12-10} = Pg;
4012 multiclass sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand listty,
4014 def NAME : sve_mem_cstnt_si<msz, asm, listty>;
4016 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
4017 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
4018 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
4019 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
4020 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
4021 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4024 class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty,
4025 RegisterOperand gprty>
4026 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4027 asm, "\t$Zt, $Pg, [$Rn, $Rm]",
4034 let Inst{31-25} = 0b1110010;
4035 let Inst{24-23} = msz;
4036 let Inst{22-21} = 0b00;
4037 let Inst{20-16} = Rm;
4038 let Inst{15-13} = 0b011;
4039 let Inst{12-10} = Pg;
4046 multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty,
4047 ZPRRegOp zprty, RegisterOperand gprty> {
4048 def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>;
4050 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
4051 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
4054 class sve2_mem_sstnt_vs_base<bits<3> opc, string asm,
4055 RegisterOperand listty, ZPRRegOp zprty>
4056 : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
4057 asm, "\t$Zt, $Pg, [$Zn, $Rm]",
4064 let Inst{31-25} = 0b1110010;
4065 let Inst{24-22} = opc;
4067 let Inst{20-16} = Rm;
4068 let Inst{15-13} = 0b001;
4069 let Inst{12-10} = Pg;
4076 multiclass sve2_mem_sstnt_vs<bits<3> opc, string asm,
4077 RegisterOperand listty, ZPRRegOp zprty> {
4078 def _REAL : sve2_mem_sstnt_vs_base<opc, asm, listty, zprty>;
4080 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
4081 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
4082 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4083 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
4084 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4085 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
4088 class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
4089 RegisterOperand VecList, RegisterOperand zprext>
4090 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
4091 asm, "\t$Zt, $Pg, [$Rn, $Zm]",
4098 let Inst{31-25} = 0b1110010;
4099 let Inst{24-22} = opc;
4100 let Inst{21} = scaled;
4101 let Inst{20-16} = Zm;
4105 let Inst{12-10} = Pg;
4112 multiclass sve_mem_sst_sv_32_scaled<bits<3> opc, string asm,
4113 RegisterOperand listty,
4115 RegisterOperand sxtw_opnd,
4116 RegisterOperand uxtw_opnd > {
4117 def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, listty, uxtw_opnd>;
4118 def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, listty, sxtw_opnd>;
4120 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4121 (!cast<Instruction>(NAME # _UXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
4122 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4123 (!cast<Instruction>(NAME # _SXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
4126 multiclass sve_mem_sst_sv_32_unscaled<bits<3> opc, string asm,
4127 RegisterOperand listty,
4129 RegisterOperand sxtw_opnd,
4130 RegisterOperand uxtw_opnd> {
4131 def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, listty, uxtw_opnd>;
4132 def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, listty, sxtw_opnd>;
4134 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4135 (!cast<Instruction>(NAME # _UXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
4136 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4137 (!cast<Instruction>(NAME # _SXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
4140 class sve_mem_sst_sv2<bits<2> msz, bit scaled, string asm,
4141 RegisterOperand zprext>
4142 : I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
4143 asm, "\t$Zt, $Pg, [$Rn, $Zm]",
4150 let Inst{31-25} = 0b1110010;
4151 let Inst{24-23} = msz;
4153 let Inst{21} = scaled;
4154 let Inst{20-16} = Zm;
4155 let Inst{15-13} = 0b101;
4156 let Inst{12-10} = Pg;
4163 multiclass sve_mem_sst_sv_64_scaled<bits<2> msz, string asm,
4164 RegisterOperand zprext> {
4165 def "" : sve_mem_sst_sv2<msz, 1, asm, zprext>;
4167 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4168 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
4172 multiclass sve_mem_sst_sv_64_unscaled<bits<2> msz, string asm> {
4173 def "" : sve_mem_sst_sv2<msz, 0, asm, ZPR64ExtLSL8>;
4175 def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
4176 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
4179 class sve_mem_sst_vi<bits<3> opc, string asm, ZPRRegOp zprty,
4180 RegisterOperand VecList, Operand imm_ty>
4181 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5),
4182 asm, "\t$Zt, $Pg, [$Zn, $imm5]",
4189 let Inst{31-25} = 0b1110010;
4190 let Inst{24-23} = opc{2-1};
4192 let Inst{21} = opc{0};
4193 let Inst{20-16} = imm5;
4194 let Inst{15-13} = 0b101;
4195 let Inst{12-10} = Pg;
4202 multiclass sve_mem_sst_vi_ptrs<bits<3> opc, string asm, RegisterOperand listty,
4203 ZPRRegOp zprty, Operand imm_ty> {
4204 def _IMM : sve_mem_sst_vi<opc, asm, zprty, listty, imm_ty>;
4206 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4207 (!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 0>;
4208 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
4209 (!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 0>;
4210 def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
4211 (!cast<Instruction>(NAME # _IMM) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 1>;
4214 class sve_mem_z_spill<string asm>
4215 : I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
4216 asm, "\t$Zt, [$Rn, $imm9, mul vl]",
4222 let Inst{31-22} = 0b1110010110;
4223 let Inst{21-16} = imm9{8-3};
4224 let Inst{15-13} = 0b010;
4225 let Inst{12-10} = imm9{2-0};
4232 multiclass sve_mem_z_spill<string asm> {
4233 def NAME : sve_mem_z_spill<asm>;
4235 def : InstAlias<asm # "\t$Zt, [$Rn]",
4236 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
4239 class sve_mem_p_spill<string asm>
4240 : I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
4241 asm, "\t$Pt, [$Rn, $imm9, mul vl]",
4247 let Inst{31-22} = 0b1110010110;
4248 let Inst{21-16} = imm9{8-3};
4249 let Inst{15-13} = 0b000;
4250 let Inst{12-10} = imm9{2-0};
4258 multiclass sve_mem_p_spill<string asm> {
4259 def NAME : sve_mem_p_spill<asm>;
4261 def : InstAlias<asm # "\t$Pt, [$Rn]",
4262 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
4265 //===----------------------------------------------------------------------===//
4266 // SVE Permute - Predicates Group
4267 //===----------------------------------------------------------------------===//
4269 class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
4271 : I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
4272 asm, "\t$Pd, $Pn, $Pm",
4278 let Inst{31-24} = 0b00000101;
4279 let Inst{23-22} = sz8_64;
4280 let Inst{21-20} = 0b10;
4281 let Inst{19-16} = Pm;
4282 let Inst{15-13} = 0b010;
4283 let Inst{12-10} = opc;
4290 multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
4291 def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
4292 def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
4293 def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
4294 def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
4297 class sve_int_perm_punpk<bit opc, string asm>
4298 : I<(outs PPR16:$Pd), (ins PPR8:$Pn),
4304 let Inst{31-17} = 0b000001010011000;
4306 let Inst{15-9} = 0b0100000;
4312 multiclass sve_int_perm_punpk<bit opc, string asm, SDPatternOperator op> {
4313 def NAME : sve_int_perm_punpk<opc, asm>;
4315 def : SVE_1_Op_Pat<nxv8i1, op, nxv16i1, !cast<Instruction>(NAME)>;
4316 def : SVE_1_Op_Pat<nxv4i1, op, nxv8i1, !cast<Instruction>(NAME)>;
4317 def : SVE_1_Op_Pat<nxv2i1, op, nxv4i1, !cast<Instruction>(NAME)>;
4320 class sve_int_rdffr_pred<bit s, string asm>
4321 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg),
4322 asm, "\t$Pd, $Pg/z",
4327 let Inst{31-23} = 0b001001010;
4329 let Inst{21-9} = 0b0110001111000;
4334 let Defs = !if(!eq (s, 1), [NZCV], []);
4338 class sve_int_rdffr_unpred<string asm> : I<
4339 (outs PPR8:$Pd), (ins),
4344 let Inst{31-4} = 0b0010010100011001111100000000;
4350 class sve_int_wrffr<string asm>
4351 : I<(outs), (ins PPR8:$Pn),
4356 let Inst{31-9} = 0b00100101001010001001000;
4358 let Inst{4-0} = 0b00000;
4360 let hasSideEffects = 1;
4364 class sve_int_setffr<string asm>
4369 let Inst{31-0} = 0b00100101001011001001000000000000;
4371 let hasSideEffects = 1;
4375 //===----------------------------------------------------------------------===//
4376 // SVE Permute Vector - Predicated Group
4377 //===----------------------------------------------------------------------===//
4379 class sve_int_perm_clast_rz<bits<2> sz8_64, bit ab, string asm,
4380 ZPRRegOp zprty, RegisterClass rt>
4381 : I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm),
4382 asm, "\t$Rdn, $Pg, $_Rdn, $Zm",
4388 let Inst{31-24} = 0b00000101;
4389 let Inst{23-22} = sz8_64;
4390 let Inst{21-17} = 0b11000;
4392 let Inst{15-13} = 0b101;
4393 let Inst{12-10} = Pg;
4395 let Inst{4-0} = Rdn;
4397 let Constraints = "$Rdn = $_Rdn";
4400 multiclass sve_int_perm_clast_rz<bit ab, string asm> {
4401 def _B : sve_int_perm_clast_rz<0b00, ab, asm, ZPR8, GPR32>;
4402 def _H : sve_int_perm_clast_rz<0b01, ab, asm, ZPR16, GPR32>;
4403 def _S : sve_int_perm_clast_rz<0b10, ab, asm, ZPR32, GPR32>;
4404 def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>;
4407 class sve_int_perm_clast_vz<bits<2> sz8_64, bit ab, string asm,
4408 ZPRRegOp zprty, RegisterClass rt>
4409 : I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm),
4410 asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
4416 let Inst{31-24} = 0b00000101;
4417 let Inst{23-22} = sz8_64;
4418 let Inst{21-17} = 0b10101;
4420 let Inst{15-13} = 0b100;
4421 let Inst{12-10} = Pg;
4423 let Inst{4-0} = Vdn;
4425 let Constraints = "$Vdn = $_Vdn";
4428 multiclass sve_int_perm_clast_vz<bit ab, string asm> {
4429 def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>;
4430 def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>;
4431 def _S : sve_int_perm_clast_vz<0b10, ab, asm, ZPR32, FPR32>;
4432 def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>;
4435 class sve_int_perm_clast_zz<bits<2> sz8_64, bit ab, string asm,
4437 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
4438 asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
4444 let Inst{31-24} = 0b00000101;
4445 let Inst{23-22} = sz8_64;
4446 let Inst{21-17} = 0b10100;
4448 let Inst{15-13} = 0b100;
4449 let Inst{12-10} = Pg;
4451 let Inst{4-0} = Zdn;
4453 let Constraints = "$Zdn = $_Zdn";
4454 let DestructiveInstType = Destructive;
4455 let ElementSize = ElementSizeNone;
4458 multiclass sve_int_perm_clast_zz<bit ab, string asm> {
4459 def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>;
4460 def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>;
4461 def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>;
4462 def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>;
4465 class sve_int_perm_last_r<bits<2> sz8_64, bit ab, string asm,
4466 ZPRRegOp zprty, RegisterClass resultRegType>
4467 : I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn),
4468 asm, "\t$Rd, $Pg, $Zn",
4474 let Inst{31-24} = 0b00000101;
4475 let Inst{23-22} = sz8_64;
4476 let Inst{21-17} = 0b10000;
4478 let Inst{15-13} = 0b101;
4479 let Inst{12-10} = Pg;
4484 multiclass sve_int_perm_last_r<bit ab, string asm> {
4485 def _B : sve_int_perm_last_r<0b00, ab, asm, ZPR8, GPR32>;
4486 def _H : sve_int_perm_last_r<0b01, ab, asm, ZPR16, GPR32>;
4487 def _S : sve_int_perm_last_r<0b10, ab, asm, ZPR32, GPR32>;
4488 def _D : sve_int_perm_last_r<0b11, ab, asm, ZPR64, GPR64>;
4491 class sve_int_perm_last_v<bits<2> sz8_64, bit ab, string asm,
4492 ZPRRegOp zprty, RegisterClass dstRegtype>
4493 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
4494 asm, "\t$Vd, $Pg, $Zn",
4500 let Inst{31-24} = 0b00000101;
4501 let Inst{23-22} = sz8_64;
4502 let Inst{21-17} = 0b10001;
4504 let Inst{15-13} = 0b100;
4505 let Inst{12-10} = Pg;
4510 multiclass sve_int_perm_last_v<bit ab, string asm> {
4511 def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>;
4512 def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>;
4513 def _S : sve_int_perm_last_v<0b10, ab, asm, ZPR32, FPR32>;
4514 def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>;
4517 class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty>
4518 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
4519 asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
4525 let Inst{31-24} = 0b00000101;
4526 let Inst{23-22} = sz8_64;
4527 let Inst{21-13} = 0b101100100;
4528 let Inst{12-10} = Pg;
4530 let Inst{4-0} = Zdn;
4532 let Constraints = "$Zdn = $_Zdn";
4533 let DestructiveInstType = Destructive;
4534 let ElementSize = ElementSizeNone;
4537 multiclass sve_int_perm_splice<string asm> {
4538 def _B : sve_int_perm_splice<0b00, asm, ZPR8>;
4539 def _H : sve_int_perm_splice<0b01, asm, ZPR16>;
4540 def _S : sve_int_perm_splice<0b10, asm, ZPR32>;
4541 def _D : sve_int_perm_splice<0b11, asm, ZPR64>;
4544 class sve2_int_perm_splice_cons<bits<2> sz8_64, string asm,
4545 ZPRRegOp zprty, RegisterOperand VecList>
4546 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, VecList:$Zn),
4547 asm, "\t$Zd, $Pg, $Zn",
4553 let Inst{31-24} = 0b00000101;
4554 let Inst{23-22} = sz8_64;
4555 let Inst{21-13} = 0b101101100;
4556 let Inst{12-10} = Pg;
4561 multiclass sve2_int_perm_splice_cons<string asm> {
4562 def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8, ZZ_b>;
4563 def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>;
4564 def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>;
4565 def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>;
4568 class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm,
4570 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
4571 asm, "\t$Zd, $Pg/m, $Zn",
4577 let Inst{31-24} = 0b00000101;
4578 let Inst{23-22} = sz8_64;
4579 let Inst{21-18} = 0b1001;
4580 let Inst{17-16} = opc;
4581 let Inst{15-13} = 0b100;
4582 let Inst{12-10} = Pg;
4586 let Constraints = "$Zd = $_Zd";
4587 let DestructiveInstType = Destructive;
4588 let ElementSize = zprty.ElementSize;
4591 multiclass sve_int_perm_rev_rbit<string asm> {
4592 def _B : sve_int_perm_rev<0b00, 0b11, asm, ZPR8>;
4593 def _H : sve_int_perm_rev<0b01, 0b11, asm, ZPR16>;
4594 def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>;
4595 def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>;
4598 multiclass sve_int_perm_rev_revb<string asm> {
4599 def _H : sve_int_perm_rev<0b01, 0b00, asm, ZPR16>;
4600 def _S : sve_int_perm_rev<0b10, 0b00, asm, ZPR32>;
4601 def _D : sve_int_perm_rev<0b11, 0b00, asm, ZPR64>;
4604 multiclass sve_int_perm_rev_revh<string asm> {
4605 def _S : sve_int_perm_rev<0b10, 0b01, asm, ZPR32>;
4606 def _D : sve_int_perm_rev<0b11, 0b01, asm, ZPR64>;
4609 multiclass sve_int_perm_rev_revw<string asm> {
4610 def _D : sve_int_perm_rev<0b11, 0b10, asm, ZPR64>;
4613 class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
4614 RegisterClass srcRegType>
4615 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
4616 asm, "\t$Zd, $Pg/m, $Rn",
4622 let Inst{31-24} = 0b00000101;
4623 let Inst{23-22} = sz8_64;
4624 let Inst{21-13} = 0b101000101;
4625 let Inst{12-10} = Pg;
4629 let Constraints = "$Zd = $_Zd";
4630 let DestructiveInstType = Destructive;
4631 let ElementSize = zprty.ElementSize;
4634 multiclass sve_int_perm_cpy_r<string asm> {
4635 def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>;
4636 def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>;
4637 def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>;
4638 def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>;
4640 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
4641 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
4642 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
4643 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
4644 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
4645 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
4646 def : InstAlias<"mov $Zd, $Pg/m, $Rn",
4647 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>;
4650 class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty,
4651 RegisterClass srcRegtype>
4652 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
4653 asm, "\t$Zd, $Pg/m, $Vn",
4659 let Inst{31-24} = 0b00000101;
4660 let Inst{23-22} = sz8_64;
4661 let Inst{21-13} = 0b100000100;
4662 let Inst{12-10} = Pg;
4666 let Constraints = "$Zd = $_Zd";
4667 let DestructiveInstType = Destructive;
4668 let ElementSize = zprty.ElementSize;
4671 multiclass sve_int_perm_cpy_v<string asm> {
4672 def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
4673 def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>;
4674 def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>;
4675 def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
4677 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
4678 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
4679 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
4680 (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
4681 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
4682 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
4683 def : InstAlias<"mov $Zd, $Pg/m, $Vn",
4684 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
4687 class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
4688 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
4689 asm, "\t$Zd, $Pg, $Zn",
4695 let Inst{31-23} = 0b000001011;
4697 let Inst{21-13} = 0b100001100;
4698 let Inst{12-10} = Pg;
4703 multiclass sve_int_perm_compact<string asm> {
4704 def _S : sve_int_perm_compact<0b0, asm, ZPR32>;
4705 def _D : sve_int_perm_compact<0b1, asm, ZPR64>;
4709 //===----------------------------------------------------------------------===//
4710 // SVE Memory - Contiguous Load Group
4711 //===----------------------------------------------------------------------===//
4713 class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
4714 RegisterOperand VecList>
4715 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
4716 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
4723 let Inst{31-25} = 0b1010010;
4724 let Inst{24-21} = dtype;
4726 let Inst{19-16} = imm4;
4727 let Inst{15-13} = 0b101;
4728 let Inst{12-10} = Pg;
4733 let Uses = !if(!eq(nf, 1), [FFR], []);
4734 let Defs = !if(!eq(nf, 1), [FFR], []);
4737 multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
4738 RegisterOperand listty, ZPRRegOp zprty> {
4739 def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>;
4741 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4742 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
4743 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
4744 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
4745 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4746 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4749 multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
4751 : sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
4753 class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList>
4754 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
4755 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
4762 let Inst{31-25} = 0b1010010;
4763 let Inst{24-23} = msz;
4764 let Inst{22-20} = 0b000;
4765 let Inst{19-16} = imm4;
4766 let Inst{15-13} = 0b111;
4767 let Inst{12-10} = Pg;
4774 multiclass sve_mem_cldnt_si<bits<2> msz, string asm, RegisterOperand listty,
4776 def NAME : sve_mem_cldnt_si_base<msz, asm, listty>;
4778 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4779 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
4780 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
4781 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
4782 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4783 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4786 class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList,
4787 RegisterOperand gprty>
4788 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4789 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
4796 let Inst{31-25} = 0b1010010;
4797 let Inst{24-23} = msz;
4798 let Inst{22-21} = 0b00;
4799 let Inst{20-16} = Rm;
4800 let Inst{15-13} = 0b110;
4801 let Inst{12-10} = Pg;
4808 multiclass sve_mem_cldnt_ss<bits<2> msz, string asm, RegisterOperand listty,
4809 ZPRRegOp zprty, RegisterOperand gprty> {
4810 def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>;
4812 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
4813 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
4816 class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList>
4817 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
4818 asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
4823 let Inst{31-25} = 0b1010010;
4824 let Inst{24-23} = sz;
4825 let Inst{22-20} = 0;
4826 let Inst{19-16} = imm4;
4827 let Inst{15-13} = 0b001;
4828 let Inst{12-10} = Pg;
4835 multiclass sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand listty,
4837 def NAME : sve_mem_ldqr_si<sz, asm, listty>;
4838 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4839 (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4840 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4841 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
4842 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]",
4843 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>;
4846 class sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand VecList,
4847 RegisterOperand gprty>
4848 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4849 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> {
4854 let Inst{31-25} = 0b1010010;
4855 let Inst{24-23} = sz;
4856 let Inst{22-21} = 0;
4857 let Inst{20-16} = Rm;
4858 let Inst{15-13} = 0;
4859 let Inst{12-10} = Pg;
4866 multiclass sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand listty,
4867 ZPRRegOp zprty, RegisterOperand gprty> {
4868 def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>;
4870 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
4871 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
4874 class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
4875 RegisterOperand VecList, Operand immtype>
4876 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
4877 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
4884 let Inst{31-25} = 0b1000010;
4885 let Inst{24-23} = dtypeh;
4887 let Inst{21-16} = imm6;
4889 let Inst{14-13} = dtypel;
4890 let Inst{12-10} = Pg;
4897 multiclass sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
4898 RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> {
4899 def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>;
4901 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4902 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
4903 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]",
4904 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
4905 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4906 (!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4909 class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
4910 RegisterOperand VecList>
4911 : I<(outs VecList:$Zt), iops,
4912 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
4919 let Inst{31-25} = 0b1010010;
4920 let Inst{24-21} = dtype;
4921 let Inst{20-16} = Rm;
4922 let Inst{15-14} = 0b01;
4924 let Inst{12-10} = Pg;
4929 let Uses = !if(!eq(ff, 1), [FFR], []);
4930 let Defs = !if(!eq(ff, 1), [FFR], []);
4933 multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
4934 ZPRRegOp zprty, RegisterOperand gprty> {
4935 def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4938 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
4939 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
4942 multiclass sve_mem_cldff_ss<bits<4> dtype, string asm, RegisterOperand listty,
4943 ZPRRegOp zprty, RegisterOperand gprty> {
4944 def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4947 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
4948 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
4950 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4951 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
4953 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4954 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
4957 multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty,
4959 : sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>;
4961 class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
4962 string asm, Operand immtype>
4963 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
4964 asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
4971 let Inst{31-25} = 0b1010010;
4972 let Inst{24-23} = sz;
4973 let Inst{22-21} = nregs;
4975 let Inst{19-16} = imm4;
4976 let Inst{15-13} = 0b111;
4977 let Inst{12-10} = Pg;
4984 multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
4985 string asm, Operand immtype> {
4986 def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>;
4988 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
4989 (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
4992 class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
4993 string asm, RegisterOperand gprty>
4994 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
4995 asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
5002 let Inst{31-25} = 0b1010010;
5003 let Inst{24-23} = sz;
5004 let Inst{22-21} = nregs;
5005 let Inst{20-16} = Rm;
5006 let Inst{15-13} = 0b110;
5007 let Inst{12-10} = Pg;
5014 //===----------------------------------------------------------------------===//
5015 // SVE Memory - 32-bit Gather and Unsized Contiguous Group
5016 //===----------------------------------------------------------------------===//
5018 // bit xs is '1' if offsets are signed
5019 // bit scaled is '1' if the offsets are scaled
5020 class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm,
5021 RegisterOperand zprext>
5022 : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
5023 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
5030 let Inst{31-25} = 0b1000010;
5031 let Inst{24-23} = opc{3-2};
5033 let Inst{21} = scaled;
5034 let Inst{20-16} = Zm;
5036 let Inst{14-13} = opc{1-0};
5037 let Inst{12-10} = Pg;
5042 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
5043 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
5046 multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm,
5047 RegisterOperand sxtw_opnd,
5048 RegisterOperand uxtw_opnd> {
5049 def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>;
5050 def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>;
5052 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5053 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
5054 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5055 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
5058 multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
5059 RegisterOperand sxtw_opnd,
5060 RegisterOperand uxtw_opnd> {
5061 def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>;
5062 def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>;
5064 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5065 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
5066 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5067 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
5071 class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
5072 : I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
5073 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
5080 let Inst{31-25} = 0b1000010;
5081 let Inst{24-23} = opc{3-2};
5082 let Inst{22-21} = 0b01;
5083 let Inst{20-16} = imm5;
5085 let Inst{14-13} = opc{1-0};
5086 let Inst{12-10} = Pg;
5091 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
5092 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
5095 multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> {
5096 def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
5098 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5099 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
5100 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
5101 (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
5102 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5103 (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
5106 class sve_mem_prfm_si<bits<2> msz, string asm>
5107 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6),
5108 asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]",
5115 let Inst{31-22} = 0b1000010111;
5116 let Inst{21-16} = imm6;
5118 let Inst{14-13} = msz;
5119 let Inst{12-10} = Pg;
5122 let Inst{3-0} = prfop;
5124 let hasSideEffects = 1;
5127 multiclass sve_mem_prfm_si<bits<2> msz, string asm> {
5128 def NAME : sve_mem_prfm_si<msz, asm>;
5130 def : InstAlias<asm # "\t$prfop, $Pg, [$Rn]",
5131 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
5134 class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty>
5135 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
5136 asm, "\t$prfop, $Pg, [$Rn, $Rm]",
5143 let Inst{31-25} = 0b1000010;
5144 let Inst{24-23} = opc{2-1};
5145 let Inst{22-21} = 0b00;
5146 let Inst{20-16} = Rm;
5148 let Inst{14} = opc{0};
5150 let Inst{12-10} = Pg;
5153 let Inst{3-0} = prfop;
5155 let hasSideEffects = 1;
5158 class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm,
5159 RegisterOperand zprext>
5160 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
5161 asm, "\t$prfop, $Pg, [$Rn, $Zm]",
5168 let Inst{31-23} = 0b100001000;
5171 let Inst{20-16} = Zm;
5173 let Inst{14-13} = msz;
5174 let Inst{12-10} = Pg;
5177 let Inst{3-0} = prfop;
5179 let hasSideEffects = 1;
5182 multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm,
5183 RegisterOperand sxtw_opnd,
5184 RegisterOperand uxtw_opnd> {
5185 def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>;
5186 def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
5189 class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
5190 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
5191 asm, "\t$prfop, $Pg, [$Zn, $imm5]",
5198 let Inst{31-25} = 0b1000010;
5199 let Inst{24-23} = msz;
5200 let Inst{22-21} = 0b00;
5201 let Inst{20-16} = imm5;
5202 let Inst{15-13} = 0b111;
5203 let Inst{12-10} = Pg;
5206 let Inst{3-0} = prfop;
5209 multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
5210 def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>;
5212 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
5213 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
5216 class sve_mem_z_fill<string asm>
5217 : I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9),
5218 asm, "\t$Zt, [$Rn, $imm9, mul vl]",
5224 let Inst{31-22} = 0b1000010110;
5225 let Inst{21-16} = imm9{8-3};
5226 let Inst{15-13} = 0b010;
5227 let Inst{12-10} = imm9{2-0};
5234 multiclass sve_mem_z_fill<string asm> {
5235 def NAME : sve_mem_z_fill<asm>;
5237 def : InstAlias<asm # "\t$Zt, [$Rn]",
5238 (!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
5241 class sve_mem_p_fill<string asm>
5242 : I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
5243 asm, "\t$Pt, [$Rn, $imm9, mul vl]",
5249 let Inst{31-22} = 0b1000010110;
5250 let Inst{21-16} = imm9{8-3};
5251 let Inst{15-13} = 0b000;
5252 let Inst{12-10} = imm9{2-0};
5260 multiclass sve_mem_p_fill<string asm> {
5261 def NAME : sve_mem_p_fill<asm>;
5263 def : InstAlias<asm # "\t$Pt, [$Rn]",
5264 (!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
5267 class sve2_mem_gldnt_vs_base<bits<5> opc, dag iops, string asm,
5268 RegisterOperand VecList>
5269 : I<(outs VecList:$Zt), iops,
5270 asm, "\t$Zt, $Pg/z, [$Zn, $Rm]",
5278 let Inst{30} = opc{4};
5279 let Inst{29-25} = 0b00010;
5280 let Inst{24-23} = opc{3-2};
5281 let Inst{22-21} = 0b00;
5282 let Inst{20-16} = Rm;
5284 let Inst{14-13} = opc{1-0};
5285 let Inst{12-10} = Pg;
5292 multiclass sve2_mem_gldnt_vs<bits<5> opc, string asm,
5293 RegisterOperand listty, ZPRRegOp zprty> {
5294 def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
5297 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
5298 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
5299 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5300 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
5301 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5302 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
5305 //===----------------------------------------------------------------------===//
5306 // SVE Memory - 64-bit Gather Group
5307 //===----------------------------------------------------------------------===//
5309 // bit xs is '1' if offsets are signed
5310 // bit scaled is '1' if the offsets are scaled
5311 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
5312 class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm,
5313 RegisterOperand zprext>
5314 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
5315 asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
5322 let Inst{31-25} = 0b1100010;
5323 let Inst{24-23} = opc{3-2};
5325 let Inst{21} = scaled;
5326 let Inst{20-16} = Zm;
5328 let Inst{14-13} = opc{1-0};
5329 let Inst{12-10} = Pg;
5334 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
5335 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
5338 multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm,
5339 RegisterOperand sxtw_opnd,
5340 RegisterOperand uxtw_opnd> {
5341 def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>;
5342 def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>;
5344 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5345 (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
5346 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5347 (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
5350 multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
5351 RegisterOperand sxtw_opnd,
5352 RegisterOperand uxtw_opnd> {
5353 def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>;
5354 def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>;
5356 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5357 (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
5358 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5359 (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
5362 multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm,
5363 RegisterOperand zprext> {
5364 def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>;
5366 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5367 (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
5370 multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> {
5371 def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>;
5373 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
5374 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
5377 class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
5378 : I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
5379 asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
5386 let Inst{31-25} = 0b1100010;
5387 let Inst{24-23} = opc{3-2};
5388 let Inst{22-21} = 0b01;
5389 let Inst{20-16} = imm5;
5391 let Inst{14-13} = opc{1-0};
5392 let Inst{12-10} = Pg;
5397 let Defs = !if(!eq(opc{0}, 1), [FFR], []);
5398 let Uses = !if(!eq(opc{0}, 1), [FFR], []);
5401 multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
5402 def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
5404 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5405 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
5406 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
5407 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
5408 def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
5409 (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
5412 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
5413 class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm,
5414 RegisterOperand zprext>
5415 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
5416 asm, "\t$prfop, $Pg, [$Rn, $Zm]",
5423 let Inst{31-23} = 0b110001000;
5426 let Inst{20-16} = Zm;
5428 let Inst{14-13} = msz;
5429 let Inst{12-10} = Pg;
5432 let Inst{3-0} = prfop;
5434 let hasSideEffects = 1;
5437 multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm,
5438 RegisterOperand sxtw_opnd,
5439 RegisterOperand uxtw_opnd> {
5440 def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>;
5441 def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>;
5444 multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm,
5445 RegisterOperand zprext> {
5446 def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>;
5450 class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
5451 : I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
5452 asm, "\t$prfop, $Pg, [$Zn, $imm5]",
5459 let Inst{31-25} = 0b1100010;
5460 let Inst{24-23} = msz;
5461 let Inst{22-21} = 0b00;
5462 let Inst{20-16} = imm5;
5463 let Inst{15-13} = 0b111;
5464 let Inst{12-10} = Pg;
5467 let Inst{3-0} = prfop;
5469 let hasSideEffects = 1;
5472 multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
5473 def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>;
5475 def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
5476 (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
5480 //===----------------------------------------------------------------------===//
5481 // SVE Compute Vector Address Group
5482 //===----------------------------------------------------------------------===//
5484 class sve_int_bin_cons_misc_0_a<bits<2> opc, bits<2> msz, string asm,
5485 ZPRRegOp zprty, RegisterOperand zprext>
5486 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm),
5487 asm, "\t$Zd, [$Zn, $Zm]",
5493 let Inst{31-24} = 0b00000100;
5494 let Inst{23-22} = opc;
5496 let Inst{20-16} = Zm;
5497 let Inst{15-12} = 0b1010;
5498 let Inst{11-10} = msz;
5503 multiclass sve_int_bin_cons_misc_0_a_uxtw<bits<2> opc, string asm> {
5504 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtUXTW8>;
5505 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtUXTW16>;
5506 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtUXTW32>;
5507 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtUXTW64>;
5510 multiclass sve_int_bin_cons_misc_0_a_sxtw<bits<2> opc, string asm> {
5511 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtSXTW8>;
5512 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtSXTW16>;
5513 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtSXTW32>;
5514 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtSXTW64>;
5517 multiclass sve_int_bin_cons_misc_0_a_32_lsl<bits<2> opc, string asm> {
5518 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR32, ZPR32ExtLSL8>;
5519 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR32, ZPR32ExtLSL16>;
5520 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR32, ZPR32ExtLSL32>;
5521 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR32, ZPR32ExtLSL64>;
5524 multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> {
5525 def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtLSL8>;
5526 def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtLSL16>;
5527 def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>;
5528 def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>;
5532 //===----------------------------------------------------------------------===//
5533 // SVE Integer Misc - Unpredicated Group
5534 //===----------------------------------------------------------------------===//
5536 class sve_int_bin_cons_misc_0_b<bits<2> sz, string asm, ZPRRegOp zprty>
5537 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
5538 asm, "\t$Zd, $Zn, $Zm",
5544 let Inst{31-24} = 0b00000100;
5545 let Inst{23-22} = sz;
5547 let Inst{20-16} = Zm;
5548 let Inst{15-10} = 0b101100;
5553 multiclass sve_int_bin_cons_misc_0_b<string asm> {
5554 def _H : sve_int_bin_cons_misc_0_b<0b01, asm, ZPR16>;
5555 def _S : sve_int_bin_cons_misc_0_b<0b10, asm, ZPR32>;
5556 def _D : sve_int_bin_cons_misc_0_b<0b11, asm, ZPR64>;
5559 class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty>
5560 : I<(outs zprty:$Zd), (ins zprty:$Zn),
5566 let Inst{31-24} = 0b00000100;
5567 let Inst{23-22} = opc{7-6};
5569 let Inst{20-16} = opc{5-1};
5570 let Inst{15-11} = 0b10111;
5571 let Inst{10} = opc{0};
5576 //===----------------------------------------------------------------------===//
5577 // SVE Integer Reduction Group
5578 //===----------------------------------------------------------------------===//
5580 class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm,
5581 ZPRRegOp zprty, RegisterClass regtype>
5582 : I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
5583 asm, "\t$Vd, $Pg, $Zn",
5589 let Inst{31-24} = 0b00000100;
5590 let Inst{23-22} = sz8_32;
5592 let Inst{20-19} = fmt;
5593 let Inst{18-16} = opc;
5594 let Inst{15-13} = 0b001;
5595 let Inst{12-10} = Pg;
5600 multiclass sve_int_reduce_0_saddv<bits<3> opc, string asm> {
5601 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
5602 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
5603 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
5606 multiclass sve_int_reduce_0_uaddv<bits<3> opc, string asm> {
5607 def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
5608 def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
5609 def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
5610 def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>;
5613 multiclass sve_int_reduce_1<bits<3> opc, string asm> {
5614 def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>;
5615 def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>;
5616 def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>;
5617 def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>;
5620 multiclass sve_int_reduce_2<bits<3> opc, string asm> {
5621 def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>;
5622 def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>;
5623 def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>;
5624 def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>;
5627 class sve_int_movprfx_pred<bits<2> sz8_32, bits<3> opc, string asm,
5628 ZPRRegOp zprty, string pg_suffix, dag iops>
5629 : I<(outs zprty:$Zd), iops,
5630 asm, "\t$Zd, $Pg"#pg_suffix#", $Zn",
5636 let Inst{31-24} = 0b00000100;
5637 let Inst{23-22} = sz8_32;
5638 let Inst{21-19} = 0b010;
5639 let Inst{18-16} = opc;
5640 let Inst{15-13} = 0b001;
5641 let Inst{12-10} = Pg;
5645 let ElementSize = zprty.ElementSize;
5648 multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> {
5649 let Constraints = "$Zd = $_Zd" in {
5650 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m",
5651 (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>;
5652 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m",
5653 (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>;
5654 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m",
5655 (ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>;
5656 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m",
5657 (ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>;
5661 multiclass sve_int_movprfx_pred_zero<bits<3> opc, string asm> {
5662 def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z",
5663 (ins PPR3bAny:$Pg, ZPR8:$Zn)>;
5664 def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z",
5665 (ins PPR3bAny:$Pg, ZPR16:$Zn)>;
5666 def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z",
5667 (ins PPR3bAny:$Pg, ZPR32:$Zn)>;
5668 def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z",
5669 (ins PPR3bAny:$Pg, ZPR64:$Zn)>;
5672 //===----------------------------------------------------------------------===//
5673 // SVE Propagate Break Group
5674 //===----------------------------------------------------------------------===//
5676 class sve_int_brkp<bits<2> opc, string asm>
5677 : I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
5678 asm, "\t$Pd, $Pg/z, $Pn, $Pm",
5685 let Inst{31-24} = 0b00100101;
5687 let Inst{22} = opc{1};
5688 let Inst{21-20} = 0b00;
5689 let Inst{19-16} = Pm;
5690 let Inst{15-14} = 0b11;
5691 let Inst{13-10} = Pg;
5694 let Inst{4} = opc{0};
5697 let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
5701 //===----------------------------------------------------------------------===//
5702 // SVE Partition Break Group
5703 //===----------------------------------------------------------------------===//
5705 class sve_int_brkn<bit S, string asm>
5706 : I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm),
5707 asm, "\t$Pdm, $Pg/z, $Pn, $_Pdm",
5713 let Inst{31-23} = 0b001001010;
5715 let Inst{21-14} = 0b01100001;
5716 let Inst{13-10} = Pg;
5720 let Inst{3-0} = Pdm;
5722 let Constraints = "$Pdm = $_Pdm";
5723 let Defs = !if(!eq (S, 0b1), [NZCV], []);
5726 class sve_int_break<bits<3> opc, string asm, string suffix, dag iops>
5727 : I<(outs PPR8:$Pd), iops,
5728 asm, "\t$Pd, $Pg"#suffix#", $Pn",
5734 let Inst{31-24} = 0b00100101;
5735 let Inst{23-22} = opc{2-1};
5736 let Inst{21-14} = 0b01000001;
5737 let Inst{13-10} = Pg;
5740 let Inst{4} = opc{0};
5743 let Constraints = !if(!eq (opc{0}, 1), "$Pd = $_Pd", "");
5744 let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
5748 multiclass sve_int_break_m<bits<3> opc, string asm> {
5749 def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>;
5752 multiclass sve_int_break_z<bits<3> opc, string asm> {
5753 def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>;
5756 //===----------------------------------------------------------------------===//
5757 // SVE2 String Processing Group
5758 //===----------------------------------------------------------------------===//
5760 class sve2_char_match<bit sz, bit opc, string asm,
5761 PPRRegOp pprty, ZPRRegOp zprty>
5762 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
5763 asm, "\t$Pd, $Pg/z, $Zn, $Zm",
5770 let Inst{31-23} = 0b010001010;
5773 let Inst{20-16} = Zm;
5774 let Inst{15-13} = 0b100;
5775 let Inst{12-10} = Pg;
5783 multiclass sve2_char_match<bit opc, string asm> {
5784 def _B : sve2_char_match<0b0, opc, asm, PPR8, ZPR8>;
5785 def _H : sve2_char_match<0b1, opc, asm, PPR16, ZPR16>;
5788 //===----------------------------------------------------------------------===//
5789 // SVE2 Histogram Computation - Segment Group
5790 //===----------------------------------------------------------------------===//
5792 class sve2_hist_gen_segment<string asm>
5793 : I<(outs ZPR8:$Zd), (ins ZPR8:$Zn, ZPR8:$Zm),
5794 asm, "\t$Zd, $Zn, $Zm",
5800 let Inst{31-21} = 0b01000101001;
5801 let Inst{20-16} = Zm;
5802 let Inst{15-10} = 0b101000;
5807 //===----------------------------------------------------------------------===//
5808 // SVE2 Histogram Computation - Vector Group
5809 //===----------------------------------------------------------------------===//
5811 class sve2_hist_gen_vector<bit sz, string asm, ZPRRegOp zprty>
5812 : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
5813 asm, "\t$Zd, $Pg/z, $Zn, $Zm",
5820 let Inst{31-23} = 0b010001011;
5823 let Inst{20-16} = Zm;
5824 let Inst{15-13} = 0b110;
5825 let Inst{12-10} = Pg;
5830 multiclass sve2_hist_gen_vector<string asm> {
5831 def _S : sve2_hist_gen_vector<0b0, asm, ZPR32>;
5832 def _D : sve2_hist_gen_vector<0b1, asm, ZPR64>;
5835 //===----------------------------------------------------------------------===//
5836 // SVE2 Crypto Extensions Group
5837 //===----------------------------------------------------------------------===//
5839 class sve2_crypto_cons_bin_op<bit opc, string asm, ZPRRegOp zprty>
5840 : I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
5841 asm, "\t$Zd, $Zn, $Zm",
5847 let Inst{31-21} = 0b01000101001;
5848 let Inst{20-16} = Zm;
5849 let Inst{15-11} = 0b11110;
5855 class sve2_crypto_des_bin_op<bits<2> opc, string asm, ZPRRegOp zprty>
5856 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm),
5857 asm, "\t$Zdn, $_Zdn, $Zm",
5862 let Inst{31-17} = 0b010001010010001;
5863 let Inst{16} = opc{1};
5864 let Inst{15-11} = 0b11100;
5865 let Inst{10} = opc{0};
5867 let Inst{4-0} = Zdn;
5869 let Constraints = "$Zdn = $_Zdn";
5872 class sve2_crypto_unary_op<bit opc, string asm>
5873 : I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn),
5874 asm, "\t$Zdn, $_Zdn",
5878 let Inst{31-11} = 0b010001010010000011100;
5880 let Inst{9-5} = 0b00000;
5881 let Inst{4-0} = Zdn;
5883 let Constraints = "$Zdn = $_Zdn";