lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // ARM Subtarget state.
  20 //
  21
  22 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  23                                              "true", "Thumb mode">;
  24
  25 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  26                                              "true", "Use software floating "
  27                                              "point features.">;
  28
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget features.
  32 //
  33
  34 // Floating Point, HW Division and Neon Support
  35
  36 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
  37 // version).
  38 def FeatureFPRegs         : SubtargetFeature<"fpregs", "HasFPRegs", "true",
  39                                              "Enable FP registers">;
  40
  41 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
  42 // extension) and MVE (even in the integer-only version).
  43 def FeatureFPRegs16       : SubtargetFeature<"fpregs16", "HasFPRegs16", "true",
  44                                              "Enable 16-bit FP registers",
  45                                              [FeatureFPRegs]>;
  46
  47 def FeatureFPRegs64       : SubtargetFeature<"fpregs64", "HasFPRegs64", "true",
  48                                              "Enable 64-bit FP registers",
  49                                              [FeatureFPRegs]>;
  50
  51 def FeatureFP64           : SubtargetFeature<"fp64", "HasFP64", "true",
  52                                              "Floating point unit supports "
  53                                              "double precision",
  54                                              [FeatureFPRegs64]>;
  55
  56 def FeatureD32            : SubtargetFeature<"d32", "HasD32", "true",
  57                                              "Extend FP to 32 double registers">;
  58
  59 multiclass VFPver<string name, string query, string description,
  60                   list<SubtargetFeature> prev,
  61                   list<SubtargetFeature> otherimplies,
  62                   list<SubtargetFeature> vfp2prev = []> {
  63   def _D16_SP: SubtargetFeature<
  64     name#"d16sp", query#"D16SP", "true",
  65     description#" with only 16 d-registers and no double precision",
  66     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16_SP")) #
  67       !foreach(v, vfp2prev, !cast<SubtargetFeature>(v # "_SP")) #
  68       otherimplies>;
  69   def _SP: SubtargetFeature<
  70     name#"sp", query#"SP", "true",
  71     description#" with no double precision",
  72     !foreach(v, prev, !cast<SubtargetFeature>(v # "_SP")) #
  73       otherimplies # [FeatureD32, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  74   def _D16: SubtargetFeature<
  75     name#"d16", query#"D16", "true",
  76     description#" with only 16 d-registers",
  77     !foreach(v, prev, !cast<SubtargetFeature>(v # "_D16")) #
  78       vfp2prev #
  79       otherimplies # [FeatureFP64, !cast<SubtargetFeature>(NAME # "_D16_SP")]>;
  80   def "": SubtargetFeature<
  81     name, query, "true", description,
  82     prev # otherimplies # [
  83         !cast<SubtargetFeature>(NAME # "_D16"),
  84         !cast<SubtargetFeature>(NAME # "_SP")]>;
  85 }
  86
  87 def FeatureVFP2_SP        : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
  88                                              "Enable VFP2 instructions with "
  89                                              "no double precision",
  90                                              [FeatureFPRegs]>;
  91
  92 def FeatureVFP2           : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  93                                              "Enable VFP2 instructions",
  94                                              [FeatureFP64, FeatureVFP2_SP]>;
  95
  96 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
  97                          [], [], [FeatureVFP2]>;
  98
  99 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
 100                                              "Enable NEON instructions",
 101                                              [FeatureVFP3]>;
 102
 103 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
 104                                              "Enable half-precision "
 105                                              "floating point">;
 106
 107 defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions",
 108                          [FeatureVFP3], [FeatureFP16]>;
 109
 110 defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
 111                          [FeatureVFP4], []>;
 112
 113 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
 114                                              "Enable full half-precision "
 115                                              "floating point",
 116                                              [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>;
 117
 118 def FeatureFP16FML        : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
 119                                              "Enable full half-precision "
 120                                              "floating point fml instructions",
 121                                              [FeatureFullFP16]>;
 122
 123 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
 124                                              "HasHardwareDivideInThumb", "true",
 125                                              "Enable divide instructions in Thumb">;
 126
 127 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
 128                                              "HasHardwareDivideInARM", "true",
 129                                              "Enable divide instructions in ARM mode">;
 130
 131 // Atomic Support
 132 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
 133                                              "Has data barrier (dmb/dsb) instructions">;
 134
 135 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
 136                                              "Has v7 clrex instruction">;
 137
 138 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
 139                                    "Has full data barrier (dfb) instruction">;
 140
 141 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
 142                                              "HasAcquireRelease", "true",
 143                                              "Has v8 acquire/release (lda/ldaex "
 144                                              " etc) instructions">;
 145
 146
 147 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
 148                                              "FP compare + branch is slow">;
 149
 150 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
 151                                              "Enable support for Performance "
 152                                              "Monitor extensions">;
 153
 154
 155 // TrustZone Security Extensions
 156 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 157                                              "Enable support for TrustZone "
 158                                              "security extensions">;
 159
 160 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 161                                              "Enable support for ARMv8-M "
 162                                              "Security Extensions">;
 163
 164 def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
 165                                              "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 166
 167 def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
 168                                              "Enable AES support", [FeatureNEON]>;
 169
 170 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 171                                              "Enable support for "
 172                                              "Cryptography extensions",
 173                                              [FeatureNEON, FeatureSHA2, FeatureAES]>;
 174
 175 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 176                                              "Enable support for CRC instructions">;
 177
 178 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 179                                              "Enable support for dot product instructions",
 180                                              [FeatureNEON]>;
 181
 182 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 183 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 184                                              "Enable Reliability, Availability "
 185                                              "and Serviceability extensions">;
 186
 187 // Fast computation of non-negative address offsets
 188 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 189                                              "Enable fast computation of "
 190                                              "positive address offsets">;
 191
 192 // Fast execution of AES crypto operations
 193 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 194                                              "CPU fuses AES crypto operations">;
 195
 196 // Fast execution of bottom and top halves of literal generation
 197 def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
 198                                              "CPU fuses literal generation operations">;
 199
 200 // The way of reading thread pointer
 201 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 202                                       "Reading thread pointer from register">;
 203
 204 // Cyclone can zero VFP registers in 0 cycles.
 205 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 206                                              "Has zero-cycle zeroing instructions">;
 207
 208 // Whether it is profitable to unpredicate certain instructions during if-conversion
 209 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 210                                               "IsProfitableToUnpredicate", "true",
 211                                               "Is profitable to unpredicate">;
 212
 213 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 214 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 215                                              "HasSlowVGETLNi32", "true",
 216                                              "Has slow VGETLNi32 - prefer VMOV">;
 217
 218 // Some targets (e.g. Swift) have microcoded VDUP32.
 219 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 220                                              "true",
 221                                              "Has slow VDUP32 - prefer VMOV">;
 222
 223 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 224 // for scalar FP, as this allows more effective execution domain optimization.
 225 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 226                                              "true", "Prefer VMOVSR">;
 227
 228 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 229 // than ISH
 230 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 231                                                "true", "Prefer ISHST barriers">;
 232
 233 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 234 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 235                                              "true",
 236                                              "Has muxed AGU and NEON/FPU">;
 237
 238 // Whether VLDM/VSTM starting with odd register number need more microops
 239 // than single VLDRS
 240 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 241                                               "true", "VLDM/VSTM starting "
 242                                               "with an odd register is slow">;
 243
 244 // Some targets have a renaming dependency when loading into D subregisters.
 245 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 246                                               "SlowLoadDSubregister", "true",
 247                                               "Loading into D subregs is slow">;
 248
 249 def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp",
 250                                                "UseWideStrideVFP", "true",
 251                                                "Use a wide stride when allocating VFP registers">;
 252
 253 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 254 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 255                                              "DontWidenVMOVS", "true",
 256                                              "Don't widen VMOVS to VMOVD">;
 257
 258 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
 259 // VFP register widths.
 260 def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
 261                                              "SplatVFPToNeon", "true",
 262                                              "Splat register from VFP to NEON",
 263                                              [FeatureDontWidenVMOVS]>;
 264
 265 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 266 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 267                                              "ExpandMLx", "true",
 268                                              "Expand VFP/NEON MLA/MLS instructions">;
 269
 270 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 271 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 272                                              "true", "Has VMLx hazards">;
 273
 274 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 275 // VFP to NEON, as an execution domain optimization.
 276 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 277                                              "UseNEONForFPMovs", "true",
 278                                              "Convert VMOVSR, VMOVRS, "
 279                                              "VMOVS to NEON">;
 280
 281 // Some processors benefit from using NEON instructions for scalar
 282 // single-precision FP operations. This affects instruction selection and should
 283 // only be enabled if the handling of denormals is not important.
 284 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 285                                              "UseNEONForSinglePrecisionFP",
 286                                              "true",
 287                                              "Use NEON for single precision FP">;
 288
 289 // On some processors, VLDn instructions that access unaligned data take one
 290 // extra cycle. Take that into account when computing operand latencies.
 291 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 292                                              "true",
 293                                              "Check for VLDn unaligned access">;
 294
 295 // Some processors have a nonpipelined VFP coprocessor.
 296 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 297                                               "NonpipelinedVFP", "true",
 298                                               "VFP instructions are not pipelined">;
 299
 300 // Some processors have FP multiply-accumulate instructions that don't
 301 // play nicely with other VFP / NEON instructions, and it's generally better
 302 // to just not use them.
 303 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 304                                              "Disable VFP / NEON MAC instructions">;
 305
 306 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 307 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 308                                              "HasVMLxForwarding", "true",
 309                                              "Has multiplier accumulator forwarding">;
 310
 311 // Disable 32-bit to 16-bit narrowing for experimentation.
 312 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 313                                              "Prefer 32-bit Thumb instrs">;
 314
 315 def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2",
 316                                               "Prefer 32-bit alignment for loops">;
 317
 318 def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "1",
 319                         "Model MVE instructions as a 1 beat per tick architecture">;
 320
 321 def FeatureMVEVectorCostFactor2 : SubtargetFeature<"mve2beat", "MVEVectorCostFactor", "2",
 322                         "Model MVE instructions as a 2 beats per tick architecture">;
 323
 324 def FeatureMVEVectorCostFactor4 : SubtargetFeature<"mve4beat", "MVEVectorCostFactor", "4",
 325                         "Model MVE instructions as a 4 beats per tick architecture">;
 326
 327 /// Some instructions update CPSR partially, which can add false dependency for
 328 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 329 /// mapped to a separate physical register. Avoid partial CPSR update for these
 330 /// processors.
 331 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 332                                                "AvoidCPSRPartialUpdate", "true",
 333                                  "Avoid CPSR partial update for OOO execution">;
 334
 335 /// Disable +1 predication cost for instructions updating CPSR.
 336 /// Enabled for Cortex-A57.
 337 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 338                                                   "CheapPredicableCPSRDef",
 339                                                   "true",
 340                   "Disable +1 predication cost for instructions updating CPSR">;
 341
 342 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 343                                              "AvoidMOVsShifterOperand", "true",
 344                                              "Avoid movs instructions with "
 345                                              "shifter operand">;
 346
 347 // Some processors perform return stack prediction. CodeGen should avoid issue
 348 // "normal" call instructions to callees which do not return.
 349 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 350                                               "HasRetAddrStack", "true",
 351                                               "Has return address stack">;
 352
 353 // Some processors have no branch predictor, which changes the expected cost of
 354 // taking a branch which affects the choice of whether to use predicated
 355 // instructions.
 356 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 357                                                    "HasBranchPredictor", "false",
 358                                                    "Has no branch predictor">;
 359
 360 /// DSP extension.
 361 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 362                                              "Supports DSP instructions in "
 363                                              "ARM and/or Thumb2">;
 364
 365 // Multiprocessing extension.
 366 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 367                                         "Supports Multiprocessing extension">;
 368
 369 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 370 def FeatureVirtualization : SubtargetFeature<"virtualization",
 371                                              "HasVirtualization", "true",
 372                                              "Supports Virtualization extension",
 373                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 374
 375 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 376 // See ARMInstrInfo.td for details.
 377 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 378                                              "NaCl trap">;
 379
 380 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 381                                              "StrictAlign", "true",
 382                                              "Disallow all unaligned memory "
 383                                              "access">;
 384
 385 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 386                                              "Generate calls via indirect call "
 387                                              "instructions">;
 388
 389 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 390                                              "GenExecuteOnly", "true",
 391                                              "Enable the generation of "
 392                                              "execute only code.">;
 393
 394 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 395                                              "Reserve R9, making it unavailable"
 396                                              " as GPR">;
 397
 398 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 399                                              "Don't use movt/movw pairs for "
 400                                              "32-bit imms">;
 401
 402 def FeatureNoNegativeImmediates
 403                           : SubtargetFeature<"no-neg-immediates",
 404                                              "NegativeImmediates", "false",
 405                                              "Convert immediates and instructions "
 406                                              "to their negated or complemented "
 407                                              "equivalent when the immediate does "
 408                                              "not fit in the encoding.">;
 409
 410 // Use the MachineScheduler for instruction scheduling for the subtarget.
 411 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 412                                         "Use the MachineScheduler">;
 413
 414 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 415     "DisablePostRAScheduler", "true",
 416     "Don't schedule again after register allocation">;
 417
 418 // Enable use of alias analysis during code generation
 419 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 420                                     "Use alias analysis during codegen">;
 421
 422 // Armv8.5-A extensions
 423
 424 def FeatureSB       : SubtargetFeature<"sb", "HasSB", "true",
 425   "Enable v8.5a Speculation Barrier" >;
 426
 427 // Armv8.1-M extensions
 428
 429 def FeatureLOB            : SubtargetFeature<"lob", "HasLOB", "true",
 430                                              "Enable Low Overhead Branch "
 431                                              "extensions">;
 432
 433 //===----------------------------------------------------------------------===//
 434 // ARM architecture class
 435 //
 436
 437 // A-series ISA
 438 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 439                                      "Is application profile ('A' series)">;
 440
 441 // R-series ISA
 442 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 443                                      "Is realtime profile ('R' series)">;
 444
 445 // M-series ISA
 446 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 447                                      "Is microcontroller profile ('M' series)">;
 448
 449
 450 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 451                                      "Enable Thumb2 instructions">;
 452
 453 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 454                                      "Does not support ARM mode execution">;
 455
 456 //===----------------------------------------------------------------------===//
 457 // ARM ISAa.
 458 //
 459
 460 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 461                                    "Support ARM v4T instructions">;
 462
 463 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 464                                    "Support ARM v5T instructions",
 465                                    [HasV4TOps]>;
 466
 467 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 468                                    "Support ARM v5TE, v5TEj, and "
 469                                    "v5TExp instructions",
 470                                    [HasV5TOps]>;
 471
 472 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 473                                    "Support ARM v6 instructions",
 474                                    [HasV5TEOps]>;
 475
 476 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 477                                    "Support ARM v6M instructions",
 478                                    [HasV6Ops]>;
 479
 480 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 481                                          "Support ARM v8M Baseline instructions",
 482                                          [HasV6MOps]>;
 483
 484 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 485                                    "Support ARM v6k instructions",
 486                                    [HasV6Ops]>;
 487
 488 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 489                                    "Support ARM v6t2 instructions",
 490                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 491
 492 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 493                                    "Support ARM v7 instructions",
 494                                    [HasV6T2Ops, FeaturePerfMon,
 495                                     FeatureV7Clrex]>;
 496
 497 def HasV8MMainlineOps :
 498                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 499                                    "Support ARM v8M Mainline instructions",
 500                                    [HasV7Ops]>;
 501
 502 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 503                                    "Support ARM v8 instructions",
 504                                    [HasV7Ops, FeatureAcquireRelease]>;
 505
 506 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 507                                    "Support ARM v8.1a instructions",
 508                                    [HasV8Ops]>;
 509
 510 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 511                                    "Support ARM v8.2a instructions",
 512                                    [HasV8_1aOps]>;
 513
 514 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 515                                    "Support ARM v8.3a instructions",
 516                                    [HasV8_2aOps]>;
 517
 518 def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 519                                    "Support ARM v8.4a instructions",
 520                                    [HasV8_3aOps, FeatureDotProd]>;
 521
 522 def HasV8_5aOps   : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
 523                                    "Support ARM v8.5a instructions",
 524                                    [HasV8_4aOps, FeatureSB]>;
 525
 526 def HasV8_1MMainlineOps : SubtargetFeature<
 527                "v8.1m.main", "HasV8_1MMainlineOps", "true",
 528                "Support ARM v8-1M Mainline instructions",
 529                [HasV8MMainlineOps]>;
 530 def HasMVEIntegerOps : SubtargetFeature<
 531                "mve", "HasMVEIntegerOps", "true",
 532                "Support M-Class Vector Extension with integer ops",
 533                [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>;
 534 def HasMVEFloatOps : SubtargetFeature<
 535                "mve.fp", "HasMVEFloatOps", "true",
 536                "Support M-Class Vector Extension with integer and floating ops",
 537                [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>;
 538
 539 //===----------------------------------------------------------------------===//
 540 // ARM Processor subtarget features.
 541 //
 542
 543 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 544                                    "Cortex-A5 ARM processors", []>;
 545 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 546                                    "Cortex-A7 ARM processors", []>;
 547 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 548                                    "Cortex-A8 ARM processors", []>;
 549 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 550                                    "Cortex-A9 ARM processors", []>;
 551 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 552                                    "Cortex-A12 ARM processors", []>;
 553 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 554                                    "Cortex-A15 ARM processors", []>;
 555 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 556                                    "Cortex-A17 ARM processors", []>;
 557 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 558                                    "Cortex-A32 ARM processors", []>;
 559 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 560                                    "Cortex-A35 ARM processors", []>;
 561 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 562                                    "Cortex-A53 ARM processors", []>;
 563 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 564                                    "Cortex-A55 ARM processors", []>;
 565 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 566                                    "Cortex-A57 ARM processors", []>;
 567 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 568                                    "Cortex-A72 ARM processors", []>;
 569 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 570                                    "Cortex-A73 ARM processors", []>;
 571 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 572                                    "Cortex-A75 ARM processors", []>;
 573 def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
 574                                    "Cortex-A76 ARM processors", []>;
 575
 576 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 577                                    "Qualcomm Krait processors", []>;
 578 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 579                                    "Qualcomm Kryo processors", []>;
 580 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 581                                    "Swift ARM processors", []>;
 582
 583 def ProcExynos  : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos",
 584                                    "Samsung Exynos processors",
 585                                    [FeatureZCZeroing,
 586                                     FeatureUseWideStrideVFP,
 587                                     FeatureUseAA,
 588                                     FeatureSplatVFPToNeon,
 589                                     FeatureSlowVGETLNi32,
 590                                     FeatureSlowVDUP32,
 591                                     FeatureSlowFPBrcc,
 592                                     FeatureProfUnpredicate,
 593                                     FeatureHWDivThumb,
 594                                     FeatureHWDivARM,
 595                                     FeatureHasSlowFPVMLx,
 596                                     FeatureHasRetAddrStack,
 597                                     FeatureFuseLiterals,
 598                                     FeatureFuseAES,
 599                                     FeatureExpandMLx,
 600                                     FeatureCrypto,
 601                                     FeatureCRC]>;
 602
 603 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 604                                    "Cortex-R4 ARM processors", []>;
 605 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 606                                    "Cortex-R5 ARM processors", []>;
 607 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 608                                    "Cortex-R7 ARM processors", []>;
 609 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 610                                    "Cortex-R52 ARM processors", []>;
 611
 612 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 613                                    "Cortex-M3 ARM processors", []>;
 614
 615
 616 //===----------------------------------------------------------------------===//
 617 // ARM Helper classes.
 618 //
 619
 620 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 621   : SubtargetFeature<fname, "ARMArch", aname,
 622                      !strconcat(aname, " architecture"), features>;
 623
 624 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 625   : Processor<Name, NoItineraries, Features>;
 626
 627
 628 //===----------------------------------------------------------------------===//
 629 // ARM architectures
 630 //
 631
 632 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 633
 634 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 635
 636 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 637
 638 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 639
 640 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 641
 642 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 643
 644 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 645
 646 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 647
 648 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 649
 650 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
 651                                                        FeatureDSP]>;
 652
 653 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 654                                                        FeatureDSP]>;
 655
 656 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 657
 658 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 659                                                        FeatureTrustZone]>;
 660
 661 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 662                                                        FeatureNoARM,
 663                                                        ModeThumb,
 664                                                        FeatureDB,
 665                                                        FeatureMClass,
 666                                                        FeatureStrictAlign]>;
 667
 668 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 669                                                        FeatureNoARM,
 670                                                        ModeThumb,
 671                                                        FeatureDB,
 672                                                        FeatureMClass,
 673                                                        FeatureStrictAlign]>;
 674
 675 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 676                                                        FeatureNEON,
 677                                                        FeatureDB,
 678                                                        FeatureDSP,
 679                                                        FeatureAClass]>;
 680
 681 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 682                                                        FeatureNEON,
 683                                                        FeatureDB,
 684                                                        FeatureDSP,
 685                                                        FeatureTrustZone,
 686                                                        FeatureMP,
 687                                                        FeatureVirtualization,
 688                                                        FeatureAClass]>;
 689
 690 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 691                                                        FeatureDB,
 692                                                        FeatureDSP,
 693                                                        FeatureHWDivThumb,
 694                                                        FeatureRClass]>;
 695
 696 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 697                                                        FeatureThumb2,
 698                                                        FeatureNoARM,
 699                                                        ModeThumb,
 700                                                        FeatureDB,
 701                                                        FeatureHWDivThumb,
 702                                                        FeatureMClass]>;
 703
 704 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 705                                                        FeatureThumb2,
 706                                                        FeatureNoARM,
 707                                                        ModeThumb,
 708                                                        FeatureDB,
 709                                                        FeatureHWDivThumb,
 710                                                        FeatureMClass,
 711                                                        FeatureDSP]>;
 712
 713 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 714                                                        FeatureAClass,
 715                                                        FeatureDB,
 716                                                        FeatureFPARMv8,
 717                                                        FeatureNEON,
 718                                                        FeatureDSP,
 719                                                        FeatureTrustZone,
 720                                                        FeatureMP,
 721                                                        FeatureVirtualization,
 722                                                        FeatureCrypto,
 723                                                        FeatureCRC]>;
 724
 725 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 726                                                        FeatureAClass,
 727                                                        FeatureDB,
 728                                                        FeatureFPARMv8,
 729                                                        FeatureNEON,
 730                                                        FeatureDSP,
 731                                                        FeatureTrustZone,
 732                                                        FeatureMP,
 733                                                        FeatureVirtualization,
 734                                                        FeatureCrypto,
 735                                                        FeatureCRC]>;
 736
 737 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 738                                                        FeatureAClass,
 739                                                        FeatureDB,
 740                                                        FeatureFPARMv8,
 741                                                        FeatureNEON,
 742                                                        FeatureDSP,
 743                                                        FeatureTrustZone,
 744                                                        FeatureMP,
 745                                                        FeatureVirtualization,
 746                                                        FeatureCrypto,
 747                                                        FeatureCRC,
 748                                                        FeatureRAS]>;
 749
 750 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 751                                                        FeatureAClass,
 752                                                        FeatureDB,
 753                                                        FeatureFPARMv8,
 754                                                        FeatureNEON,
 755                                                        FeatureDSP,
 756                                                        FeatureTrustZone,
 757                                                        FeatureMP,
 758                                                        FeatureVirtualization,
 759                                                        FeatureCrypto,
 760                                                        FeatureCRC,
 761                                                        FeatureRAS]>;
 762
 763 def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
 764                                                        FeatureAClass,
 765                                                        FeatureDB,
 766                                                        FeatureFPARMv8,
 767                                                        FeatureNEON,
 768                                                        FeatureDSP,
 769                                                        FeatureTrustZone,
 770                                                        FeatureMP,
 771                                                        FeatureVirtualization,
 772                                                        FeatureCrypto,
 773                                                        FeatureCRC,
 774                                                        FeatureRAS,
 775                                                        FeatureDotProd]>;
 776
 777 def ARMv85a   : Architecture<"armv8.5-a", "ARMv85a",  [HasV8_5aOps,
 778                                                        FeatureAClass,
 779                                                        FeatureDB,
 780                                                        FeatureFPARMv8,
 781                                                        FeatureNEON,
 782                                                        FeatureDSP,
 783                                                        FeatureTrustZone,
 784                                                        FeatureMP,
 785                                                        FeatureVirtualization,
 786                                                        FeatureCrypto,
 787                                                        FeatureCRC,
 788                                                        FeatureRAS,
 789                                                        FeatureDotProd]>;
 790
 791 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 792                                                        FeatureRClass,
 793                                                        FeatureDB,
 794                                                        FeatureDFB,
 795                                                        FeatureDSP,
 796                                                        FeatureCRC,
 797                                                        FeatureMP,
 798                                                        FeatureVirtualization,
 799                                                        FeatureFPARMv8,
 800                                                        FeatureNEON]>;
 801
 802 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 803                                                       [HasV8MBaselineOps,
 804                                                        FeatureNoARM,
 805                                                        ModeThumb,
 806                                                        FeatureDB,
 807                                                        FeatureHWDivThumb,
 808                                                        FeatureV7Clrex,
 809                                                        Feature8MSecExt,
 810                                                        FeatureAcquireRelease,
 811                                                        FeatureMClass,
 812                                                        FeatureStrictAlign]>;
 813
 814 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 815                                                       [HasV8MMainlineOps,
 816                                                        FeatureNoARM,
 817                                                        ModeThumb,
 818                                                        FeatureDB,
 819                                                        FeatureHWDivThumb,
 820                                                        Feature8MSecExt,
 821                                                        FeatureAcquireRelease,
 822                                                        FeatureMClass]>;
 823
 824 def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline",
 825                                                       [HasV8_1MMainlineOps,
 826                                                        FeatureNoARM,
 827                                                        ModeThumb,
 828                                                        FeatureDB,
 829                                                        FeatureHWDivThumb,
 830                                                        Feature8MSecExt,
 831                                                        FeatureAcquireRelease,
 832                                                        FeatureMClass,
 833                                                        FeatureRAS,
 834                                                        FeatureLOB]>;
 835
 836 // Aliases
 837 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 838 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 839 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 840 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 841 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 842 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 843
 844
 845 //===----------------------------------------------------------------------===//
 846 // ARM schedules.
 847 //===----------------------------------------------------------------------===//
 848 //
 849 include "ARMPredicates.td"
 850 include "ARMSchedule.td"
 851
 852 //===----------------------------------------------------------------------===//
 853 // ARM processors
 854 //
 855
 856 // Dummy CPU, used to target architectures
 857 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 858
 859 // FIXME: Several processors below are not using their own scheduler
 860 // model, but one of similar/previous processor. These should be fixed.
 861
 862 def : ProcNoItin<"arm8",                                [ARMv4]>;
 863 def : ProcNoItin<"arm810",                              [ARMv4]>;
 864 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 865 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 866 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 867 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 868
 869 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 870 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 871 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 872 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 873 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 874 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 875 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 876 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 877 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 878 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 879 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 880
 881 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 882 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 883
 884 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 885 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 886 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 887 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 888 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 889 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 890 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 891 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 892 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 893 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 894
 895 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 896 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 897                                                          FeatureVFP2,
 898                                                          FeatureHasSlowFPVMLx]>;
 899
 900 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 901 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 902 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 903 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 904
 905 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 906 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 907 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 908                                                          FeatureVFP2,
 909                                                          FeatureHasSlowFPVMLx]>;
 910
 911 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 912 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 913                                                          FeatureVFP2,
 914                                                          FeatureHasSlowFPVMLx]>;
 915
 916 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 917 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 918                                                          FeatureVFP2,
 919                                                          FeatureHasSlowFPVMLx]>;
 920
 921 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 922                                                          FeatureHasRetAddrStack,
 923                                                          FeatureTrustZone,
 924                                                          FeatureSlowFPBrcc,
 925                                                          FeatureHasSlowFPVMLx,
 926                                                          FeatureVMLxForwarding,
 927                                                          FeatureMP,
 928                                                          FeatureVFP4]>;
 929
 930 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 931                                                          FeatureHasRetAddrStack,
 932                                                          FeatureTrustZone,
 933                                                          FeatureSlowFPBrcc,
 934                                                          FeatureHasVMLxHazards,
 935                                                          FeatureHasSlowFPVMLx,
 936                                                          FeatureVMLxForwarding,
 937                                                          FeatureMP,
 938                                                          FeatureVFP4,
 939                                                          FeatureVirtualization]>;
 940
 941 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 942                                                          FeatureHasRetAddrStack,
 943                                                          FeatureNonpipelinedVFP,
 944                                                          FeatureTrustZone,
 945                                                          FeatureSlowFPBrcc,
 946                                                          FeatureHasVMLxHazards,
 947                                                          FeatureHasSlowFPVMLx,
 948                                                          FeatureVMLxForwarding]>;
 949
 950 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 951                                                          FeatureHasRetAddrStack,
 952                                                          FeatureTrustZone,
 953                                                          FeatureHasVMLxHazards,
 954                                                          FeatureVMLxForwarding,
 955                                                          FeatureFP16,
 956                                                          FeatureAvoidPartialCPSR,
 957                                                          FeatureExpandMLx,
 958                                                          FeaturePreferVMOVSR,
 959                                                          FeatureMuxedUnits,
 960                                                          FeatureNEONForFPMovs,
 961                                                          FeatureCheckVLDnAlign,
 962                                                          FeatureMP]>;
 963
 964 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 965                                                          FeatureHasRetAddrStack,
 966                                                          FeatureTrustZone,
 967                                                          FeatureVMLxForwarding,
 968                                                          FeatureVFP4,
 969                                                          FeatureAvoidPartialCPSR,
 970                                                          FeatureVirtualization,
 971                                                          FeatureMP]>;
 972
 973 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 974                                                          FeatureDontWidenVMOVS,
 975                                                          FeatureSplatVFPToNeon,
 976                                                          FeatureHasRetAddrStack,
 977                                                          FeatureMuxedUnits,
 978                                                          FeatureTrustZone,
 979                                                          FeatureVFP4,
 980                                                          FeatureMP,
 981                                                          FeatureCheckVLDnAlign,
 982                                                          FeatureAvoidPartialCPSR,
 983                                                          FeatureVirtualization]>;
 984
 985 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 986                                                          FeatureHasRetAddrStack,
 987                                                          FeatureTrustZone,
 988                                                          FeatureMP,
 989                                                          FeatureVMLxForwarding,
 990                                                          FeatureVFP4,
 991                                                          FeatureAvoidPartialCPSR,
 992                                                          FeatureVirtualization]>;
 993
 994 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 995 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 996                                                          FeatureHasRetAddrStack,
 997                                                          FeatureMuxedUnits,
 998                                                          FeatureCheckVLDnAlign,
 999                                                          FeatureVMLxForwarding,
1000                                                          FeatureFP16,
1001                                                          FeatureAvoidPartialCPSR,
1002                                                          FeatureVFP4,
1003                                                          FeatureHWDivThumb,
1004                                                          FeatureHWDivARM]>;
1005
1006 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
1007                                                          FeatureHasRetAddrStack,
1008                                                          FeatureNEONForFP,
1009                                                          FeatureVFP4,
1010                                                          FeatureUseWideStrideVFP,
1011                                                          FeatureMP,
1012                                                          FeatureHWDivThumb,
1013                                                          FeatureHWDivARM,
1014                                                          FeatureAvoidPartialCPSR,
1015                                                          FeatureAvoidMOVsShOp,
1016                                                          FeatureHasSlowFPVMLx,
1017                                                          FeatureHasVMLxHazards,
1018                                                          FeatureProfUnpredicate,
1019                                                          FeaturePrefISHSTBarrier,
1020                                                          FeatureSlowOddRegister,
1021                                                          FeatureSlowLoadDSubreg,
1022                                                          FeatureSlowVGETLNi32,
1023                                                          FeatureSlowVDUP32,
1024                                                          FeatureUseMISched,
1025                                                          FeatureNoPostRASched]>;
1026
1027 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
1028                                                          FeatureHasRetAddrStack,
1029                                                          FeatureAvoidPartialCPSR]>;
1030
1031 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
1032                                                          FeatureHasRetAddrStack,
1033                                                          FeatureSlowFPBrcc,
1034                                                          FeatureHasSlowFPVMLx,
1035                                                          FeatureVFP3_D16,
1036                                                          FeatureAvoidPartialCPSR]>;
1037
1038 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
1039                                                          FeatureHasRetAddrStack,
1040                                                          FeatureVFP3_D16,
1041                                                          FeatureSlowFPBrcc,
1042                                                          FeatureHWDivARM,
1043                                                          FeatureHasSlowFPVMLx,
1044                                                          FeatureAvoidPartialCPSR]>;
1045
1046 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
1047                                                          FeatureHasRetAddrStack,
1048                                                          FeatureVFP3_D16,
1049                                                          FeatureFP16,
1050                                                          FeatureMP,
1051                                                          FeatureSlowFPBrcc,
1052                                                          FeatureHWDivARM,
1053                                                          FeatureHasSlowFPVMLx,
1054                                                          FeatureAvoidPartialCPSR]>;
1055
1056 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
1057                                                          FeatureHasRetAddrStack,
1058                                                          FeatureVFP3_D16,
1059                                                          FeatureFP16,
1060                                                          FeatureMP,
1061                                                          FeatureSlowFPBrcc,
1062                                                          FeatureHWDivARM,
1063                                                          FeatureHasSlowFPVMLx,
1064                                                          FeatureAvoidPartialCPSR]>;
1065
1066 def : ProcessorModel<"cortex-m3",   CortexM4Model,      [ARMv7m,
1067                                                          ProcM3,
1068                                                          FeaturePrefLoopAlign32,
1069                                                          FeatureUseMISched,
1070                                                          FeatureUseAA,
1071                                                          FeatureHasNoBranchPredictor]>;
1072
1073 def : ProcessorModel<"sc300",       CortexM4Model,      [ARMv7m,
1074                                                          ProcM3,
1075                                                          FeatureUseMISched,
1076                                                          FeatureUseAA,
1077                                                          FeatureHasNoBranchPredictor]>;
1078
1079 def : ProcessorModel<"cortex-m4", CortexM4Model,        [ARMv7em,
1080                                                          FeatureVFP4_D16_SP,
1081                                                          FeaturePrefLoopAlign32,
1082                                                          FeatureHasSlowFPVMLx,
1083                                                          FeatureUseMISched,
1084                                                          FeatureUseAA,
1085                                                          FeatureHasNoBranchPredictor]>;
1086
1087 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
1088                                                          FeatureFPARMv8_D16]>;
1089
1090 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
1091                                                          FeatureNoMovt]>;
1092
1093 def : ProcessorModel<"cortex-m33", CortexM4Model,       [ARMv8mMainline,
1094                                                          FeatureDSP,
1095                                                          FeatureFPARMv8_D16_SP,
1096                                                          FeaturePrefLoopAlign32,
1097                                                          FeatureHasSlowFPVMLx,
1098                                                          FeatureUseMISched,
1099                                                          FeatureUseAA,
1100                                                          FeatureHasNoBranchPredictor]>;
1101
1102 def : ProcessorModel<"cortex-m35p", CortexM4Model,      [ARMv8mMainline,
1103                                                          FeatureDSP,
1104                                                          FeatureFPARMv8_D16_SP,
1105                                                          FeaturePrefLoopAlign32,
1106                                                          FeatureHasSlowFPVMLx,
1107                                                          FeatureUseMISched,
1108                                                          FeatureUseAA,
1109                                                          FeatureHasNoBranchPredictor]>;
1110
1111
1112 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
1113                                                          FeatureHWDivThumb,
1114                                                          FeatureHWDivARM,
1115                                                          FeatureCrypto,
1116                                                          FeatureCRC]>;
1117
1118 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
1119                                                          FeatureHWDivThumb,
1120                                                          FeatureHWDivARM,
1121                                                          FeatureCrypto,
1122                                                          FeatureCRC]>;
1123
1124 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
1125                                                          FeatureHWDivThumb,
1126                                                          FeatureHWDivARM,
1127                                                          FeatureCrypto,
1128                                                          FeatureCRC,
1129                                                          FeatureFPAO]>;
1130
1131 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
1132                                                          FeatureHWDivThumb,
1133                                                          FeatureHWDivARM,
1134                                                          FeatureDotProd]>;
1135
1136 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
1137                                                          FeatureHWDivThumb,
1138                                                          FeatureHWDivARM,
1139                                                          FeatureCrypto,
1140                                                          FeatureCRC,
1141                                                          FeatureFPAO,
1142                                                          FeatureAvoidPartialCPSR,
1143                                                          FeatureCheapPredicableCPSR]>;
1144
1145 def : ProcessorModel<"cortex-a72",  CortexA57Model,     [ARMv8a, ProcA72,
1146                                                          FeatureHWDivThumb,
1147                                                          FeatureHWDivARM,
1148                                                          FeatureCrypto,
1149                                                          FeatureCRC]>;
1150
1151 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
1152                                                          FeatureHWDivThumb,
1153                                                          FeatureHWDivARM,
1154                                                          FeatureCrypto,
1155                                                          FeatureCRC]>;
1156
1157 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
1158                                                          FeatureHWDivThumb,
1159                                                          FeatureHWDivARM,
1160                                                          FeatureDotProd]>;
1161
1162 def : ProcNoItin<"cortex-a76",                          [ARMv82a, ProcA76,
1163                                                          FeatureHWDivThumb,
1164                                                          FeatureHWDivARM,
1165                                                          FeatureCrypto,
1166                                                          FeatureCRC,
1167                                                          FeatureFullFP16,
1168                                                          FeatureDotProd]>;
1169
1170 def : ProcNoItin<"cortex-a76ae",                        [ARMv82a, ProcA76,
1171                                                          FeatureHWDivThumb,
1172                                                          FeatureHWDivARM,
1173                                                          FeatureCrypto,
1174                                                          FeatureCRC,
1175                                                          FeatureFullFP16,
1176                                                          FeatureDotProd]>;
1177
1178 def : ProcNoItin<"neoverse-n1",                         [ARMv82a,
1179                                                          FeatureHWDivThumb,
1180                                                          FeatureHWDivARM,
1181                                                          FeatureCrypto,
1182                                                          FeatureCRC,
1183                                                          FeatureDotProd]>;
1184
1185 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
1186                                                          FeatureHasRetAddrStack,
1187                                                          FeatureNEONForFP,
1188                                                          FeatureVFP4,
1189                                                          FeatureMP,
1190                                                          FeatureHWDivThumb,
1191                                                          FeatureHWDivARM,
1192                                                          FeatureAvoidPartialCPSR,
1193                                                          FeatureAvoidMOVsShOp,
1194                                                          FeatureHasSlowFPVMLx,
1195                                                          FeatureCrypto,
1196                                                          FeatureUseMISched,
1197                                                          FeatureZCZeroing,
1198                                                          FeatureNoPostRASched]>;
1199
1200 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynos]>;
1201 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynos]>;
1202 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynos]>;
1203 def : ProcNoItin<"exynos-m4",                           [ARMv82a, ProcExynos,
1204                                                          FeatureFullFP16,
1205                                                          FeatureDotProd]>;
1206 def : ProcNoItin<"exynos-m5",                           [ARMv82a, ProcExynos,
1207                                                          FeatureFullFP16,
1208                                                          FeatureDotProd]>;
1209
1210 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1211                                                          FeatureHWDivThumb,
1212                                                          FeatureHWDivARM,
1213                                                          FeatureCrypto,
1214                                                          FeatureCRC]>;
1215
1216 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1217                                                          FeatureUseMISched,
1218                                                          FeatureFPAO,
1219                                                          FeatureUseAA]>;
1220
1221 //===----------------------------------------------------------------------===//
1222 // Register File Description
1223 //===----------------------------------------------------------------------===//
1224
1225 include "ARMRegisterInfo.td"
1226 include "ARMRegisterBanks.td"
1227 include "ARMCallingConv.td"
1228
1229 //===----------------------------------------------------------------------===//
1230 // Instruction Descriptions
1231 //===----------------------------------------------------------------------===//
1232
1233 include "ARMInstrInfo.td"
1234 def ARMInstrInfo : InstrInfo;
1235
1236 //===----------------------------------------------------------------------===//
1237 // Declare the target which we are implementing
1238 //===----------------------------------------------------------------------===//
1239
1240 def ARMAsmWriter : AsmWriter {
1241   string AsmWriterClassName  = "InstPrinter";
1242   int PassSubtarget = 1;
1243   int Variant = 0;
1244   bit isMCAsmWriter = 1;
1245 }
1246
1247 def ARMAsmParser : AsmParser {
1248   bit ReportMultipleNearMisses = 1;
1249 }
1250
1251 def ARMAsmParserVariant : AsmParserVariant {
1252   int Variant = 0;
1253   string Name = "ARM";
1254   string BreakCharacters = ".";
1255 }
1256
1257 def ARM : Target {
1258   // Pull in Instruction Info.
1259   let InstructionSet = ARMInstrInfo;
1260   let AssemblyWriters = [ARMAsmWriter];
1261   let AssemblyParsers = [ARMAsmParser];
1262   let AssemblyParserVariants = [ARMAsmParserVariant];
1263   let AllowRegisterRenaming = 1;
1264 }