1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //===----------------------------------------------------------------------===//
13 #include "ARMBaseRegisterInfo.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMFrameLowering.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "MCTargetDesc/ARMBaseInfo.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineOperand.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/RegisterScavenging.h"
33 #include "llvm/CodeGen/TargetInstrInfo.h"
34 #include "llvm/CodeGen/TargetRegisterInfo.h"
35 #include "llvm/CodeGen/VirtRegMap.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DebugLoc.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/MC/MCInstrDesc.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
50 #define DEBUG_TYPE "arm-register-info"
52 #define GET_REGINFO_TARGET_DESC
53 #include "ARMGenRegisterInfo.inc"
57 ARMBaseRegisterInfo::ARMBaseRegisterInfo()
58 : ARMGenRegisterInfo(ARM::LR
, 0, 0, ARM::PC
) {}
60 static unsigned getFramePointerReg(const ARMSubtarget
&STI
) {
61 return STI
.useR7AsFramePointer() ? ARM::R7
: ARM::R11
;
65 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF
) const {
66 const ARMSubtarget
&STI
= MF
->getSubtarget
<ARMSubtarget
>();
67 bool UseSplitPush
= STI
.splitFramePushPop(*MF
);
68 const MCPhysReg
*RegList
=
71 : (UseSplitPush
? CSR_AAPCS_SplitPush_SaveList
: CSR_AAPCS_SaveList
);
73 const Function
&F
= MF
->getFunction();
74 if (F
.getCallingConv() == CallingConv::GHC
) {
75 // GHC set of callee saved regs is empty as all those regs are
76 // used for passing STG regs around
77 return CSR_NoRegs_SaveList
;
78 } else if (F
.hasFnAttribute("interrupt")) {
80 // M-class CPUs have hardware which saves the registers needed to allow a
81 // function conforming to the AAPCS to function as a handler.
82 return UseSplitPush
? CSR_AAPCS_SplitPush_SaveList
: CSR_AAPCS_SaveList
;
83 } else if (F
.getFnAttribute("interrupt").getValueAsString() == "FIQ") {
84 // Fast interrupt mode gives the handler a private copy of R8-R14, so less
85 // need to be saved to restore user-mode state.
86 return CSR_FIQ_SaveList
;
88 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
89 // exception handling.
90 return CSR_GenericInt_SaveList
;
94 if (STI
.getTargetLowering()->supportSwiftError() &&
95 F
.getAttributes().hasAttrSomewhere(Attribute::SwiftError
)) {
96 if (STI
.isTargetDarwin())
97 return CSR_iOS_SwiftError_SaveList
;
99 return UseSplitPush
? CSR_AAPCS_SplitPush_SwiftError_SaveList
:
100 CSR_AAPCS_SwiftError_SaveList
;
103 if (STI
.isTargetDarwin() && F
.getCallingConv() == CallingConv::CXX_FAST_TLS
)
104 return MF
->getInfo
<ARMFunctionInfo
>()->isSplitCSR()
105 ? CSR_iOS_CXX_TLS_PE_SaveList
106 : CSR_iOS_CXX_TLS_SaveList
;
110 const MCPhysReg
*ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
111 const MachineFunction
*MF
) const {
112 assert(MF
&& "Invalid MachineFunction pointer.");
113 if (MF
->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS
&&
114 MF
->getInfo
<ARMFunctionInfo
>()->isSplitCSR())
115 return CSR_iOS_CXX_TLS_ViaCopy_SaveList
;
120 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction
&MF
,
121 CallingConv::ID CC
) const {
122 const ARMSubtarget
&STI
= MF
.getSubtarget
<ARMSubtarget
>();
123 if (CC
== CallingConv::GHC
)
124 // This is academic because all GHC calls are (supposed to be) tail calls
125 return CSR_NoRegs_RegMask
;
127 if (STI
.getTargetLowering()->supportSwiftError() &&
128 MF
.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError
))
129 return STI
.isTargetDarwin() ? CSR_iOS_SwiftError_RegMask
130 : CSR_AAPCS_SwiftError_RegMask
;
132 if (STI
.isTargetDarwin() && CC
== CallingConv::CXX_FAST_TLS
)
133 return CSR_iOS_CXX_TLS_RegMask
;
134 return STI
.isTargetDarwin() ? CSR_iOS_RegMask
: CSR_AAPCS_RegMask
;
138 ARMBaseRegisterInfo::getNoPreservedMask() const {
139 return CSR_NoRegs_RegMask
;
143 ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction
&MF
) const {
144 assert(MF
.getSubtarget
<ARMSubtarget
>().isTargetDarwin() &&
145 "only know about special TLS call on Darwin");
146 return CSR_iOS_TLSCall_RegMask
;
150 ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction
&MF
) const {
151 const ARMSubtarget
&STI
= MF
.getSubtarget
<ARMSubtarget
>();
152 if (!STI
.useSoftFloat() && STI
.hasVFP2Base() && !STI
.isThumb1Only())
153 return CSR_NoRegs_RegMask
;
155 return CSR_FPRegs_RegMask
;
159 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction
&MF
,
160 CallingConv::ID CC
) const {
161 const ARMSubtarget
&STI
= MF
.getSubtarget
<ARMSubtarget
>();
162 // This should return a register mask that is the same as that returned by
163 // getCallPreservedMask but that additionally preserves the register used for
164 // the first i32 argument (which must also be the register used to return a
165 // single i32 return value)
167 // In case that the calling convention does not use the same register for
168 // both or otherwise does not want to enable this optimization, the function
169 // should return NULL
170 if (CC
== CallingConv::GHC
)
171 // This is academic because all GHC calls are (supposed to be) tail calls
173 return STI
.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
174 : CSR_AAPCS_ThisReturn_RegMask
;
177 ArrayRef
<MCPhysReg
> ARMBaseRegisterInfo::getIntraCallClobberedRegs(
178 const MachineFunction
*MF
) const {
179 static const MCPhysReg IntraCallClobberedRegs
[] = {ARM::R12
};
180 return ArrayRef
<MCPhysReg
>(IntraCallClobberedRegs
);
183 BitVector
ARMBaseRegisterInfo::
184 getReservedRegs(const MachineFunction
&MF
) const {
185 const ARMSubtarget
&STI
= MF
.getSubtarget
<ARMSubtarget
>();
186 const ARMFrameLowering
*TFI
= getFrameLowering(MF
);
188 // FIXME: avoid re-calculating this every time.
189 BitVector
Reserved(getNumRegs());
190 markSuperRegs(Reserved
, ARM::SP
);
191 markSuperRegs(Reserved
, ARM::PC
);
192 markSuperRegs(Reserved
, ARM::FPSCR
);
193 markSuperRegs(Reserved
, ARM::APSR_NZCV
);
194 if (TFI
->hasFP(MF
) || STI
.isTargetDarwin())
195 markSuperRegs(Reserved
, getFramePointerReg(STI
));
196 if (hasBasePointer(MF
))
197 markSuperRegs(Reserved
, BasePtr
);
198 // Some targets reserve R9.
199 if (STI
.isR9Reserved())
200 markSuperRegs(Reserved
, ARM::R9
);
201 // Reserve D16-D31 if the subtarget doesn't support them.
203 static_assert(ARM::D31
== ARM::D16
+ 15, "Register list not consecutive!");
204 for (unsigned R
= 0; R
< 16; ++R
)
205 markSuperRegs(Reserved
, ARM::D16
+ R
);
207 const TargetRegisterClass
&RC
= ARM::GPRPairRegClass
;
208 for (unsigned Reg
: RC
)
209 for (MCSubRegIterator
SI(Reg
, this); SI
.isValid(); ++SI
)
210 if (Reserved
.test(*SI
))
211 markSuperRegs(Reserved
, Reg
);
212 // For v8.1m architecture
213 markSuperRegs(Reserved
, ARM::ZR
);
215 assert(checkAllSuperRegsMarked(Reserved
));
219 bool ARMBaseRegisterInfo::
220 isAsmClobberable(const MachineFunction
&MF
, unsigned PhysReg
) const {
221 return !getReservedRegs(MF
).test(PhysReg
);
224 const TargetRegisterClass
*
225 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass
*RC
,
226 const MachineFunction
&MF
) const {
227 const TargetRegisterClass
*Super
= RC
;
228 TargetRegisterClass::sc_iterator I
= RC
->getSuperClasses();
230 switch (Super
->getID()) {
231 case ARM::GPRRegClassID
:
232 case ARM::SPRRegClassID
:
233 case ARM::DPRRegClassID
:
234 case ARM::GPRPairRegClassID
:
236 case ARM::QPRRegClassID
:
237 case ARM::QQPRRegClassID
:
238 case ARM::QQQQPRRegClassID
:
239 if (MF
.getSubtarget
<ARMSubtarget
>().hasNEON())
247 const TargetRegisterClass
*
248 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction
&MF
, unsigned Kind
)
250 return &ARM::GPRRegClass
;
253 const TargetRegisterClass
*
254 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass
*RC
) const {
255 if (RC
== &ARM::CCRRegClass
)
256 return &ARM::rGPRRegClass
; // Can't copy CCR registers.
261 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass
*RC
,
262 MachineFunction
&MF
) const {
263 const ARMSubtarget
&STI
= MF
.getSubtarget
<ARMSubtarget
>();
264 const ARMFrameLowering
*TFI
= getFrameLowering(MF
);
266 switch (RC
->getID()) {
269 case ARM::tGPRRegClassID
: {
270 // hasFP ends up calling getMaxCallFrameComputed() which may not be
271 // available when getPressureLimit() is called as part of
272 // ScheduleDAGRRList.
273 bool HasFP
= MF
.getFrameInfo().isMaxCallFrameSizeComputed()
274 ? TFI
->hasFP(MF
) : true;
277 case ARM::GPRRegClassID
: {
278 bool HasFP
= MF
.getFrameInfo().isMaxCallFrameSizeComputed()
279 ? TFI
->hasFP(MF
) : true;
280 return 10 - HasFP
- (STI
.isR9Reserved() ? 1 : 0);
282 case ARM::SPRRegClassID
: // Currently not used as 'rep' register class.
283 case ARM::DPRRegClassID
:
288 // Get the other register in a GPRPair.
289 static unsigned getPairedGPR(unsigned Reg
, bool Odd
, const MCRegisterInfo
*RI
) {
290 for (MCSuperRegIterator
Supers(Reg
, RI
); Supers
.isValid(); ++Supers
)
291 if (ARM::GPRPairRegClass
.contains(*Supers
))
292 return RI
->getSubReg(*Supers
, Odd
? ARM::gsub_1
: ARM::gsub_0
);
296 // Resolve the RegPairEven / RegPairOdd register allocator hints.
298 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg
,
299 ArrayRef
<MCPhysReg
> Order
,
300 SmallVectorImpl
<MCPhysReg
> &Hints
,
301 const MachineFunction
&MF
,
302 const VirtRegMap
*VRM
,
303 const LiveRegMatrix
*Matrix
) const {
304 const MachineRegisterInfo
&MRI
= MF
.getRegInfo();
305 std::pair
<unsigned, unsigned> Hint
= MRI
.getRegAllocationHint(VirtReg
);
308 switch (Hint
.first
) {
309 case ARMRI::RegPairEven
:
312 case ARMRI::RegPairOdd
:
316 TargetRegisterInfo::getRegAllocationHints(VirtReg
, Order
, Hints
, MF
, VRM
);
320 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
321 // Check if the other part of the pair has already been assigned, and provide
322 // the paired register as the first hint.
323 unsigned Paired
= Hint
.second
;
327 unsigned PairedPhys
= 0;
328 if (Register::isPhysicalRegister(Paired
)) {
330 } else if (VRM
&& VRM
->hasPhys(Paired
)) {
331 PairedPhys
= getPairedGPR(VRM
->getPhys(Paired
), Odd
, this);
334 // First prefer the paired physreg.
335 if (PairedPhys
&& is_contained(Order
, PairedPhys
))
336 Hints
.push_back(PairedPhys
);
338 // Then prefer even or odd registers.
339 for (unsigned Reg
: Order
) {
340 if (Reg
== PairedPhys
|| (getEncodingValue(Reg
) & 1) != Odd
)
342 // Don't provide hints that are paired to a reserved register.
343 unsigned Paired
= getPairedGPR(Reg
, !Odd
, this);
344 if (!Paired
|| MRI
.isReserved(Paired
))
346 Hints
.push_back(Reg
);
352 ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg
, unsigned NewReg
,
353 MachineFunction
&MF
) const {
354 MachineRegisterInfo
*MRI
= &MF
.getRegInfo();
355 std::pair
<unsigned, unsigned> Hint
= MRI
->getRegAllocationHint(Reg
);
356 if ((Hint
.first
== (unsigned)ARMRI::RegPairOdd
||
357 Hint
.first
== (unsigned)ARMRI::RegPairEven
) &&
358 Register::isVirtualRegister(Hint
.second
)) {
359 // If 'Reg' is one of the even / odd register pair and it's now changed
360 // (e.g. coalesced) into a different register. The other register of the
361 // pair allocation hint must be updated to reflect the relationship
363 unsigned OtherReg
= Hint
.second
;
364 Hint
= MRI
->getRegAllocationHint(OtherReg
);
365 // Make sure the pair has not already divorced.
366 if (Hint
.second
== Reg
) {
367 MRI
->setRegAllocationHint(OtherReg
, Hint
.first
, NewReg
);
368 if (Register::isVirtualRegister(NewReg
))
369 MRI
->setRegAllocationHint(NewReg
,
370 Hint
.first
== (unsigned)ARMRI::RegPairOdd
? ARMRI::RegPairEven
371 : ARMRI::RegPairOdd
, OtherReg
);
376 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction
&MF
) const {
377 const MachineFrameInfo
&MFI
= MF
.getFrameInfo();
378 const ARMFunctionInfo
*AFI
= MF
.getInfo
<ARMFunctionInfo
>();
379 const ARMFrameLowering
*TFI
= getFrameLowering(MF
);
381 // If we have stack realignment and VLAs, we have no pointer to use to
382 // access the stack. If we have stack realignment, and a large call frame,
383 // we have no place to allocate the emergency spill slot.
384 if (needsStackRealignment(MF
) && !TFI
->hasReservedCallFrame(MF
))
387 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
388 // negative range for ldr/str (255), and thumb1 is positive offsets only.
390 // It's going to be better to use the SP or Base Pointer instead. When there
391 // are variable sized objects, we can't reference off of the SP, so we
392 // reserve a Base Pointer.
394 // For Thumb2, estimate whether a negative offset from the frame pointer
395 // will be sufficient to reach the whole stack frame. If a function has a
396 // smallish frame, it's less likely to have lots of spills and callee saved
397 // space, so it's all more likely to be within range of the frame pointer.
398 // If it's wrong, the scavenger will still enable access to work, it just
399 // won't be optimal. (We should always be able to reach the emergency
400 // spill slot from the frame pointer.)
401 if (AFI
->isThumb2Function() && MFI
.hasVarSizedObjects() &&
402 MFI
.getLocalFrameSize() >= 128)
404 // For Thumb1, if sp moves, nothing is in range, so force a base pointer.
405 // This is necessary for correctness in cases where we need an emergency
406 // spill slot. (In Thumb1, we can't use a negative offset from the frame
408 if (AFI
->isThumb1OnlyFunction() && !TFI
->hasReservedCallFrame(MF
))
413 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction
&MF
) const {
414 const MachineRegisterInfo
*MRI
= &MF
.getRegInfo();
415 const ARMFrameLowering
*TFI
= getFrameLowering(MF
);
416 // We can't realign the stack if:
417 // 1. Dynamic stack realignment is explicitly disabled,
418 // 2. There are VLAs in the function and the base pointer is disabled.
419 if (!TargetRegisterInfo::canRealignStack(MF
))
421 // Stack realignment requires a frame pointer. If we already started
422 // register allocation with frame pointer elimination, it is too late now.
423 if (!MRI
->canReserveReg(getFramePointerReg(MF
.getSubtarget
<ARMSubtarget
>())))
425 // We may also need a base pointer if there are dynamic allocas or stack
426 // pointer adjustments around calls.
427 if (TFI
->hasReservedCallFrame(MF
))
429 // A base pointer is required and allowed. Check that it isn't too late to
431 return MRI
->canReserveReg(BasePtr
);
434 bool ARMBaseRegisterInfo::
435 cannotEliminateFrame(const MachineFunction
&MF
) const {
436 const MachineFrameInfo
&MFI
= MF
.getFrameInfo();
437 if (MF
.getTarget().Options
.DisableFramePointerElim(MF
) && MFI
.adjustsStack())
439 return MFI
.hasVarSizedObjects() || MFI
.isFrameAddressTaken()
440 || needsStackRealignment(MF
);
444 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction
&MF
) const {
445 const ARMSubtarget
&STI
= MF
.getSubtarget
<ARMSubtarget
>();
446 const ARMFrameLowering
*TFI
= getFrameLowering(MF
);
449 return getFramePointerReg(STI
);
453 /// emitLoadConstPool - Emits a load from constpool to materialize the
454 /// specified immediate.
455 void ARMBaseRegisterInfo::emitLoadConstPool(
456 MachineBasicBlock
&MBB
, MachineBasicBlock::iterator
&MBBI
,
457 const DebugLoc
&dl
, unsigned DestReg
, unsigned SubIdx
, int Val
,
458 ARMCC::CondCodes Pred
, unsigned PredReg
, unsigned MIFlags
) const {
459 MachineFunction
&MF
= *MBB
.getParent();
460 const TargetInstrInfo
&TII
= *MF
.getSubtarget().getInstrInfo();
461 MachineConstantPool
*ConstantPool
= MF
.getConstantPool();
463 ConstantInt::get(Type::getInt32Ty(MF
.getFunction().getContext()), Val
);
464 unsigned Idx
= ConstantPool
->getConstantPoolIndex(C
, 4);
466 BuildMI(MBB
, MBBI
, dl
, TII
.get(ARM::LDRcp
))
467 .addReg(DestReg
, getDefRegState(true), SubIdx
)
468 .addConstantPoolIndex(Idx
)
470 .add(predOps(Pred
, PredReg
))
471 .setMIFlags(MIFlags
);
474 bool ARMBaseRegisterInfo::
475 requiresRegisterScavenging(const MachineFunction
&MF
) const {
479 bool ARMBaseRegisterInfo::
480 trackLivenessAfterRegAlloc(const MachineFunction
&MF
) const {
484 bool ARMBaseRegisterInfo::
485 requiresFrameIndexScavenging(const MachineFunction
&MF
) const {
489 bool ARMBaseRegisterInfo::
490 requiresVirtualBaseRegisters(const MachineFunction
&MF
) const {
494 int64_t ARMBaseRegisterInfo::
495 getFrameIndexInstrOffset(const MachineInstr
*MI
, int Idx
) const {
496 const MCInstrDesc
&Desc
= MI
->getDesc();
497 unsigned AddrMode
= (Desc
.TSFlags
& ARMII::AddrModeMask
);
498 int64_t InstrOffs
= 0;
502 case ARMII::AddrModeT2_i8
:
503 case ARMII::AddrModeT2_i12
:
504 case ARMII::AddrMode_i12
:
505 InstrOffs
= MI
->getOperand(Idx
+1).getImm();
508 case ARMII::AddrMode5
: {
510 const MachineOperand
&OffOp
= MI
->getOperand(Idx
+1);
511 InstrOffs
= ARM_AM::getAM5Offset(OffOp
.getImm());
512 if (ARM_AM::getAM5Op(OffOp
.getImm()) == ARM_AM::sub
)
513 InstrOffs
= -InstrOffs
;
517 case ARMII::AddrMode2
:
519 InstrOffs
= ARM_AM::getAM2Offset(MI
->getOperand(ImmIdx
).getImm());
520 if (ARM_AM::getAM2Op(MI
->getOperand(ImmIdx
).getImm()) == ARM_AM::sub
)
521 InstrOffs
= -InstrOffs
;
523 case ARMII::AddrMode3
:
525 InstrOffs
= ARM_AM::getAM3Offset(MI
->getOperand(ImmIdx
).getImm());
526 if (ARM_AM::getAM3Op(MI
->getOperand(ImmIdx
).getImm()) == ARM_AM::sub
)
527 InstrOffs
= -InstrOffs
;
529 case ARMII::AddrModeT1_s
:
531 InstrOffs
= MI
->getOperand(ImmIdx
).getImm();
535 llvm_unreachable("Unsupported addressing mode!");
538 return InstrOffs
* Scale
;
541 /// needsFrameBaseReg - Returns true if the instruction's frame index
542 /// reference would be better served by a base register other than FP
543 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
544 /// references it should create new base registers for.
545 bool ARMBaseRegisterInfo::
546 needsFrameBaseReg(MachineInstr
*MI
, int64_t Offset
) const {
547 for (unsigned i
= 0; !MI
->getOperand(i
).isFI(); ++i
) {
548 assert(i
< MI
->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
551 // It's the load/store FI references that cause issues, as it can be difficult
552 // to materialize the offset if it won't fit in the literal field. Estimate
553 // based on the size of the local frame and some conservative assumptions
554 // about the rest of the stack frame (note, this is pre-regalloc, so
555 // we don't know everything for certain yet) whether this offset is likely
556 // to be out of range of the immediate. Return true if so.
558 // We only generate virtual base registers for loads and stores, so
559 // return false for everything else.
560 unsigned Opc
= MI
->getOpcode();
562 case ARM::LDRi12
: case ARM::LDRH
: case ARM::LDRBi12
:
563 case ARM::STRi12
: case ARM::STRH
: case ARM::STRBi12
:
564 case ARM::t2LDRi12
: case ARM::t2LDRi8
:
565 case ARM::t2STRi12
: case ARM::t2STRi8
:
566 case ARM::VLDRS
: case ARM::VLDRD
:
567 case ARM::VSTRS
: case ARM::VSTRD
:
568 case ARM::tSTRspi
: case ARM::tLDRspi
:
574 // Without a virtual base register, if the function has variable sized
575 // objects, all fixed-size local references will be via the frame pointer,
576 // Approximate the offset and see if it's legal for the instruction.
577 // Note that the incoming offset is based on the SP value at function entry,
578 // so it'll be negative.
579 MachineFunction
&MF
= *MI
->getParent()->getParent();
580 const ARMFrameLowering
*TFI
= getFrameLowering(MF
);
581 MachineFrameInfo
&MFI
= MF
.getFrameInfo();
582 ARMFunctionInfo
*AFI
= MF
.getInfo
<ARMFunctionInfo
>();
584 // Estimate an offset from the frame pointer.
585 // Conservatively assume all callee-saved registers get pushed. R4-R6
586 // will be earlier than the FP, so we ignore those.
588 int64_t FPOffset
= Offset
- 8;
589 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
590 if (!AFI
->isThumbFunction() || !AFI
->isThumb1OnlyFunction())
592 // Estimate an offset from the stack pointer.
593 // The incoming offset is relating to the SP at the start of the function,
594 // but when we access the local it'll be relative to the SP after local
595 // allocation, so adjust our SP-relative offset by that allocation size.
596 Offset
+= MFI
.getLocalFrameSize();
597 // Assume that we'll have at least some spill slots allocated.
598 // FIXME: This is a total SWAG number. We should run some statistics
599 // and pick a real one.
600 Offset
+= 128; // 128 bytes of spill slots
602 // If there's a frame pointer and the addressing mode allows it, try using it.
603 // The FP is only available if there is no dynamic realignment. We
604 // don't know for sure yet whether we'll need that, so we guess based
605 // on whether there are any local variables that would trigger it.
606 unsigned StackAlign
= TFI
->getStackAlignment();
607 if (TFI
->hasFP(MF
) &&
608 !((MFI
.getLocalFrameMaxAlign() > StackAlign
) && canRealignStack(MF
))) {
609 if (isFrameOffsetLegal(MI
, getFrameRegister(MF
), FPOffset
))
612 // If we can reference via the stack pointer, try that.
613 // FIXME: This (and the code that resolves the references) can be improved
614 // to only disallow SP relative references in the live range of
615 // the VLA(s). In practice, it's unclear how much difference that
616 // would make, but it may be worth doing.
617 if (!MFI
.hasVarSizedObjects() && isFrameOffsetLegal(MI
, ARM::SP
, Offset
))
620 // The offset likely isn't legal, we want to allocate a virtual base register.
624 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
625 /// be a pointer to FrameIdx at the beginning of the basic block.
626 void ARMBaseRegisterInfo::
627 materializeFrameBaseRegister(MachineBasicBlock
*MBB
,
628 unsigned BaseReg
, int FrameIdx
,
629 int64_t Offset
) const {
630 ARMFunctionInfo
*AFI
= MBB
->getParent()->getInfo
<ARMFunctionInfo
>();
631 unsigned ADDriOpc
= !AFI
->isThumbFunction() ? ARM::ADDri
:
632 (AFI
->isThumb1OnlyFunction() ? ARM::tADDframe
: ARM::t2ADDri
);
634 MachineBasicBlock::iterator Ins
= MBB
->begin();
635 DebugLoc DL
; // Defaults to "unknown"
636 if (Ins
!= MBB
->end())
637 DL
= Ins
->getDebugLoc();
639 const MachineFunction
&MF
= *MBB
->getParent();
640 MachineRegisterInfo
&MRI
= MBB
->getParent()->getRegInfo();
641 const TargetInstrInfo
&TII
= *MF
.getSubtarget().getInstrInfo();
642 const MCInstrDesc
&MCID
= TII
.get(ADDriOpc
);
643 MRI
.constrainRegClass(BaseReg
, TII
.getRegClass(MCID
, 0, this, MF
));
645 MachineInstrBuilder MIB
= BuildMI(*MBB
, Ins
, DL
, MCID
, BaseReg
)
646 .addFrameIndex(FrameIdx
).addImm(Offset
);
648 if (!AFI
->isThumb1OnlyFunction())
649 MIB
.add(predOps(ARMCC::AL
)).add(condCodeOp());
652 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr
&MI
, unsigned BaseReg
,
653 int64_t Offset
) const {
654 MachineBasicBlock
&MBB
= *MI
.getParent();
655 MachineFunction
&MF
= *MBB
.getParent();
656 const ARMBaseInstrInfo
&TII
=
657 *static_cast<const ARMBaseInstrInfo
*>(MF
.getSubtarget().getInstrInfo());
658 ARMFunctionInfo
*AFI
= MF
.getInfo
<ARMFunctionInfo
>();
659 int Off
= Offset
; // ARM doesn't need the general 64-bit offsets
662 assert(!AFI
->isThumb1OnlyFunction() &&
663 "This resolveFrameIndex does not support Thumb1!");
665 while (!MI
.getOperand(i
).isFI()) {
667 assert(i
< MI
.getNumOperands() && "Instr doesn't have FrameIndex operand!");
670 if (!AFI
->isThumbFunction())
671 Done
= rewriteARMFrameIndex(MI
, i
, BaseReg
, Off
, TII
);
673 assert(AFI
->isThumb2Function());
674 Done
= rewriteT2FrameIndex(MI
, i
, BaseReg
, Off
, TII
, this);
676 assert(Done
&& "Unable to resolve frame index!");
680 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr
*MI
, unsigned BaseReg
,
681 int64_t Offset
) const {
682 const MCInstrDesc
&Desc
= MI
->getDesc();
683 unsigned AddrMode
= (Desc
.TSFlags
& ARMII::AddrModeMask
);
685 for (; !MI
->getOperand(i
).isFI(); ++i
)
686 assert(i
+1 < MI
->getNumOperands() && "Instr doesn't have FrameIndex operand!");
688 // AddrMode4 and AddrMode6 cannot handle any offset.
689 if (AddrMode
== ARMII::AddrMode4
|| AddrMode
== ARMII::AddrMode6
)
692 unsigned NumBits
= 0;
694 bool isSigned
= true;
696 case ARMII::AddrModeT2_i8
:
697 case ARMII::AddrModeT2_i12
:
698 // i8 supports only negative, and i12 supports only positive, so
699 // based on Offset sign, consider the appropriate instruction
708 case ARMII::AddrMode5
:
713 case ARMII::AddrMode_i12
:
714 case ARMII::AddrMode2
:
717 case ARMII::AddrMode3
:
720 case ARMII::AddrModeT1_s
:
721 NumBits
= (BaseReg
== ARM::SP
? 8 : 5);
726 llvm_unreachable("Unsupported addressing mode!");
729 Offset
+= getFrameIndexInstrOffset(MI
, i
);
730 // Make sure the offset is encodable for instructions that scale the
732 if ((Offset
& (Scale
-1)) != 0)
735 if (isSigned
&& Offset
< 0)
738 unsigned Mask
= (1 << NumBits
) - 1;
739 if ((unsigned)Offset
<= Mask
* Scale
)
746 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II
,
747 int SPAdj
, unsigned FIOperandNum
,
748 RegScavenger
*RS
) const {
749 MachineInstr
&MI
= *II
;
750 MachineBasicBlock
&MBB
= *MI
.getParent();
751 MachineFunction
&MF
= *MBB
.getParent();
752 const ARMBaseInstrInfo
&TII
=
753 *static_cast<const ARMBaseInstrInfo
*>(MF
.getSubtarget().getInstrInfo());
754 const ARMFrameLowering
*TFI
= getFrameLowering(MF
);
755 ARMFunctionInfo
*AFI
= MF
.getInfo
<ARMFunctionInfo
>();
756 assert(!AFI
->isThumb1OnlyFunction() &&
757 "This eliminateFrameIndex does not support Thumb1!");
758 int FrameIndex
= MI
.getOperand(FIOperandNum
).getIndex();
761 int Offset
= TFI
->ResolveFrameIndexReference(MF
, FrameIndex
, FrameReg
, SPAdj
);
763 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
764 // call frame setup/destroy instructions have already been eliminated. That
765 // means the stack pointer cannot be used to access the emergency spill slot
766 // when !hasReservedCallFrame().
768 if (RS
&& FrameReg
== ARM::SP
&& RS
->isScavengingFrameIndex(FrameIndex
)){
769 assert(TFI
->hasReservedCallFrame(MF
) &&
770 "Cannot use SP to access the emergency spill slot in "
771 "functions without a reserved call frame");
772 assert(!MF
.getFrameInfo().hasVarSizedObjects() &&
773 "Cannot use SP to access the emergency spill slot in "
774 "functions with variable sized frame objects");
778 assert(!MI
.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
780 // Modify MI as necessary to handle as much of 'Offset' as possible
782 if (!AFI
->isThumbFunction())
783 Done
= rewriteARMFrameIndex(MI
, FIOperandNum
, FrameReg
, Offset
, TII
);
785 assert(AFI
->isThumb2Function());
786 Done
= rewriteT2FrameIndex(MI
, FIOperandNum
, FrameReg
, Offset
, TII
, this);
791 // If we get here, the immediate doesn't fit into the instruction. We folded
792 // as much as possible above, handle the rest, providing a register that is
796 (MI
.getDesc().TSFlags
& ARMII::AddrModeMask
) == ARMII::AddrMode4
||
797 (MI
.getDesc().TSFlags
& ARMII::AddrModeMask
) == ARMII::AddrMode6
||
798 (MI
.getDesc().TSFlags
& ARMII::AddrModeMask
) == ARMII::AddrModeT2_i7
||
799 (MI
.getDesc().TSFlags
& ARMII::AddrModeMask
) == ARMII::AddrModeT2_i7s2
||
800 (MI
.getDesc().TSFlags
& ARMII::AddrModeMask
) ==
801 ARMII::AddrModeT2_i7s4
) &&
802 "This code isn't needed if offset already handled!");
804 unsigned ScratchReg
= 0;
805 int PIdx
= MI
.findFirstPredOperandIdx();
806 ARMCC::CondCodes Pred
= (PIdx
== -1)
807 ? ARMCC::AL
: (ARMCC::CondCodes
)MI
.getOperand(PIdx
).getImm();
808 Register PredReg
= (PIdx
== -1) ? Register() : MI
.getOperand(PIdx
+1).getReg();
810 const MCInstrDesc
&MCID
= MI
.getDesc();
811 const TargetRegisterClass
*RegClass
=
812 TII
.getRegClass(MCID
, FIOperandNum
, this, *MI
.getParent()->getParent());
815 (Register::isVirtualRegister(FrameReg
) || RegClass
->contains(FrameReg
)))
816 // Must be addrmode4/6.
817 MI
.getOperand(FIOperandNum
).ChangeToRegister(FrameReg
, false, false, false);
819 ScratchReg
= MF
.getRegInfo().createVirtualRegister(RegClass
);
820 if (!AFI
->isThumbFunction())
821 emitARMRegPlusImmediate(MBB
, II
, MI
.getDebugLoc(), ScratchReg
, FrameReg
,
822 Offset
, Pred
, PredReg
, TII
);
824 assert(AFI
->isThumb2Function());
825 emitT2RegPlusImmediate(MBB
, II
, MI
.getDebugLoc(), ScratchReg
, FrameReg
,
826 Offset
, Pred
, PredReg
, TII
);
828 // Update the original instruction to use the scratch register.
829 MI
.getOperand(FIOperandNum
).ChangeToRegister(ScratchReg
, false, false,true);
833 bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr
*MI
,
834 const TargetRegisterClass
*SrcRC
,
836 const TargetRegisterClass
*DstRC
,
838 const TargetRegisterClass
*NewRC
,
839 LiveIntervals
&LIS
) const {
840 auto MBB
= MI
->getParent();
841 auto MF
= MBB
->getParent();
842 const MachineRegisterInfo
&MRI
= MF
->getRegInfo();
843 // If not copying into a sub-register this should be ok because we shouldn't
844 // need to split the reg.
847 // Small registers don't frequently cause a problem, so we can coalesce them.
848 if (getRegSizeInBits(*NewRC
) < 256 && getRegSizeInBits(*DstRC
) < 256 &&
849 getRegSizeInBits(*SrcRC
) < 256)
853 MRI
.getTargetRegisterInfo()->getRegClassWeight(NewRC
);
855 MRI
.getTargetRegisterInfo()->getRegClassWeight(SrcRC
);
857 MRI
.getTargetRegisterInfo()->getRegClassWeight(DstRC
);
858 // If the source register class is more expensive than the destination, the
859 // coalescing is probably profitable.
860 if (SrcRCWeight
.RegWeight
> NewRCWeight
.RegWeight
)
862 if (DstRCWeight
.RegWeight
> NewRCWeight
.RegWeight
)
865 // If the register allocator isn't constrained, we can always allow coalescing
866 // unfortunately we don't know yet if we will be constrained.
867 // The goal of this heuristic is to restrict how many expensive registers
868 // we allow to coalesce in a given basic block.
869 auto AFI
= MF
->getInfo
<ARMFunctionInfo
>();
870 auto It
= AFI
->getCoalescedWeight(MBB
);
872 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
873 << It
->second
<< "\n");
874 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
875 << NewRCWeight
.RegWeight
<< "\n");
877 // This number is the largest round number that which meets the criteria:
878 // (1) addresses PR18825
879 // (2) generates better code in some test cases (like vldm-shed-a9.ll)
880 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
881 // In practice the SizeMultiplier will only factor in for straight line code
882 // that uses a lot of NEON vectors, which isn't terribly common.
883 unsigned SizeMultiplier
= MBB
->size()/100;
884 SizeMultiplier
= SizeMultiplier
? SizeMultiplier
: 1;
885 if (It
->second
< NewRCWeight
.WeightLimit
* SizeMultiplier
) {
886 It
->second
+= NewRCWeight
.RegWeight
;