lib/Target/ARM/ARMFeatures.h

   1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the code shared between ARM CodeGen and ARM MC
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_ARM_ARMFEATURES_H
  14 #define LLVM_LIB_TARGET_ARM_ARMFEATURES_H
  15
  16 #include "MCTargetDesc/ARMMCTargetDesc.h"
  17
  18 namespace llvm {
  19
  20 template<typename InstrType> // could be MachineInstr or MCInst
  21 bool IsCPSRDead(const InstrType *Instr);
  22
  23 template<typename InstrType> // could be MachineInstr or MCInst
  24 inline bool isV8EligibleForIT(const InstrType *Instr) {
  25   switch (Instr->getOpcode()) {
  26   default:
  27     return false;
  28   case ARM::tADC:
  29   case ARM::tADDi3:
  30   case ARM::tADDi8:
  31   case ARM::tADDrr:
  32   case ARM::tAND:
  33   case ARM::tASRri:
  34   case ARM::tASRrr:
  35   case ARM::tBIC:
  36   case ARM::tEOR:
  37   case ARM::tLSLri:
  38   case ARM::tLSLrr:
  39   case ARM::tLSRri:
  40   case ARM::tLSRrr:
  41   case ARM::tMOVi8:
  42   case ARM::tMUL:
  43   case ARM::tMVN:
  44   case ARM::tORR:
  45   case ARM::tROR:
  46   case ARM::tRSB:
  47   case ARM::tSBC:
  48   case ARM::tSUBi3:
  49   case ARM::tSUBi8:
  50   case ARM::tSUBrr:
  51     // Outside of an IT block, these set CPSR.
  52     return IsCPSRDead(Instr);
  53   case ARM::tADDrSPi:
  54   case ARM::tCMNz:
  55   case ARM::tCMPi8:
  56   case ARM::tCMPr:
  57   case ARM::tLDRBi:
  58   case ARM::tLDRBr:
  59   case ARM::tLDRHi:
  60   case ARM::tLDRHr:
  61   case ARM::tLDRSB:
  62   case ARM::tLDRSH:
  63   case ARM::tLDRi:
  64   case ARM::tLDRr:
  65   case ARM::tLDRspi:
  66   case ARM::tSTRBi:
  67   case ARM::tSTRBr:
  68   case ARM::tSTRHi:
  69   case ARM::tSTRHr:
  70   case ARM::tSTRi:
  71   case ARM::tSTRr:
  72   case ARM::tSTRspi:
  73   case ARM::tTST:
  74     return true;
  75 // there are some "conditionally deprecated" opcodes
  76   case ARM::tADDspr:
  77   case ARM::tBLXr:
  78     return Instr->getOperand(2).getReg() != ARM::PC;
  79   // ADD PC, SP and BLX PC were always unpredictable,
  80   // now on top of it they're deprecated
  81   case ARM::tADDrSP:
  82   case ARM::tBX:
  83     return Instr->getOperand(0).getReg() != ARM::PC;
  84   case ARM::tADDhirr:
  85     return Instr->getOperand(0).getReg() != ARM::PC &&
  86            Instr->getOperand(2).getReg() != ARM::PC;
  87   case ARM::tCMPhir:
  88   case ARM::tMOVr:
  89     return Instr->getOperand(0).getReg() != ARM::PC &&
  90            Instr->getOperand(1).getReg() != ARM::PC;
  91   }
  92 }
  93
  94 }
  95
  96 #endif