[InstCombine] Signed saturation tests. NFC
[llvm-complete.git] / lib / Target / ARM / AsmParser / ARMAsmParser.cpp
blobd2c355c1da75a2435af4b2753ddaf5cca348a669
1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #include "ARMFeatures.h"
10 #include "ARMBaseInstrInfo.h"
11 #include "Utils/ARMBaseInfo.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMBaseInfo.h"
14 #include "MCTargetDesc/ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "MCTargetDesc/ARMMCTargetDesc.h"
17 #include "TargetInfo/ARMTargetInfo.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringMap.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/MC/MCInstrDesc.h"
33 #include "llvm/MC/MCInstrInfo.h"
34 #include "llvm/MC/MCObjectFileInfo.h"
35 #include "llvm/MC/MCParser/MCAsmLexer.h"
36 #include "llvm/MC/MCParser/MCAsmParser.h"
37 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
38 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
39 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
40 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
41 #include "llvm/MC/MCRegisterInfo.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSubtargetInfo.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/MC/SubtargetFeature.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/ARMEHABI.h"
49 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Compiler.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Support/SMLoc.h"
55 #include "llvm/Support/TargetParser.h"
56 #include "llvm/Support/TargetRegistry.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include <algorithm>
59 #include <cassert>
60 #include <cstddef>
61 #include <cstdint>
62 #include <iterator>
63 #include <limits>
64 #include <memory>
65 #include <string>
66 #include <utility>
67 #include <vector>
69 #define DEBUG_TYPE "asm-parser"
71 using namespace llvm;
73 namespace llvm {
74 extern const MCInstrDesc ARMInsts[];
75 } // end namespace llvm
77 namespace {
79 enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
81 static cl::opt<ImplicitItModeTy> ImplicitItMode(
82 "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
83 cl::desc("Allow conditional instructions outdside of an IT block"),
84 cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
85 "Accept in both ISAs, emit implicit ITs in Thumb"),
86 clEnumValN(ImplicitItModeTy::Never, "never",
87 "Warn in ARM, reject in Thumb"),
88 clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
89 "Accept in ARM, reject in Thumb"),
90 clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
91 "Warn in ARM, emit implicit ITs in Thumb")));
93 static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
94 cl::init(false));
96 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
98 static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) {
99 // Position==0 means we're not in an IT block at all. Position==1
100 // means we want the first state bit, which is always 0 (Then).
101 // Position==2 means we want the second state bit, stored at bit 3
102 // of Mask, and so on downwards. So (5 - Position) will shift the
103 // right bit down to bit 0, including the always-0 bit at bit 4 for
104 // the mandatory initial Then.
105 return (Mask >> (5 - Position) & 1);
108 class UnwindContext {
109 using Locs = SmallVector<SMLoc, 4>;
111 MCAsmParser &Parser;
112 Locs FnStartLocs;
113 Locs CantUnwindLocs;
114 Locs PersonalityLocs;
115 Locs PersonalityIndexLocs;
116 Locs HandlerDataLocs;
117 int FPReg;
119 public:
120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
122 bool hasFnStart() const { return !FnStartLocs.empty(); }
123 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
124 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
126 bool hasPersonality() const {
127 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
130 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
131 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
132 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
133 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
134 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
136 void saveFPReg(int Reg) { FPReg = Reg; }
137 int getFPReg() const { return FPReg; }
139 void emitFnStartLocNotes() const {
140 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
141 FI != FE; ++FI)
142 Parser.Note(*FI, ".fnstart was specified here");
145 void emitCantUnwindLocNotes() const {
146 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
147 UE = CantUnwindLocs.end(); UI != UE; ++UI)
148 Parser.Note(*UI, ".cantunwind was specified here");
151 void emitHandlerDataLocNotes() const {
152 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
153 HE = HandlerDataLocs.end(); HI != HE; ++HI)
154 Parser.Note(*HI, ".handlerdata was specified here");
157 void emitPersonalityLocNotes() const {
158 for (Locs::const_iterator PI = PersonalityLocs.begin(),
159 PE = PersonalityLocs.end(),
160 PII = PersonalityIndexLocs.begin(),
161 PIE = PersonalityIndexLocs.end();
162 PI != PE || PII != PIE;) {
163 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
164 Parser.Note(*PI++, ".personality was specified here");
165 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
166 Parser.Note(*PII++, ".personalityindex was specified here");
167 else
168 llvm_unreachable(".personality and .personalityindex cannot be "
169 "at the same location");
173 void reset() {
174 FnStartLocs = Locs();
175 CantUnwindLocs = Locs();
176 PersonalityLocs = Locs();
177 HandlerDataLocs = Locs();
178 PersonalityIndexLocs = Locs();
179 FPReg = ARM::SP;
184 class ARMAsmParser : public MCTargetAsmParser {
185 const MCRegisterInfo *MRI;
186 UnwindContext UC;
188 ARMTargetStreamer &getTargetStreamer() {
189 assert(getParser().getStreamer().getTargetStreamer() &&
190 "do not have a target streamer");
191 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
192 return static_cast<ARMTargetStreamer &>(TS);
195 // Map of register aliases registers via the .req directive.
196 StringMap<unsigned> RegisterReqs;
198 bool NextSymbolIsThumb;
200 bool useImplicitITThumb() const {
201 return ImplicitItMode == ImplicitItModeTy::Always ||
202 ImplicitItMode == ImplicitItModeTy::ThumbOnly;
205 bool useImplicitITARM() const {
206 return ImplicitItMode == ImplicitItModeTy::Always ||
207 ImplicitItMode == ImplicitItModeTy::ARMOnly;
210 struct {
211 ARMCC::CondCodes Cond; // Condition for IT block.
212 unsigned Mask:4; // Condition mask for instructions.
213 // Starting at first 1 (from lsb).
214 // '1' condition as indicated in IT.
215 // '0' inverse of condition (else).
216 // Count of instructions in IT block is
217 // 4 - trailingzeroes(mask)
218 // Note that this does not have the same encoding
219 // as in the IT instruction, which also depends
220 // on the low bit of the condition code.
222 unsigned CurPosition; // Current position in parsing of IT
223 // block. In range [0,4], with 0 being the IT
224 // instruction itself. Initialized according to
225 // count of instructions in block. ~0U if no
226 // active IT block.
228 bool IsExplicit; // true - The IT instruction was present in the
229 // input, we should not modify it.
230 // false - The IT instruction was added
231 // implicitly, we can extend it if that
232 // would be legal.
233 } ITState;
235 SmallVector<MCInst, 4> PendingConditionalInsts;
237 void flushPendingInstructions(MCStreamer &Out) override {
238 if (!inImplicitITBlock()) {
239 assert(PendingConditionalInsts.size() == 0);
240 return;
243 // Emit the IT instruction
244 MCInst ITInst;
245 ITInst.setOpcode(ARM::t2IT);
246 ITInst.addOperand(MCOperand::createImm(ITState.Cond));
247 ITInst.addOperand(MCOperand::createImm(ITState.Mask));
248 Out.EmitInstruction(ITInst, getSTI());
250 // Emit the conditonal instructions
251 assert(PendingConditionalInsts.size() <= 4);
252 for (const MCInst &Inst : PendingConditionalInsts) {
253 Out.EmitInstruction(Inst, getSTI());
255 PendingConditionalInsts.clear();
257 // Clear the IT state
258 ITState.Mask = 0;
259 ITState.CurPosition = ~0U;
262 bool inITBlock() { return ITState.CurPosition != ~0U; }
263 bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
264 bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
266 bool lastInITBlock() {
267 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
270 void forwardITPosition() {
271 if (!inITBlock()) return;
272 // Move to the next instruction in the IT block, if there is one. If not,
273 // mark the block as done, except for implicit IT blocks, which we leave
274 // open until we find an instruction that can't be added to it.
275 unsigned TZ = countTrailingZeros(ITState.Mask);
276 if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
277 ITState.CurPosition = ~0U; // Done with the IT block after this.
280 // Rewind the state of the current IT block, removing the last slot from it.
281 void rewindImplicitITPosition() {
282 assert(inImplicitITBlock());
283 assert(ITState.CurPosition > 1);
284 ITState.CurPosition--;
285 unsigned TZ = countTrailingZeros(ITState.Mask);
286 unsigned NewMask = 0;
287 NewMask |= ITState.Mask & (0xC << TZ);
288 NewMask |= 0x2 << TZ;
289 ITState.Mask = NewMask;
292 // Rewind the state of the current IT block, removing the last slot from it.
293 // If we were at the first slot, this closes the IT block.
294 void discardImplicitITBlock() {
295 assert(inImplicitITBlock());
296 assert(ITState.CurPosition == 1);
297 ITState.CurPosition = ~0U;
300 // Return the low-subreg of a given Q register.
301 unsigned getDRegFromQReg(unsigned QReg) const {
302 return MRI->getSubReg(QReg, ARM::dsub_0);
305 // Get the condition code corresponding to the current IT block slot.
306 ARMCC::CondCodes currentITCond() {
307 unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition);
308 return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond;
311 // Invert the condition of the current IT block slot without changing any
312 // other slots in the same block.
313 void invertCurrentITCondition() {
314 if (ITState.CurPosition == 1) {
315 ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
316 } else {
317 ITState.Mask ^= 1 << (5 - ITState.CurPosition);
321 // Returns true if the current IT block is full (all 4 slots used).
322 bool isITBlockFull() {
323 return inITBlock() && (ITState.Mask & 1);
326 // Extend the current implicit IT block to have one more slot with the given
327 // condition code.
328 void extendImplicitITBlock(ARMCC::CondCodes Cond) {
329 assert(inImplicitITBlock());
330 assert(!isITBlockFull());
331 assert(Cond == ITState.Cond ||
332 Cond == ARMCC::getOppositeCondition(ITState.Cond));
333 unsigned TZ = countTrailingZeros(ITState.Mask);
334 unsigned NewMask = 0;
335 // Keep any existing condition bits.
336 NewMask |= ITState.Mask & (0xE << TZ);
337 // Insert the new condition bit.
338 NewMask |= (Cond != ITState.Cond) << TZ;
339 // Move the trailing 1 down one bit.
340 NewMask |= 1 << (TZ - 1);
341 ITState.Mask = NewMask;
344 // Create a new implicit IT block with a dummy condition code.
345 void startImplicitITBlock() {
346 assert(!inITBlock());
347 ITState.Cond = ARMCC::AL;
348 ITState.Mask = 8;
349 ITState.CurPosition = 1;
350 ITState.IsExplicit = false;
353 // Create a new explicit IT block with the given condition and mask.
354 // The mask should be in the format used in ARMOperand and
355 // MCOperand, with a 1 implying 'e', regardless of the low bit of
356 // the condition.
357 void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
358 assert(!inITBlock());
359 ITState.Cond = Cond;
360 ITState.Mask = Mask;
361 ITState.CurPosition = 0;
362 ITState.IsExplicit = true;
365 struct {
366 unsigned Mask : 4;
367 unsigned CurPosition;
368 } VPTState;
369 bool inVPTBlock() { return VPTState.CurPosition != ~0U; }
370 void forwardVPTPosition() {
371 if (!inVPTBlock()) return;
372 unsigned TZ = countTrailingZeros(VPTState.Mask);
373 if (++VPTState.CurPosition == 5 - TZ)
374 VPTState.CurPosition = ~0U;
377 void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
378 return getParser().Note(L, Msg, Range);
381 bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
382 return getParser().Warning(L, Msg, Range);
385 bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
386 return getParser().Error(L, Msg, Range);
389 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
390 unsigned ListNo, bool IsARPop = false);
391 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
392 unsigned ListNo);
394 int tryParseRegister();
395 bool tryParseRegisterWithWriteBack(OperandVector &);
396 int tryParseShiftRegister(OperandVector &);
397 bool parseRegisterList(OperandVector &, bool EnforceOrder = true);
398 bool parseMemory(OperandVector &);
399 bool parseOperand(OperandVector &, StringRef Mnemonic);
400 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
401 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
402 unsigned &ShiftAmount);
403 bool parseLiteralValues(unsigned Size, SMLoc L);
404 bool parseDirectiveThumb(SMLoc L);
405 bool parseDirectiveARM(SMLoc L);
406 bool parseDirectiveThumbFunc(SMLoc L);
407 bool parseDirectiveCode(SMLoc L);
408 bool parseDirectiveSyntax(SMLoc L);
409 bool parseDirectiveReq(StringRef Name, SMLoc L);
410 bool parseDirectiveUnreq(SMLoc L);
411 bool parseDirectiveArch(SMLoc L);
412 bool parseDirectiveEabiAttr(SMLoc L);
413 bool parseDirectiveCPU(SMLoc L);
414 bool parseDirectiveFPU(SMLoc L);
415 bool parseDirectiveFnStart(SMLoc L);
416 bool parseDirectiveFnEnd(SMLoc L);
417 bool parseDirectiveCantUnwind(SMLoc L);
418 bool parseDirectivePersonality(SMLoc L);
419 bool parseDirectiveHandlerData(SMLoc L);
420 bool parseDirectiveSetFP(SMLoc L);
421 bool parseDirectivePad(SMLoc L);
422 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
423 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
424 bool parseDirectiveLtorg(SMLoc L);
425 bool parseDirectiveEven(SMLoc L);
426 bool parseDirectivePersonalityIndex(SMLoc L);
427 bool parseDirectiveUnwindRaw(SMLoc L);
428 bool parseDirectiveTLSDescSeq(SMLoc L);
429 bool parseDirectiveMovSP(SMLoc L);
430 bool parseDirectiveObjectArch(SMLoc L);
431 bool parseDirectiveArchExtension(SMLoc L);
432 bool parseDirectiveAlign(SMLoc L);
433 bool parseDirectiveThumbSet(SMLoc L);
435 bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken);
436 StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken,
437 unsigned &PredicationCode,
438 unsigned &VPTPredicationCode, bool &CarrySetting,
439 unsigned &ProcessorIMod, StringRef &ITMask);
440 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken,
441 StringRef FullInst, bool &CanAcceptCarrySet,
442 bool &CanAcceptPredicationCode,
443 bool &CanAcceptVPTPredicationCode);
445 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
446 OperandVector &Operands);
447 bool isThumb() const {
448 // FIXME: Can tablegen auto-generate this?
449 return getSTI().getFeatureBits()[ARM::ModeThumb];
452 bool isThumbOne() const {
453 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
456 bool isThumbTwo() const {
457 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
460 bool hasThumb() const {
461 return getSTI().getFeatureBits()[ARM::HasV4TOps];
464 bool hasThumb2() const {
465 return getSTI().getFeatureBits()[ARM::FeatureThumb2];
468 bool hasV6Ops() const {
469 return getSTI().getFeatureBits()[ARM::HasV6Ops];
472 bool hasV6T2Ops() const {
473 return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
476 bool hasV6MOps() const {
477 return getSTI().getFeatureBits()[ARM::HasV6MOps];
480 bool hasV7Ops() const {
481 return getSTI().getFeatureBits()[ARM::HasV7Ops];
484 bool hasV8Ops() const {
485 return getSTI().getFeatureBits()[ARM::HasV8Ops];
488 bool hasV8MBaseline() const {
489 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
492 bool hasV8MMainline() const {
493 return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
495 bool hasV8_1MMainline() const {
496 return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
498 bool hasMVE() const {
499 return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
501 bool hasMVEFloat() const {
502 return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
504 bool has8MSecExt() const {
505 return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
508 bool hasARM() const {
509 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
512 bool hasDSP() const {
513 return getSTI().getFeatureBits()[ARM::FeatureDSP];
516 bool hasD32() const {
517 return getSTI().getFeatureBits()[ARM::FeatureD32];
520 bool hasV8_1aOps() const {
521 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
524 bool hasRAS() const {
525 return getSTI().getFeatureBits()[ARM::FeatureRAS];
528 void SwitchMode() {
529 MCSubtargetInfo &STI = copySTI();
530 auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
531 setAvailableFeatures(FB);
534 void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
536 bool isMClass() const {
537 return getSTI().getFeatureBits()[ARM::FeatureMClass];
540 /// @name Auto-generated Match Functions
541 /// {
543 #define GET_ASSEMBLER_HEADER
544 #include "ARMGenAsmMatcher.inc"
546 /// }
548 OperandMatchResultTy parseITCondCode(OperandVector &);
549 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
550 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
551 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
552 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
553 OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
554 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
555 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
556 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
557 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
558 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
559 int High);
560 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
561 return parsePKHImm(O, "lsl", 0, 31);
563 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
564 return parsePKHImm(O, "asr", 1, 32);
566 OperandMatchResultTy parseSetEndImm(OperandVector &);
567 OperandMatchResultTy parseShifterImm(OperandVector &);
568 OperandMatchResultTy parseRotImm(OperandVector &);
569 OperandMatchResultTy parseModImm(OperandVector &);
570 OperandMatchResultTy parseBitfield(OperandVector &);
571 OperandMatchResultTy parsePostIdxReg(OperandVector &);
572 OperandMatchResultTy parseAM3Offset(OperandVector &);
573 OperandMatchResultTy parseFPImm(OperandVector &);
574 OperandMatchResultTy parseVectorList(OperandVector &);
575 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
576 SMLoc &EndLoc);
578 // Asm Match Converter Methods
579 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
580 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
581 void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &);
583 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
584 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
585 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
586 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
587 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
588 bool isITBlockTerminator(MCInst &Inst) const;
589 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
590 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
591 bool Load, bool ARMMode, bool Writeback);
593 public:
594 enum ARMMatchResultTy {
595 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
596 Match_RequiresNotITBlock,
597 Match_RequiresV6,
598 Match_RequiresThumb2,
599 Match_RequiresV8,
600 Match_RequiresFlagSetting,
601 #define GET_OPERAND_DIAGNOSTIC_TYPES
602 #include "ARMGenAsmMatcher.inc"
606 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
607 const MCInstrInfo &MII, const MCTargetOptions &Options)
608 : MCTargetAsmParser(Options, STI, MII), UC(Parser) {
609 MCAsmParserExtension::Initialize(Parser);
611 // Cache the MCRegisterInfo.
612 MRI = getContext().getRegisterInfo();
614 // Initialize the set of available features.
615 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
617 // Add build attributes based on the selected target.
618 if (AddBuildAttributes)
619 getTargetStreamer().emitTargetAttributes(STI);
621 // Not in an ITBlock to start with.
622 ITState.CurPosition = ~0U;
624 VPTState.CurPosition = ~0U;
626 NextSymbolIsThumb = false;
629 // Implementation of the MCTargetAsmParser interface:
630 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
631 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
632 SMLoc NameLoc, OperandVector &Operands) override;
633 bool ParseDirective(AsmToken DirectiveID) override;
635 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
636 unsigned Kind) override;
637 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
639 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
640 OperandVector &Operands, MCStreamer &Out,
641 uint64_t &ErrorInfo,
642 bool MatchingInlineAsm) override;
643 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
644 SmallVectorImpl<NearMissInfo> &NearMisses,
645 bool MatchingInlineAsm, bool &EmitInITBlock,
646 MCStreamer &Out);
648 struct NearMissMessage {
649 SMLoc Loc;
650 SmallString<128> Message;
653 const char *getCustomOperandDiag(ARMMatchResultTy MatchError);
655 void FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
656 SmallVectorImpl<NearMissMessage> &NearMissesOut,
657 SMLoc IDLoc, OperandVector &Operands);
658 void ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses, SMLoc IDLoc,
659 OperandVector &Operands);
661 void doBeforeLabelEmit(MCSymbol *Symbol) override;
663 void onLabelParsed(MCSymbol *Symbol) override;
666 /// ARMOperand - Instances of this class represent a parsed ARM machine
667 /// operand.
668 class ARMOperand : public MCParsedAsmOperand {
669 enum KindTy {
670 k_CondCode,
671 k_VPTPred,
672 k_CCOut,
673 k_ITCondMask,
674 k_CoprocNum,
675 k_CoprocReg,
676 k_CoprocOption,
677 k_Immediate,
678 k_MemBarrierOpt,
679 k_InstSyncBarrierOpt,
680 k_TraceSyncBarrierOpt,
681 k_Memory,
682 k_PostIndexRegister,
683 k_MSRMask,
684 k_BankedReg,
685 k_ProcIFlags,
686 k_VectorIndex,
687 k_Register,
688 k_RegisterList,
689 k_RegisterListWithAPSR,
690 k_DPRRegisterList,
691 k_SPRRegisterList,
692 k_FPSRegisterListWithVPR,
693 k_FPDRegisterListWithVPR,
694 k_VectorList,
695 k_VectorListAllLanes,
696 k_VectorListIndexed,
697 k_ShiftedRegister,
698 k_ShiftedImmediate,
699 k_ShifterImmediate,
700 k_RotateImmediate,
701 k_ModifiedImmediate,
702 k_ConstantPoolImmediate,
703 k_BitfieldDescriptor,
704 k_Token,
705 } Kind;
707 SMLoc StartLoc, EndLoc, AlignmentLoc;
708 SmallVector<unsigned, 8> Registers;
710 struct CCOp {
711 ARMCC::CondCodes Val;
714 struct VCCOp {
715 ARMVCC::VPTCodes Val;
718 struct CopOp {
719 unsigned Val;
722 struct CoprocOptionOp {
723 unsigned Val;
726 struct ITMaskOp {
727 unsigned Mask:4;
730 struct MBOptOp {
731 ARM_MB::MemBOpt Val;
734 struct ISBOptOp {
735 ARM_ISB::InstSyncBOpt Val;
738 struct TSBOptOp {
739 ARM_TSB::TraceSyncBOpt Val;
742 struct IFlagsOp {
743 ARM_PROC::IFlags Val;
746 struct MMaskOp {
747 unsigned Val;
750 struct BankedRegOp {
751 unsigned Val;
754 struct TokOp {
755 const char *Data;
756 unsigned Length;
759 struct RegOp {
760 unsigned RegNum;
763 // A vector register list is a sequential list of 1 to 4 registers.
764 struct VectorListOp {
765 unsigned RegNum;
766 unsigned Count;
767 unsigned LaneIndex;
768 bool isDoubleSpaced;
771 struct VectorIndexOp {
772 unsigned Val;
775 struct ImmOp {
776 const MCExpr *Val;
779 /// Combined record for all forms of ARM address expressions.
780 struct MemoryOp {
781 unsigned BaseRegNum;
782 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
783 // was specified.
784 const MCConstantExpr *OffsetImm; // Offset immediate value
785 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
786 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
787 unsigned ShiftImm; // shift for OffsetReg.
788 unsigned Alignment; // 0 = no alignment specified
789 // n = alignment in bytes (2, 4, 8, 16, or 32)
790 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
793 struct PostIdxRegOp {
794 unsigned RegNum;
795 bool isAdd;
796 ARM_AM::ShiftOpc ShiftTy;
797 unsigned ShiftImm;
800 struct ShifterImmOp {
801 bool isASR;
802 unsigned Imm;
805 struct RegShiftedRegOp {
806 ARM_AM::ShiftOpc ShiftTy;
807 unsigned SrcReg;
808 unsigned ShiftReg;
809 unsigned ShiftImm;
812 struct RegShiftedImmOp {
813 ARM_AM::ShiftOpc ShiftTy;
814 unsigned SrcReg;
815 unsigned ShiftImm;
818 struct RotImmOp {
819 unsigned Imm;
822 struct ModImmOp {
823 unsigned Bits;
824 unsigned Rot;
827 struct BitfieldOp {
828 unsigned LSB;
829 unsigned Width;
832 union {
833 struct CCOp CC;
834 struct VCCOp VCC;
835 struct CopOp Cop;
836 struct CoprocOptionOp CoprocOption;
837 struct MBOptOp MBOpt;
838 struct ISBOptOp ISBOpt;
839 struct TSBOptOp TSBOpt;
840 struct ITMaskOp ITMask;
841 struct IFlagsOp IFlags;
842 struct MMaskOp MMask;
843 struct BankedRegOp BankedReg;
844 struct TokOp Tok;
845 struct RegOp Reg;
846 struct VectorListOp VectorList;
847 struct VectorIndexOp VectorIndex;
848 struct ImmOp Imm;
849 struct MemoryOp Memory;
850 struct PostIdxRegOp PostIdxReg;
851 struct ShifterImmOp ShifterImm;
852 struct RegShiftedRegOp RegShiftedReg;
853 struct RegShiftedImmOp RegShiftedImm;
854 struct RotImmOp RotImm;
855 struct ModImmOp ModImm;
856 struct BitfieldOp Bitfield;
859 public:
860 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
862 /// getStartLoc - Get the location of the first token of this operand.
863 SMLoc getStartLoc() const override { return StartLoc; }
865 /// getEndLoc - Get the location of the last token of this operand.
866 SMLoc getEndLoc() const override { return EndLoc; }
868 /// getLocRange - Get the range between the first and last token of this
869 /// operand.
870 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
872 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
873 SMLoc getAlignmentLoc() const {
874 assert(Kind == k_Memory && "Invalid access!");
875 return AlignmentLoc;
878 ARMCC::CondCodes getCondCode() const {
879 assert(Kind == k_CondCode && "Invalid access!");
880 return CC.Val;
883 ARMVCC::VPTCodes getVPTPred() const {
884 assert(isVPTPred() && "Invalid access!");
885 return VCC.Val;
888 unsigned getCoproc() const {
889 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
890 return Cop.Val;
893 StringRef getToken() const {
894 assert(Kind == k_Token && "Invalid access!");
895 return StringRef(Tok.Data, Tok.Length);
898 unsigned getReg() const override {
899 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
900 return Reg.RegNum;
903 const SmallVectorImpl<unsigned> &getRegList() const {
904 assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR ||
905 Kind == k_DPRRegisterList || Kind == k_SPRRegisterList ||
906 Kind == k_FPSRegisterListWithVPR ||
907 Kind == k_FPDRegisterListWithVPR) &&
908 "Invalid access!");
909 return Registers;
912 const MCExpr *getImm() const {
913 assert(isImm() && "Invalid access!");
914 return Imm.Val;
917 const MCExpr *getConstantPoolImm() const {
918 assert(isConstantPoolImm() && "Invalid access!");
919 return Imm.Val;
922 unsigned getVectorIndex() const {
923 assert(Kind == k_VectorIndex && "Invalid access!");
924 return VectorIndex.Val;
927 ARM_MB::MemBOpt getMemBarrierOpt() const {
928 assert(Kind == k_MemBarrierOpt && "Invalid access!");
929 return MBOpt.Val;
932 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
933 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
934 return ISBOpt.Val;
937 ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const {
938 assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!");
939 return TSBOpt.Val;
942 ARM_PROC::IFlags getProcIFlags() const {
943 assert(Kind == k_ProcIFlags && "Invalid access!");
944 return IFlags.Val;
947 unsigned getMSRMask() const {
948 assert(Kind == k_MSRMask && "Invalid access!");
949 return MMask.Val;
952 unsigned getBankedReg() const {
953 assert(Kind == k_BankedReg && "Invalid access!");
954 return BankedReg.Val;
957 bool isCoprocNum() const { return Kind == k_CoprocNum; }
958 bool isCoprocReg() const { return Kind == k_CoprocReg; }
959 bool isCoprocOption() const { return Kind == k_CoprocOption; }
960 bool isCondCode() const { return Kind == k_CondCode; }
961 bool isVPTPred() const { return Kind == k_VPTPred; }
962 bool isCCOut() const { return Kind == k_CCOut; }
963 bool isITMask() const { return Kind == k_ITCondMask; }
964 bool isITCondCode() const { return Kind == k_CondCode; }
965 bool isImm() const override {
966 return Kind == k_Immediate;
969 bool isARMBranchTarget() const {
970 if (!isImm()) return false;
972 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
973 return CE->getValue() % 4 == 0;
974 return true;
978 bool isThumbBranchTarget() const {
979 if (!isImm()) return false;
981 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
982 return CE->getValue() % 2 == 0;
983 return true;
986 // checks whether this operand is an unsigned offset which fits is a field
987 // of specified width and scaled by a specific number of bits
988 template<unsigned width, unsigned scale>
989 bool isUnsignedOffset() const {
990 if (!isImm()) return false;
991 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
992 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
993 int64_t Val = CE->getValue();
994 int64_t Align = 1LL << scale;
995 int64_t Max = Align * ((1LL << width) - 1);
996 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
998 return false;
1001 // checks whether this operand is an signed offset which fits is a field
1002 // of specified width and scaled by a specific number of bits
1003 template<unsigned width, unsigned scale>
1004 bool isSignedOffset() const {
1005 if (!isImm()) return false;
1006 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1007 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1008 int64_t Val = CE->getValue();
1009 int64_t Align = 1LL << scale;
1010 int64_t Max = Align * ((1LL << (width-1)) - 1);
1011 int64_t Min = -Align * (1LL << (width-1));
1012 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
1014 return false;
1017 // checks whether this operand is an offset suitable for the LE /
1018 // LETP instructions in Arm v8.1M
1019 bool isLEOffset() const {
1020 if (!isImm()) return false;
1021 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1022 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
1023 int64_t Val = CE->getValue();
1024 return Val < 0 && Val >= -4094 && (Val & 1) == 0;
1026 return false;
1029 // checks whether this operand is a memory operand computed as an offset
1030 // applied to PC. the offset may have 8 bits of magnitude and is represented
1031 // with two bits of shift. textually it may be either [pc, #imm], #imm or
1032 // relocable expression...
1033 bool isThumbMemPC() const {
1034 int64_t Val = 0;
1035 if (isImm()) {
1036 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
1037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1038 if (!CE) return false;
1039 Val = CE->getValue();
1041 else if (isGPRMem()) {
1042 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
1043 if(Memory.BaseRegNum != ARM::PC) return false;
1044 Val = Memory.OffsetImm->getValue();
1046 else return false;
1047 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
1050 bool isFPImm() const {
1051 if (!isImm()) return false;
1052 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1053 if (!CE) return false;
1054 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1055 return Val != -1;
1058 template<int64_t N, int64_t M>
1059 bool isImmediate() const {
1060 if (!isImm()) return false;
1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062 if (!CE) return false;
1063 int64_t Value = CE->getValue();
1064 return Value >= N && Value <= M;
1067 template<int64_t N, int64_t M>
1068 bool isImmediateS4() const {
1069 if (!isImm()) return false;
1070 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1071 if (!CE) return false;
1072 int64_t Value = CE->getValue();
1073 return ((Value & 3) == 0) && Value >= N && Value <= M;
1075 template<int64_t N, int64_t M>
1076 bool isImmediateS2() const {
1077 if (!isImm()) return false;
1078 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1079 if (!CE) return false;
1080 int64_t Value = CE->getValue();
1081 return ((Value & 1) == 0) && Value >= N && Value <= M;
1083 bool isFBits16() const {
1084 return isImmediate<0, 17>();
1086 bool isFBits32() const {
1087 return isImmediate<1, 33>();
1089 bool isImm8s4() const {
1090 return isImmediateS4<-1020, 1020>();
1092 bool isImm7s4() const {
1093 return isImmediateS4<-508, 508>();
1095 bool isImm7Shift0() const {
1096 return isImmediate<-127, 127>();
1098 bool isImm7Shift1() const {
1099 return isImmediateS2<-255, 255>();
1101 bool isImm7Shift2() const {
1102 return isImmediateS4<-511, 511>();
1104 bool isImm7() const {
1105 return isImmediate<-127, 127>();
1107 bool isImm0_1020s4() const {
1108 return isImmediateS4<0, 1020>();
1110 bool isImm0_508s4() const {
1111 return isImmediateS4<0, 508>();
1113 bool isImm0_508s4Neg() const {
1114 if (!isImm()) return false;
1115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1116 if (!CE) return false;
1117 int64_t Value = -CE->getValue();
1118 // explicitly exclude zero. we want that to use the normal 0_508 version.
1119 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
1122 bool isImm0_4095Neg() const {
1123 if (!isImm()) return false;
1124 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1125 if (!CE) return false;
1126 // isImm0_4095Neg is used with 32-bit immediates only.
1127 // 32-bit immediates are zero extended to 64-bit when parsed,
1128 // thus simple -CE->getValue() results in a big negative number,
1129 // not a small positive number as intended
1130 if ((CE->getValue() >> 32) > 0) return false;
1131 uint32_t Value = -static_cast<uint32_t>(CE->getValue());
1132 return Value > 0 && Value < 4096;
1135 bool isImm0_7() const {
1136 return isImmediate<0, 7>();
1139 bool isImm1_16() const {
1140 return isImmediate<1, 16>();
1143 bool isImm1_32() const {
1144 return isImmediate<1, 32>();
1147 bool isImm8_255() const {
1148 return isImmediate<8, 255>();
1151 bool isImm256_65535Expr() const {
1152 if (!isImm()) return false;
1153 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1154 // If it's not a constant expression, it'll generate a fixup and be
1155 // handled later.
1156 if (!CE) return true;
1157 int64_t Value = CE->getValue();
1158 return Value >= 256 && Value < 65536;
1161 bool isImm0_65535Expr() const {
1162 if (!isImm()) return false;
1163 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1164 // If it's not a constant expression, it'll generate a fixup and be
1165 // handled later.
1166 if (!CE) return true;
1167 int64_t Value = CE->getValue();
1168 return Value >= 0 && Value < 65536;
1171 bool isImm24bit() const {
1172 return isImmediate<0, 0xffffff + 1>();
1175 bool isImmThumbSR() const {
1176 return isImmediate<1, 33>();
1179 template<int shift>
1180 bool isExpImmValue(uint64_t Value) const {
1181 uint64_t mask = (1 << shift) - 1;
1182 if ((Value & mask) != 0 || (Value >> shift) > 0xff)
1183 return false;
1184 return true;
1187 template<int shift>
1188 bool isExpImm() const {
1189 if (!isImm()) return false;
1190 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191 if (!CE) return false;
1193 return isExpImmValue<shift>(CE->getValue());
1196 template<int shift, int size>
1197 bool isInvertedExpImm() const {
1198 if (!isImm()) return false;
1199 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1200 if (!CE) return false;
1202 uint64_t OriginalValue = CE->getValue();
1203 uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1);
1204 return isExpImmValue<shift>(InvertedValue);
1207 bool isPKHLSLImm() const {
1208 return isImmediate<0, 32>();
1211 bool isPKHASRImm() const {
1212 return isImmediate<0, 33>();
1215 bool isAdrLabel() const {
1216 // If we have an immediate that's not a constant, treat it as a label
1217 // reference needing a fixup.
1218 if (isImm() && !isa<MCConstantExpr>(getImm()))
1219 return true;
1221 // If it is a constant, it must fit into a modified immediate encoding.
1222 if (!isImm()) return false;
1223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1224 if (!CE) return false;
1225 int64_t Value = CE->getValue();
1226 return (ARM_AM::getSOImmVal(Value) != -1 ||
1227 ARM_AM::getSOImmVal(-Value) != -1);
1230 bool isT2SOImm() const {
1231 // If we have an immediate that's not a constant, treat it as an expression
1232 // needing a fixup.
1233 if (isImm() && !isa<MCConstantExpr>(getImm())) {
1234 // We want to avoid matching :upper16: and :lower16: as we want these
1235 // expressions to match in isImm0_65535Expr()
1236 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
1237 return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
1238 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
1240 if (!isImm()) return false;
1241 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1242 if (!CE) return false;
1243 int64_t Value = CE->getValue();
1244 return ARM_AM::getT2SOImmVal(Value) != -1;
1247 bool isT2SOImmNot() const {
1248 if (!isImm()) return false;
1249 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1250 if (!CE) return false;
1251 int64_t Value = CE->getValue();
1252 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1253 ARM_AM::getT2SOImmVal(~Value) != -1;
1256 bool isT2SOImmNeg() const {
1257 if (!isImm()) return false;
1258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1259 if (!CE) return false;
1260 int64_t Value = CE->getValue();
1261 // Only use this when not representable as a plain so_imm.
1262 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1263 ARM_AM::getT2SOImmVal(-Value) != -1;
1266 bool isSetEndImm() const {
1267 if (!isImm()) return false;
1268 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1269 if (!CE) return false;
1270 int64_t Value = CE->getValue();
1271 return Value == 1 || Value == 0;
1274 bool isReg() const override { return Kind == k_Register; }
1275 bool isRegList() const { return Kind == k_RegisterList; }
1276 bool isRegListWithAPSR() const {
1277 return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList;
1279 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1280 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1281 bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; }
1282 bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; }
1283 bool isToken() const override { return Kind == k_Token; }
1284 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1285 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1286 bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
1287 bool isMem() const override {
1288 return isGPRMem() || isMVEMem();
1290 bool isMVEMem() const {
1291 if (Kind != k_Memory)
1292 return false;
1293 if (Memory.BaseRegNum &&
1294 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1295 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1296 return false;
1297 if (Memory.OffsetRegNum &&
1298 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1299 Memory.OffsetRegNum))
1300 return false;
1301 return true;
1303 bool isGPRMem() const {
1304 if (Kind != k_Memory)
1305 return false;
1306 if (Memory.BaseRegNum &&
1307 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum))
1308 return false;
1309 if (Memory.OffsetRegNum &&
1310 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum))
1311 return false;
1312 return true;
1314 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1315 bool isRegShiftedReg() const {
1316 return Kind == k_ShiftedRegister &&
1317 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1318 RegShiftedReg.SrcReg) &&
1319 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1320 RegShiftedReg.ShiftReg);
1322 bool isRegShiftedImm() const {
1323 return Kind == k_ShiftedImmediate &&
1324 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
1325 RegShiftedImm.SrcReg);
1327 bool isRotImm() const { return Kind == k_RotateImmediate; }
1329 template<unsigned Min, unsigned Max>
1330 bool isPowerTwoInRange() const {
1331 if (!isImm()) return false;
1332 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1333 if (!CE) return false;
1334 int64_t Value = CE->getValue();
1335 return Value > 0 && countPopulation((uint64_t)Value) == 1 &&
1336 Value >= Min && Value <= Max;
1338 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1340 bool isModImmNot() const {
1341 if (!isImm()) return false;
1342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1343 if (!CE) return false;
1344 int64_t Value = CE->getValue();
1345 return ARM_AM::getSOImmVal(~Value) != -1;
1348 bool isModImmNeg() const {
1349 if (!isImm()) return false;
1350 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1351 if (!CE) return false;
1352 int64_t Value = CE->getValue();
1353 return ARM_AM::getSOImmVal(Value) == -1 &&
1354 ARM_AM::getSOImmVal(-Value) != -1;
1357 bool isThumbModImmNeg1_7() const {
1358 if (!isImm()) return false;
1359 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1360 if (!CE) return false;
1361 int32_t Value = -(int32_t)CE->getValue();
1362 return 0 < Value && Value < 8;
1365 bool isThumbModImmNeg8_255() const {
1366 if (!isImm()) return false;
1367 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1368 if (!CE) return false;
1369 int32_t Value = -(int32_t)CE->getValue();
1370 return 7 < Value && Value < 256;
1373 bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
1374 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1375 bool isPostIdxRegShifted() const {
1376 return Kind == k_PostIndexRegister &&
1377 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
1379 bool isPostIdxReg() const {
1380 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1382 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1383 if (!isGPRMem())
1384 return false;
1385 // No offset of any kind.
1386 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1387 (alignOK || Memory.Alignment == Alignment);
1389 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1390 if (!isGPRMem())
1391 return false;
1393 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1394 Memory.BaseRegNum))
1395 return false;
1397 // No offset of any kind.
1398 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1399 (alignOK || Memory.Alignment == Alignment);
1401 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1402 if (!isGPRMem())
1403 return false;
1405 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
1406 Memory.BaseRegNum))
1407 return false;
1409 // No offset of any kind.
1410 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1411 (alignOK || Memory.Alignment == Alignment);
1413 bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1414 if (!isGPRMem())
1415 return false;
1417 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1418 Memory.BaseRegNum))
1419 return false;
1421 // No offset of any kind.
1422 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1423 (alignOK || Memory.Alignment == Alignment);
1425 bool isMemPCRelImm12() const {
1426 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1427 return false;
1428 // Base register must be PC.
1429 if (Memory.BaseRegNum != ARM::PC)
1430 return false;
1431 // Immediate offset in range [-4095, 4095].
1432 if (!Memory.OffsetImm) return true;
1433 int64_t Val = Memory.OffsetImm->getValue();
1434 return (Val > -4096 && Val < 4096) ||
1435 (Val == std::numeric_limits<int32_t>::min());
1438 bool isAlignedMemory() const {
1439 return isMemNoOffset(true);
1442 bool isAlignedMemoryNone() const {
1443 return isMemNoOffset(false, 0);
1446 bool isDupAlignedMemoryNone() const {
1447 return isMemNoOffset(false, 0);
1450 bool isAlignedMemory16() const {
1451 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1452 return true;
1453 return isMemNoOffset(false, 0);
1456 bool isDupAlignedMemory16() const {
1457 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1458 return true;
1459 return isMemNoOffset(false, 0);
1462 bool isAlignedMemory32() const {
1463 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1464 return true;
1465 return isMemNoOffset(false, 0);
1468 bool isDupAlignedMemory32() const {
1469 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1470 return true;
1471 return isMemNoOffset(false, 0);
1474 bool isAlignedMemory64() const {
1475 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1476 return true;
1477 return isMemNoOffset(false, 0);
1480 bool isDupAlignedMemory64() const {
1481 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1482 return true;
1483 return isMemNoOffset(false, 0);
1486 bool isAlignedMemory64or128() const {
1487 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1488 return true;
1489 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1490 return true;
1491 return isMemNoOffset(false, 0);
1494 bool isDupAlignedMemory64or128() const {
1495 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1496 return true;
1497 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1498 return true;
1499 return isMemNoOffset(false, 0);
1502 bool isAlignedMemory64or128or256() const {
1503 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1504 return true;
1505 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1506 return true;
1507 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1508 return true;
1509 return isMemNoOffset(false, 0);
1512 bool isAddrMode2() const {
1513 if (!isGPRMem() || Memory.Alignment != 0) return false;
1514 // Check for register offset.
1515 if (Memory.OffsetRegNum) return true;
1516 // Immediate offset in range [-4095, 4095].
1517 if (!Memory.OffsetImm) return true;
1518 int64_t Val = Memory.OffsetImm->getValue();
1519 return Val > -4096 && Val < 4096;
1522 bool isAM2OffsetImm() const {
1523 if (!isImm()) return false;
1524 // Immediate offset in range [-4095, 4095].
1525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1526 if (!CE) return false;
1527 int64_t Val = CE->getValue();
1528 return (Val == std::numeric_limits<int32_t>::min()) ||
1529 (Val > -4096 && Val < 4096);
1532 bool isAddrMode3() const {
1533 // If we have an immediate that's not a constant, treat it as a label
1534 // reference needing a fixup. If it is a constant, it's something else
1535 // and we reject it.
1536 if (isImm() && !isa<MCConstantExpr>(getImm()))
1537 return true;
1538 if (!isGPRMem() || Memory.Alignment != 0) return false;
1539 // No shifts are legal for AM3.
1540 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1541 // Check for register offset.
1542 if (Memory.OffsetRegNum) return true;
1543 // Immediate offset in range [-255, 255].
1544 if (!Memory.OffsetImm) return true;
1545 int64_t Val = Memory.OffsetImm->getValue();
1546 // The #-0 offset is encoded as std::numeric_limits<int32_t>::min(), and we
1547 // have to check for this too.
1548 return (Val > -256 && Val < 256) ||
1549 Val == std::numeric_limits<int32_t>::min();
1552 bool isAM3Offset() const {
1553 if (isPostIdxReg())
1554 return true;
1555 if (!isImm())
1556 return false;
1557 // Immediate offset in range [-255, 255].
1558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1559 if (!CE) return false;
1560 int64_t Val = CE->getValue();
1561 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1562 return (Val > -256 && Val < 256) ||
1563 Val == std::numeric_limits<int32_t>::min();
1566 bool isAddrMode5() const {
1567 // If we have an immediate that's not a constant, treat it as a label
1568 // reference needing a fixup. If it is a constant, it's something else
1569 // and we reject it.
1570 if (isImm() && !isa<MCConstantExpr>(getImm()))
1571 return true;
1572 if (!isGPRMem() || Memory.Alignment != 0) return false;
1573 // Check for register offset.
1574 if (Memory.OffsetRegNum) return false;
1575 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1576 if (!Memory.OffsetImm) return true;
1577 int64_t Val = Memory.OffsetImm->getValue();
1578 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1579 Val == std::numeric_limits<int32_t>::min();
1582 bool isAddrMode5FP16() const {
1583 // If we have an immediate that's not a constant, treat it as a label
1584 // reference needing a fixup. If it is a constant, it's something else
1585 // and we reject it.
1586 if (isImm() && !isa<MCConstantExpr>(getImm()))
1587 return true;
1588 if (!isGPRMem() || Memory.Alignment != 0) return false;
1589 // Check for register offset.
1590 if (Memory.OffsetRegNum) return false;
1591 // Immediate offset in range [-510, 510] and a multiple of 2.
1592 if (!Memory.OffsetImm) return true;
1593 int64_t Val = Memory.OffsetImm->getValue();
1594 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) ||
1595 Val == std::numeric_limits<int32_t>::min();
1598 bool isMemTBB() const {
1599 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1600 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1601 return false;
1602 return true;
1605 bool isMemTBH() const {
1606 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1607 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1608 Memory.Alignment != 0 )
1609 return false;
1610 return true;
1613 bool isMemRegOffset() const {
1614 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1615 return false;
1616 return true;
1619 bool isT2MemRegOffset() const {
1620 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1621 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
1622 return false;
1623 // Only lsl #{0, 1, 2, 3} allowed.
1624 if (Memory.ShiftType == ARM_AM::no_shift)
1625 return true;
1626 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1627 return false;
1628 return true;
1631 bool isMemThumbRR() const {
1632 // Thumb reg+reg addressing is simple. Just two registers, a base and
1633 // an offset. No shifts, negations or any other complicating factors.
1634 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1635 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1636 return false;
1637 return isARMLowRegister(Memory.BaseRegNum) &&
1638 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1641 bool isMemThumbRIs4() const {
1642 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1643 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1644 return false;
1645 // Immediate offset, multiple of 4 in range [0, 124].
1646 if (!Memory.OffsetImm) return true;
1647 int64_t Val = Memory.OffsetImm->getValue();
1648 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1651 bool isMemThumbRIs2() const {
1652 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1653 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1654 return false;
1655 // Immediate offset, multiple of 4 in range [0, 62].
1656 if (!Memory.OffsetImm) return true;
1657 int64_t Val = Memory.OffsetImm->getValue();
1658 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1661 bool isMemThumbRIs1() const {
1662 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1663 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1664 return false;
1665 // Immediate offset in range [0, 31].
1666 if (!Memory.OffsetImm) return true;
1667 int64_t Val = Memory.OffsetImm->getValue();
1668 return Val >= 0 && Val <= 31;
1671 bool isMemThumbSPI() const {
1672 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
1673 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1674 return false;
1675 // Immediate offset, multiple of 4 in range [0, 1020].
1676 if (!Memory.OffsetImm) return true;
1677 int64_t Val = Memory.OffsetImm->getValue();
1678 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1681 bool isMemImm8s4Offset() const {
1682 // If we have an immediate that's not a constant, treat it as a label
1683 // reference needing a fixup. If it is a constant, it's something else
1684 // and we reject it.
1685 if (isImm() && !isa<MCConstantExpr>(getImm()))
1686 return true;
1687 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1688 return false;
1689 // Immediate offset a multiple of 4 in range [-1020, 1020].
1690 if (!Memory.OffsetImm) return true;
1691 int64_t Val = Memory.OffsetImm->getValue();
1692 // Special case, #-0 is std::numeric_limits<int32_t>::min().
1693 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) ||
1694 Val == std::numeric_limits<int32_t>::min();
1696 bool isMemImm7s4Offset() const {
1697 // If we have an immediate that's not a constant, treat it as a label
1698 // reference needing a fixup. If it is a constant, it's something else
1699 // and we reject it.
1700 if (isImm() && !isa<MCConstantExpr>(getImm()))
1701 return true;
1702 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1703 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1704 Memory.BaseRegNum))
1705 return false;
1706 // Immediate offset a multiple of 4 in range [-508, 508].
1707 if (!Memory.OffsetImm) return true;
1708 int64_t Val = Memory.OffsetImm->getValue();
1709 // Special case, #-0 is INT32_MIN.
1710 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
1712 bool isMemImm0_1020s4Offset() const {
1713 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1714 return false;
1715 // Immediate offset a multiple of 4 in range [0, 1020].
1716 if (!Memory.OffsetImm) return true;
1717 int64_t Val = Memory.OffsetImm->getValue();
1718 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1721 bool isMemImm8Offset() const {
1722 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1723 return false;
1724 // Base reg of PC isn't allowed for these encodings.
1725 if (Memory.BaseRegNum == ARM::PC) return false;
1726 // Immediate offset in range [-255, 255].
1727 if (!Memory.OffsetImm) return true;
1728 int64_t Val = Memory.OffsetImm->getValue();
1729 return (Val == std::numeric_limits<int32_t>::min()) ||
1730 (Val > -256 && Val < 256);
1733 template<unsigned Bits, unsigned RegClassID>
1734 bool isMemImm7ShiftedOffset() const {
1735 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1736 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1737 return false;
1739 // Expect an immediate offset equal to an element of the range
1740 // [-127, 127], shifted left by Bits.
1742 if (!Memory.OffsetImm) return true;
1743 int64_t Val = Memory.OffsetImm->getValue();
1745 // INT32_MIN is a special-case value (indicating the encoding with
1746 // zero offset and the subtract bit set)
1747 if (Val == INT32_MIN)
1748 return true;
1750 unsigned Divisor = 1U << Bits;
1752 // Check that the low bits are zero
1753 if (Val % Divisor != 0)
1754 return false;
1756 // Check that the remaining offset is within range.
1757 Val /= Divisor;
1758 return (Val >= -127 && Val <= 127);
1761 template <int shift> bool isMemRegRQOffset() const {
1762 if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)
1763 return false;
1765 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1766 Memory.BaseRegNum))
1767 return false;
1768 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1769 Memory.OffsetRegNum))
1770 return false;
1772 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1773 return false;
1775 if (shift > 0 &&
1776 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1777 return false;
1779 return true;
1782 template <int shift> bool isMemRegQOffset() const {
1783 if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1784 return false;
1786 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1787 Memory.BaseRegNum))
1788 return false;
1790 if(!Memory.OffsetImm) return true;
1791 static_assert(shift < 56,
1792 "Such that we dont shift by a value higher than 62");
1793 int64_t Val = Memory.OffsetImm->getValue();
1795 // The value must be a multiple of (1 << shift)
1796 if ((Val & ((1U << shift) - 1)) != 0)
1797 return false;
1799 // And be in the right range, depending on the amount that it is shifted
1800 // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
1801 // separately.
1802 int64_t Range = (1U << (7+shift)) - 1;
1803 return (Val == INT32_MIN) || (Val > -Range && Val < Range);
1806 bool isMemPosImm8Offset() const {
1807 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1808 return false;
1809 // Immediate offset in range [0, 255].
1810 if (!Memory.OffsetImm) return true;
1811 int64_t Val = Memory.OffsetImm->getValue();
1812 return Val >= 0 && Val < 256;
1815 bool isMemNegImm8Offset() const {
1816 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1817 return false;
1818 // Base reg of PC isn't allowed for these encodings.
1819 if (Memory.BaseRegNum == ARM::PC) return false;
1820 // Immediate offset in range [-255, -1].
1821 if (!Memory.OffsetImm) return false;
1822 int64_t Val = Memory.OffsetImm->getValue();
1823 return (Val == std::numeric_limits<int32_t>::min()) ||
1824 (Val > -256 && Val < 0);
1827 bool isMemUImm12Offset() const {
1828 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1829 return false;
1830 // Immediate offset in range [0, 4095].
1831 if (!Memory.OffsetImm) return true;
1832 int64_t Val = Memory.OffsetImm->getValue();
1833 return (Val >= 0 && Val < 4096);
1836 bool isMemImm12Offset() const {
1837 // If we have an immediate that's not a constant, treat it as a label
1838 // reference needing a fixup. If it is a constant, it's something else
1839 // and we reject it.
1841 if (isImm() && !isa<MCConstantExpr>(getImm()))
1842 return true;
1844 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1845 return false;
1846 // Immediate offset in range [-4095, 4095].
1847 if (!Memory.OffsetImm) return true;
1848 int64_t Val = Memory.OffsetImm->getValue();
1849 return (Val > -4096 && Val < 4096) ||
1850 (Val == std::numeric_limits<int32_t>::min());
1853 bool isConstPoolAsmImm() const {
1854 // Delay processing of Constant Pool Immediate, this will turn into
1855 // a constant. Match no other operand
1856 return (isConstantPoolImm());
1859 bool isPostIdxImm8() const {
1860 if (!isImm()) return false;
1861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1862 if (!CE) return false;
1863 int64_t Val = CE->getValue();
1864 return (Val > -256 && Val < 256) ||
1865 (Val == std::numeric_limits<int32_t>::min());
1868 bool isPostIdxImm8s4() const {
1869 if (!isImm()) return false;
1870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1871 if (!CE) return false;
1872 int64_t Val = CE->getValue();
1873 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1874 (Val == std::numeric_limits<int32_t>::min());
1877 bool isMSRMask() const { return Kind == k_MSRMask; }
1878 bool isBankedReg() const { return Kind == k_BankedReg; }
1879 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1881 // NEON operands.
1882 bool isSingleSpacedVectorList() const {
1883 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1886 bool isDoubleSpacedVectorList() const {
1887 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1890 bool isVecListOneD() const {
1891 if (!isSingleSpacedVectorList()) return false;
1892 return VectorList.Count == 1;
1895 bool isVecListTwoMQ() const {
1896 return isSingleSpacedVectorList() && VectorList.Count == 2 &&
1897 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1898 VectorList.RegNum);
1901 bool isVecListDPair() const {
1902 if (!isSingleSpacedVectorList()) return false;
1903 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1904 .contains(VectorList.RegNum));
1907 bool isVecListThreeD() const {
1908 if (!isSingleSpacedVectorList()) return false;
1909 return VectorList.Count == 3;
1912 bool isVecListFourD() const {
1913 if (!isSingleSpacedVectorList()) return false;
1914 return VectorList.Count == 4;
1917 bool isVecListDPairSpaced() const {
1918 if (Kind != k_VectorList) return false;
1919 if (isSingleSpacedVectorList()) return false;
1920 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1921 .contains(VectorList.RegNum));
1924 bool isVecListThreeQ() const {
1925 if (!isDoubleSpacedVectorList()) return false;
1926 return VectorList.Count == 3;
1929 bool isVecListFourQ() const {
1930 if (!isDoubleSpacedVectorList()) return false;
1931 return VectorList.Count == 4;
1934 bool isVecListFourMQ() const {
1935 return isSingleSpacedVectorList() && VectorList.Count == 4 &&
1936 ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1937 VectorList.RegNum);
1940 bool isSingleSpacedVectorAllLanes() const {
1941 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1944 bool isDoubleSpacedVectorAllLanes() const {
1945 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1948 bool isVecListOneDAllLanes() const {
1949 if (!isSingleSpacedVectorAllLanes()) return false;
1950 return VectorList.Count == 1;
1953 bool isVecListDPairAllLanes() const {
1954 if (!isSingleSpacedVectorAllLanes()) return false;
1955 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1956 .contains(VectorList.RegNum));
1959 bool isVecListDPairSpacedAllLanes() const {
1960 if (!isDoubleSpacedVectorAllLanes()) return false;
1961 return VectorList.Count == 2;
1964 bool isVecListThreeDAllLanes() const {
1965 if (!isSingleSpacedVectorAllLanes()) return false;
1966 return VectorList.Count == 3;
1969 bool isVecListThreeQAllLanes() const {
1970 if (!isDoubleSpacedVectorAllLanes()) return false;
1971 return VectorList.Count == 3;
1974 bool isVecListFourDAllLanes() const {
1975 if (!isSingleSpacedVectorAllLanes()) return false;
1976 return VectorList.Count == 4;
1979 bool isVecListFourQAllLanes() const {
1980 if (!isDoubleSpacedVectorAllLanes()) return false;
1981 return VectorList.Count == 4;
1984 bool isSingleSpacedVectorIndexed() const {
1985 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1988 bool isDoubleSpacedVectorIndexed() const {
1989 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1992 bool isVecListOneDByteIndexed() const {
1993 if (!isSingleSpacedVectorIndexed()) return false;
1994 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1997 bool isVecListOneDHWordIndexed() const {
1998 if (!isSingleSpacedVectorIndexed()) return false;
1999 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
2002 bool isVecListOneDWordIndexed() const {
2003 if (!isSingleSpacedVectorIndexed()) return false;
2004 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
2007 bool isVecListTwoDByteIndexed() const {
2008 if (!isSingleSpacedVectorIndexed()) return false;
2009 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
2012 bool isVecListTwoDHWordIndexed() const {
2013 if (!isSingleSpacedVectorIndexed()) return false;
2014 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2017 bool isVecListTwoQWordIndexed() const {
2018 if (!isDoubleSpacedVectorIndexed()) return false;
2019 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2022 bool isVecListTwoQHWordIndexed() const {
2023 if (!isDoubleSpacedVectorIndexed()) return false;
2024 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
2027 bool isVecListTwoDWordIndexed() const {
2028 if (!isSingleSpacedVectorIndexed()) return false;
2029 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
2032 bool isVecListThreeDByteIndexed() const {
2033 if (!isSingleSpacedVectorIndexed()) return false;
2034 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
2037 bool isVecListThreeDHWordIndexed() const {
2038 if (!isSingleSpacedVectorIndexed()) return false;
2039 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2042 bool isVecListThreeQWordIndexed() const {
2043 if (!isDoubleSpacedVectorIndexed()) return false;
2044 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2047 bool isVecListThreeQHWordIndexed() const {
2048 if (!isDoubleSpacedVectorIndexed()) return false;
2049 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
2052 bool isVecListThreeDWordIndexed() const {
2053 if (!isSingleSpacedVectorIndexed()) return false;
2054 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
2057 bool isVecListFourDByteIndexed() const {
2058 if (!isSingleSpacedVectorIndexed()) return false;
2059 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
2062 bool isVecListFourDHWordIndexed() const {
2063 if (!isSingleSpacedVectorIndexed()) return false;
2064 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2067 bool isVecListFourQWordIndexed() const {
2068 if (!isDoubleSpacedVectorIndexed()) return false;
2069 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2072 bool isVecListFourQHWordIndexed() const {
2073 if (!isDoubleSpacedVectorIndexed()) return false;
2074 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
2077 bool isVecListFourDWordIndexed() const {
2078 if (!isSingleSpacedVectorIndexed()) return false;
2079 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
2082 bool isVectorIndex() const { return Kind == k_VectorIndex; }
2084 template <unsigned NumLanes>
2085 bool isVectorIndexInRange() const {
2086 if (Kind != k_VectorIndex) return false;
2087 return VectorIndex.Val < NumLanes;
2090 bool isVectorIndex8() const { return isVectorIndexInRange<8>(); }
2091 bool isVectorIndex16() const { return isVectorIndexInRange<4>(); }
2092 bool isVectorIndex32() const { return isVectorIndexInRange<2>(); }
2093 bool isVectorIndex64() const { return isVectorIndexInRange<1>(); }
2095 template<int PermittedValue, int OtherPermittedValue>
2096 bool isMVEPairVectorIndex() const {
2097 if (Kind != k_VectorIndex) return false;
2098 return VectorIndex.Val == PermittedValue ||
2099 VectorIndex.Val == OtherPermittedValue;
2102 bool isNEONi8splat() const {
2103 if (!isImm()) return false;
2104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2105 // Must be a constant.
2106 if (!CE) return false;
2107 int64_t Value = CE->getValue();
2108 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
2109 // value.
2110 return Value >= 0 && Value < 256;
2113 bool isNEONi16splat() const {
2114 if (isNEONByteReplicate(2))
2115 return false; // Leave that for bytes replication and forbid by default.
2116 if (!isImm())
2117 return false;
2118 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2119 // Must be a constant.
2120 if (!CE) return false;
2121 unsigned Value = CE->getValue();
2122 return ARM_AM::isNEONi16splat(Value);
2125 bool isNEONi16splatNot() const {
2126 if (!isImm())
2127 return false;
2128 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2129 // Must be a constant.
2130 if (!CE) return false;
2131 unsigned Value = CE->getValue();
2132 return ARM_AM::isNEONi16splat(~Value & 0xffff);
2135 bool isNEONi32splat() const {
2136 if (isNEONByteReplicate(4))
2137 return false; // Leave that for bytes replication and forbid by default.
2138 if (!isImm())
2139 return false;
2140 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2141 // Must be a constant.
2142 if (!CE) return false;
2143 unsigned Value = CE->getValue();
2144 return ARM_AM::isNEONi32splat(Value);
2147 bool isNEONi32splatNot() const {
2148 if (!isImm())
2149 return false;
2150 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2151 // Must be a constant.
2152 if (!CE) return false;
2153 unsigned Value = CE->getValue();
2154 return ARM_AM::isNEONi32splat(~Value);
2157 static bool isValidNEONi32vmovImm(int64_t Value) {
2158 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
2159 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
2160 return ((Value & 0xffffffffffffff00) == 0) ||
2161 ((Value & 0xffffffffffff00ff) == 0) ||
2162 ((Value & 0xffffffffff00ffff) == 0) ||
2163 ((Value & 0xffffffff00ffffff) == 0) ||
2164 ((Value & 0xffffffffffff00ff) == 0xff) ||
2165 ((Value & 0xffffffffff00ffff) == 0xffff);
2168 bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const {
2169 assert((Width == 8 || Width == 16 || Width == 32) &&
2170 "Invalid element width");
2171 assert(NumElems * Width <= 64 && "Invalid result width");
2173 if (!isImm())
2174 return false;
2175 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2176 // Must be a constant.
2177 if (!CE)
2178 return false;
2179 int64_t Value = CE->getValue();
2180 if (!Value)
2181 return false; // Don't bother with zero.
2182 if (Inv)
2183 Value = ~Value;
2185 uint64_t Mask = (1ull << Width) - 1;
2186 uint64_t Elem = Value & Mask;
2187 if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0)
2188 return false;
2189 if (Width == 32 && !isValidNEONi32vmovImm(Elem))
2190 return false;
2192 for (unsigned i = 1; i < NumElems; ++i) {
2193 Value >>= Width;
2194 if ((Value & Mask) != Elem)
2195 return false;
2197 return true;
2200 bool isNEONByteReplicate(unsigned NumBytes) const {
2201 return isNEONReplicate(8, NumBytes, false);
2204 static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) {
2205 assert((FromW == 8 || FromW == 16 || FromW == 32) &&
2206 "Invalid source width");
2207 assert((ToW == 16 || ToW == 32 || ToW == 64) &&
2208 "Invalid destination width");
2209 assert(FromW < ToW && "ToW is not less than FromW");
2212 template<unsigned FromW, unsigned ToW>
2213 bool isNEONmovReplicate() const {
2214 checkNeonReplicateArgs(FromW, ToW);
2215 if (ToW == 64 && isNEONi64splat())
2216 return false;
2217 return isNEONReplicate(FromW, ToW / FromW, false);
2220 template<unsigned FromW, unsigned ToW>
2221 bool isNEONinvReplicate() const {
2222 checkNeonReplicateArgs(FromW, ToW);
2223 return isNEONReplicate(FromW, ToW / FromW, true);
2226 bool isNEONi32vmov() const {
2227 if (isNEONByteReplicate(4))
2228 return false; // Let it to be classified as byte-replicate case.
2229 if (!isImm())
2230 return false;
2231 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2232 // Must be a constant.
2233 if (!CE)
2234 return false;
2235 return isValidNEONi32vmovImm(CE->getValue());
2238 bool isNEONi32vmovNeg() const {
2239 if (!isImm()) return false;
2240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2241 // Must be a constant.
2242 if (!CE) return false;
2243 return isValidNEONi32vmovImm(~CE->getValue());
2246 bool isNEONi64splat() const {
2247 if (!isImm()) return false;
2248 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2249 // Must be a constant.
2250 if (!CE) return false;
2251 uint64_t Value = CE->getValue();
2252 // i64 value with each byte being either 0 or 0xff.
2253 for (unsigned i = 0; i < 8; ++i, Value >>= 8)
2254 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
2255 return true;
2258 template<int64_t Angle, int64_t Remainder>
2259 bool isComplexRotation() const {
2260 if (!isImm()) return false;
2262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2263 if (!CE) return false;
2264 uint64_t Value = CE->getValue();
2266 return (Value % Angle == Remainder && Value <= 270);
2269 bool isMVELongShift() const {
2270 if (!isImm()) return false;
2271 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2272 // Must be a constant.
2273 if (!CE) return false;
2274 uint64_t Value = CE->getValue();
2275 return Value >= 1 && Value <= 32;
2278 bool isMveSaturateOp() const {
2279 if (!isImm()) return false;
2280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2281 if (!CE) return false;
2282 uint64_t Value = CE->getValue();
2283 return Value == 48 || Value == 64;
2286 bool isITCondCodeNoAL() const {
2287 if (!isITCondCode()) return false;
2288 ARMCC::CondCodes CC = getCondCode();
2289 return CC != ARMCC::AL;
2292 bool isITCondCodeRestrictedI() const {
2293 if (!isITCondCode())
2294 return false;
2295 ARMCC::CondCodes CC = getCondCode();
2296 return CC == ARMCC::EQ || CC == ARMCC::NE;
2299 bool isITCondCodeRestrictedS() const {
2300 if (!isITCondCode())
2301 return false;
2302 ARMCC::CondCodes CC = getCondCode();
2303 return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE ||
2304 CC == ARMCC::GE;
2307 bool isITCondCodeRestrictedU() const {
2308 if (!isITCondCode())
2309 return false;
2310 ARMCC::CondCodes CC = getCondCode();
2311 return CC == ARMCC::HS || CC == ARMCC::HI;
2314 bool isITCondCodeRestrictedFP() const {
2315 if (!isITCondCode())
2316 return false;
2317 ARMCC::CondCodes CC = getCondCode();
2318 return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT ||
2319 CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE;
2322 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
2323 // Add as immediates when possible. Null MCExpr = 0.
2324 if (!Expr)
2325 Inst.addOperand(MCOperand::createImm(0));
2326 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
2327 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2328 else
2329 Inst.addOperand(MCOperand::createExpr(Expr));
2332 void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
2333 assert(N == 1 && "Invalid number of operands!");
2334 addExpr(Inst, getImm());
2337 void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
2338 assert(N == 1 && "Invalid number of operands!");
2339 addExpr(Inst, getImm());
2342 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
2343 assert(N == 2 && "Invalid number of operands!");
2344 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2345 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
2346 Inst.addOperand(MCOperand::createReg(RegNum));
2349 void addVPTPredNOperands(MCInst &Inst, unsigned N) const {
2350 assert(N == 2 && "Invalid number of operands!");
2351 Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred())));
2352 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;
2353 Inst.addOperand(MCOperand::createReg(RegNum));
2356 void addVPTPredROperands(MCInst &Inst, unsigned N) const {
2357 assert(N == 3 && "Invalid number of operands!");
2358 addVPTPredNOperands(Inst, N-1);
2359 unsigned RegNum;
2360 if (getVPTPred() == ARMVCC::None) {
2361 RegNum = 0;
2362 } else {
2363 unsigned NextOpIndex = Inst.getNumOperands();
2364 const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
2365 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
2366 assert(TiedOp >= 0 &&
2367 "Inactive register in vpred_r is not tied to an output!");
2368 RegNum = Inst.getOperand(TiedOp).getReg();
2370 Inst.addOperand(MCOperand::createReg(RegNum));
2373 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
2374 assert(N == 1 && "Invalid number of operands!");
2375 Inst.addOperand(MCOperand::createImm(getCoproc()));
2378 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
2379 assert(N == 1 && "Invalid number of operands!");
2380 Inst.addOperand(MCOperand::createImm(getCoproc()));
2383 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
2384 assert(N == 1 && "Invalid number of operands!");
2385 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
2388 void addITMaskOperands(MCInst &Inst, unsigned N) const {
2389 assert(N == 1 && "Invalid number of operands!");
2390 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
2393 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
2394 assert(N == 1 && "Invalid number of operands!");
2395 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
2398 void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const {
2399 assert(N == 1 && "Invalid number of operands!");
2400 Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode()))));
2403 void addCCOutOperands(MCInst &Inst, unsigned N) const {
2404 assert(N == 1 && "Invalid number of operands!");
2405 Inst.addOperand(MCOperand::createReg(getReg()));
2408 void addRegOperands(MCInst &Inst, unsigned N) const {
2409 assert(N == 1 && "Invalid number of operands!");
2410 Inst.addOperand(MCOperand::createReg(getReg()));
2413 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
2414 assert(N == 3 && "Invalid number of operands!");
2415 assert(isRegShiftedReg() &&
2416 "addRegShiftedRegOperands() on non-RegShiftedReg!");
2417 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
2418 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
2419 Inst.addOperand(MCOperand::createImm(
2420 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2423 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
2424 assert(N == 2 && "Invalid number of operands!");
2425 assert(isRegShiftedImm() &&
2426 "addRegShiftedImmOperands() on non-RegShiftedImm!");
2427 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
2428 // Shift of #32 is encoded as 0 where permitted
2429 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
2430 Inst.addOperand(MCOperand::createImm(
2431 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2434 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
2435 assert(N == 1 && "Invalid number of operands!");
2436 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
2437 ShifterImm.Imm));
2440 void addRegListOperands(MCInst &Inst, unsigned N) const {
2441 assert(N == 1 && "Invalid number of operands!");
2442 const SmallVectorImpl<unsigned> &RegList = getRegList();
2443 for (SmallVectorImpl<unsigned>::const_iterator
2444 I = RegList.begin(), E = RegList.end(); I != E; ++I)
2445 Inst.addOperand(MCOperand::createReg(*I));
2448 void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const {
2449 assert(N == 1 && "Invalid number of operands!");
2450 const SmallVectorImpl<unsigned> &RegList = getRegList();
2451 for (SmallVectorImpl<unsigned>::const_iterator
2452 I = RegList.begin(), E = RegList.end(); I != E; ++I)
2453 Inst.addOperand(MCOperand::createReg(*I));
2456 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
2457 addRegListOperands(Inst, N);
2460 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
2461 addRegListOperands(Inst, N);
2464 void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2465 addRegListOperands(Inst, N);
2468 void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const {
2469 addRegListOperands(Inst, N);
2472 void addRotImmOperands(MCInst &Inst, unsigned N) const {
2473 assert(N == 1 && "Invalid number of operands!");
2474 // Encoded as val>>3. The printer handles display as 8, 16, 24.
2475 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
2478 void addModImmOperands(MCInst &Inst, unsigned N) const {
2479 assert(N == 1 && "Invalid number of operands!");
2481 // Support for fixups (MCFixup)
2482 if (isImm())
2483 return addImmOperands(Inst, N);
2485 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
2488 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
2489 assert(N == 1 && "Invalid number of operands!");
2490 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2491 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2492 Inst.addOperand(MCOperand::createImm(Enc));
2495 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
2496 assert(N == 1 && "Invalid number of operands!");
2497 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2498 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2499 Inst.addOperand(MCOperand::createImm(Enc));
2502 void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
2503 assert(N == 1 && "Invalid number of operands!");
2504 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2505 uint32_t Val = -CE->getValue();
2506 Inst.addOperand(MCOperand::createImm(Val));
2509 void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
2510 assert(N == 1 && "Invalid number of operands!");
2511 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2512 uint32_t Val = -CE->getValue();
2513 Inst.addOperand(MCOperand::createImm(Val));
2516 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
2517 assert(N == 1 && "Invalid number of operands!");
2518 // Munge the lsb/width into a bitfield mask.
2519 unsigned lsb = Bitfield.LSB;
2520 unsigned width = Bitfield.Width;
2521 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
2522 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
2523 (32 - (lsb + width)));
2524 Inst.addOperand(MCOperand::createImm(Mask));
2527 void addImmOperands(MCInst &Inst, unsigned N) const {
2528 assert(N == 1 && "Invalid number of operands!");
2529 addExpr(Inst, getImm());
2532 void addFBits16Operands(MCInst &Inst, unsigned N) const {
2533 assert(N == 1 && "Invalid number of operands!");
2534 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2535 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
2538 void addFBits32Operands(MCInst &Inst, unsigned N) const {
2539 assert(N == 1 && "Invalid number of operands!");
2540 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2541 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
2544 void addFPImmOperands(MCInst &Inst, unsigned N) const {
2545 assert(N == 1 && "Invalid number of operands!");
2546 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2547 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2548 Inst.addOperand(MCOperand::createImm(Val));
2551 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
2552 assert(N == 1 && "Invalid number of operands!");
2553 // FIXME: We really want to scale the value here, but the LDRD/STRD
2554 // instruction don't encode operands that way yet.
2555 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2556 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2559 void addImm7s4Operands(MCInst &Inst, unsigned N) const {
2560 assert(N == 1 && "Invalid number of operands!");
2561 // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR
2562 // instruction don't encode operands that way yet.
2563 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2564 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2567 void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2568 assert(N == 1 && "Invalid number of operands!");
2569 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2570 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2573 void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2574 assert(N == 1 && "Invalid number of operands!");
2575 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2576 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2579 void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2580 assert(N == 1 && "Invalid number of operands!");
2581 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2582 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2585 void addImm7Operands(MCInst &Inst, unsigned N) const {
2586 assert(N == 1 && "Invalid number of operands!");
2587 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2588 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2591 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
2592 assert(N == 1 && "Invalid number of operands!");
2593 // The immediate is scaled by four in the encoding and is stored
2594 // in the MCInst as such. Lop off the low two bits here.
2595 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2596 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2599 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
2600 assert(N == 1 && "Invalid number of operands!");
2601 // The immediate is scaled by four in the encoding and is stored
2602 // in the MCInst as such. Lop off the low two bits here.
2603 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2604 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
2607 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
2608 assert(N == 1 && "Invalid number of operands!");
2609 // The immediate is scaled by four in the encoding and is stored
2610 // in the MCInst as such. Lop off the low two bits here.
2611 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2612 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
2615 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
2616 assert(N == 1 && "Invalid number of operands!");
2617 // The constant encodes as the immediate-1, and we store in the instruction
2618 // the bits as encoded, so subtract off one here.
2619 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2620 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2623 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
2624 assert(N == 1 && "Invalid number of operands!");
2625 // The constant encodes as the immediate-1, and we store in the instruction
2626 // the bits as encoded, so subtract off one here.
2627 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2628 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
2631 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
2632 assert(N == 1 && "Invalid number of operands!");
2633 // The constant encodes as the immediate, except for 32, which encodes as
2634 // zero.
2635 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2636 unsigned Imm = CE->getValue();
2637 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
2640 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
2641 assert(N == 1 && "Invalid number of operands!");
2642 // An ASR value of 32 encodes as 0, so that's how we want to add it to
2643 // the instruction as well.
2644 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2645 int Val = CE->getValue();
2646 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
2649 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
2650 assert(N == 1 && "Invalid number of operands!");
2651 // The operand is actually a t2_so_imm, but we have its bitwise
2652 // negation in the assembly source, so twiddle it here.
2653 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2654 Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
2657 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
2658 assert(N == 1 && "Invalid number of operands!");
2659 // The operand is actually a t2_so_imm, but we have its
2660 // negation in the assembly source, so twiddle it here.
2661 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2662 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2665 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
2666 assert(N == 1 && "Invalid number of operands!");
2667 // The operand is actually an imm0_4095, but we have its
2668 // negation in the assembly source, so twiddle it here.
2669 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2670 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
2673 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2674 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2675 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2676 return;
2678 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2679 Inst.addOperand(MCOperand::createExpr(SR));
2682 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2683 assert(N == 1 && "Invalid number of operands!");
2684 if (isImm()) {
2685 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2686 if (CE) {
2687 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2688 return;
2690 const MCSymbolRefExpr *SR = cast<MCSymbolRefExpr>(Imm.Val);
2691 Inst.addOperand(MCOperand::createExpr(SR));
2692 return;
2695 assert(isGPRMem() && "Unknown value type!");
2696 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2697 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2700 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2701 assert(N == 1 && "Invalid number of operands!");
2702 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2705 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2706 assert(N == 1 && "Invalid number of operands!");
2707 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2710 void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2711 assert(N == 1 && "Invalid number of operands!");
2712 Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt())));
2715 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2716 assert(N == 1 && "Invalid number of operands!");
2717 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2720 void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const {
2721 assert(N == 1 && "Invalid number of operands!");
2722 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2725 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2726 assert(N == 1 && "Invalid number of operands!");
2727 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2730 void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
2731 assert(N == 1 && "Invalid number of operands!");
2732 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2735 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2736 assert(N == 1 && "Invalid number of operands!");
2737 int32_t Imm = Memory.OffsetImm->getValue();
2738 Inst.addOperand(MCOperand::createImm(Imm));
2741 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2742 assert(N == 1 && "Invalid number of operands!");
2743 assert(isImm() && "Not an immediate!");
2745 // If we have an immediate that's not a constant, treat it as a label
2746 // reference needing a fixup.
2747 if (!isa<MCConstantExpr>(getImm())) {
2748 Inst.addOperand(MCOperand::createExpr(getImm()));
2749 return;
2752 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
2753 int Val = CE->getValue();
2754 Inst.addOperand(MCOperand::createImm(Val));
2757 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2758 assert(N == 2 && "Invalid number of operands!");
2759 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2760 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2763 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2764 addAlignedMemoryOperands(Inst, N);
2767 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2768 addAlignedMemoryOperands(Inst, N);
2771 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2772 addAlignedMemoryOperands(Inst, N);
2775 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2776 addAlignedMemoryOperands(Inst, N);
2779 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2780 addAlignedMemoryOperands(Inst, N);
2783 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2784 addAlignedMemoryOperands(Inst, N);
2787 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2788 addAlignedMemoryOperands(Inst, N);
2791 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2792 addAlignedMemoryOperands(Inst, N);
2795 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2796 addAlignedMemoryOperands(Inst, N);
2799 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2800 addAlignedMemoryOperands(Inst, N);
2803 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2804 addAlignedMemoryOperands(Inst, N);
2807 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2808 assert(N == 3 && "Invalid number of operands!");
2809 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2810 if (!Memory.OffsetRegNum) {
2811 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2812 // Special case for #-0
2813 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2814 if (Val < 0) Val = -Val;
2815 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2816 } else {
2817 // For register offset, we encode the shift type and negation flag
2818 // here.
2819 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2820 Memory.ShiftImm, Memory.ShiftType);
2822 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2823 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2824 Inst.addOperand(MCOperand::createImm(Val));
2827 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2828 assert(N == 2 && "Invalid number of operands!");
2829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2830 assert(CE && "non-constant AM2OffsetImm operand!");
2831 int32_t Val = CE->getValue();
2832 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2833 // Special case for #-0
2834 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2835 if (Val < 0) Val = -Val;
2836 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2837 Inst.addOperand(MCOperand::createReg(0));
2838 Inst.addOperand(MCOperand::createImm(Val));
2841 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2842 assert(N == 3 && "Invalid number of operands!");
2843 // If we have an immediate that's not a constant, treat it as a label
2844 // reference needing a fixup. If it is a constant, it's something else
2845 // and we reject it.
2846 if (isImm()) {
2847 Inst.addOperand(MCOperand::createExpr(getImm()));
2848 Inst.addOperand(MCOperand::createReg(0));
2849 Inst.addOperand(MCOperand::createImm(0));
2850 return;
2853 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2854 if (!Memory.OffsetRegNum) {
2855 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2856 // Special case for #-0
2857 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2858 if (Val < 0) Val = -Val;
2859 Val = ARM_AM::getAM3Opc(AddSub, Val);
2860 } else {
2861 // For register offset, we encode the shift type and negation flag
2862 // here.
2863 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2865 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2866 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2867 Inst.addOperand(MCOperand::createImm(Val));
2870 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2871 assert(N == 2 && "Invalid number of operands!");
2872 if (Kind == k_PostIndexRegister) {
2873 int32_t Val =
2874 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2875 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2876 Inst.addOperand(MCOperand::createImm(Val));
2877 return;
2880 // Constant offset.
2881 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2882 int32_t Val = CE->getValue();
2883 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2884 // Special case for #-0
2885 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2886 if (Val < 0) Val = -Val;
2887 Val = ARM_AM::getAM3Opc(AddSub, Val);
2888 Inst.addOperand(MCOperand::createReg(0));
2889 Inst.addOperand(MCOperand::createImm(Val));
2892 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2893 assert(N == 2 && "Invalid number of operands!");
2894 // If we have an immediate that's not a constant, treat it as a label
2895 // reference needing a fixup. If it is a constant, it's something else
2896 // and we reject it.
2897 if (isImm()) {
2898 Inst.addOperand(MCOperand::createExpr(getImm()));
2899 Inst.addOperand(MCOperand::createImm(0));
2900 return;
2903 // The lower two bits are always zero and as such are not encoded.
2904 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2905 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2906 // Special case for #-0
2907 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2908 if (Val < 0) Val = -Val;
2909 Val = ARM_AM::getAM5Opc(AddSub, Val);
2910 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2911 Inst.addOperand(MCOperand::createImm(Val));
2914 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2915 assert(N == 2 && "Invalid number of operands!");
2916 // If we have an immediate that's not a constant, treat it as a label
2917 // reference needing a fixup. If it is a constant, it's something else
2918 // and we reject it.
2919 if (isImm()) {
2920 Inst.addOperand(MCOperand::createExpr(getImm()));
2921 Inst.addOperand(MCOperand::createImm(0));
2922 return;
2925 // The lower bit is always zero and as such is not encoded.
2926 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2927 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2928 // Special case for #-0
2929 if (Val == std::numeric_limits<int32_t>::min()) Val = 0;
2930 if (Val < 0) Val = -Val;
2931 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2932 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2933 Inst.addOperand(MCOperand::createImm(Val));
2936 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2937 assert(N == 2 && "Invalid number of operands!");
2938 // If we have an immediate that's not a constant, treat it as a label
2939 // reference needing a fixup. If it is a constant, it's something else
2940 // and we reject it.
2941 if (isImm()) {
2942 Inst.addOperand(MCOperand::createExpr(getImm()));
2943 Inst.addOperand(MCOperand::createImm(0));
2944 return;
2947 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2948 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2949 Inst.addOperand(MCOperand::createImm(Val));
2952 void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const {
2953 assert(N == 2 && "Invalid number of operands!");
2954 // If we have an immediate that's not a constant, treat it as a label
2955 // reference needing a fixup. If it is a constant, it's something else
2956 // and we reject it.
2957 if (isImm()) {
2958 Inst.addOperand(MCOperand::createExpr(getImm()));
2959 Inst.addOperand(MCOperand::createImm(0));
2960 return;
2963 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2964 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2965 Inst.addOperand(MCOperand::createImm(Val));
2968 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2969 assert(N == 2 && "Invalid number of operands!");
2970 // The lower two bits are always zero and as such are not encoded.
2971 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2972 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2973 Inst.addOperand(MCOperand::createImm(Val));
2976 void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
2977 assert(N == 2 && "Invalid number of operands!");
2978 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2979 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2980 Inst.addOperand(MCOperand::createImm(Val));
2983 void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
2984 assert(N == 2 && "Invalid number of operands!");
2985 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2986 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2989 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2990 assert(N == 2 && "Invalid number of operands!");
2991 // If this is an immediate, it's a label reference.
2992 if (isImm()) {
2993 addExpr(Inst, getImm());
2994 Inst.addOperand(MCOperand::createImm(0));
2995 return;
2998 // Otherwise, it's a normal memory reg+offset.
2999 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3000 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3001 Inst.addOperand(MCOperand::createImm(Val));
3004 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
3005 assert(N == 2 && "Invalid number of operands!");
3006 // If this is an immediate, it's a label reference.
3007 if (isImm()) {
3008 addExpr(Inst, getImm());
3009 Inst.addOperand(MCOperand::createImm(0));
3010 return;
3013 // Otherwise, it's a normal memory reg+offset.
3014 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
3015 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3016 Inst.addOperand(MCOperand::createImm(Val));
3019 void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
3020 assert(N == 1 && "Invalid number of operands!");
3021 // This is container for the immediate that we will create the constant
3022 // pool from
3023 addExpr(Inst, getConstantPoolImm());
3024 return;
3027 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
3028 assert(N == 2 && "Invalid number of operands!");
3029 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3030 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3033 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
3034 assert(N == 2 && "Invalid number of operands!");
3035 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3036 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3039 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3040 assert(N == 3 && "Invalid number of operands!");
3041 unsigned Val =
3042 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
3043 Memory.ShiftImm, Memory.ShiftType);
3044 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3045 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3046 Inst.addOperand(MCOperand::createImm(Val));
3049 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
3050 assert(N == 3 && "Invalid number of operands!");
3051 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3052 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3053 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
3056 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
3057 assert(N == 2 && "Invalid number of operands!");
3058 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3059 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
3062 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
3063 assert(N == 2 && "Invalid number of operands!");
3064 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3065 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3066 Inst.addOperand(MCOperand::createImm(Val));
3069 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
3070 assert(N == 2 && "Invalid number of operands!");
3071 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
3072 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3073 Inst.addOperand(MCOperand::createImm(Val));
3076 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
3077 assert(N == 2 && "Invalid number of operands!");
3078 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
3079 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3080 Inst.addOperand(MCOperand::createImm(Val));
3083 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
3084 assert(N == 2 && "Invalid number of operands!");
3085 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
3086 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
3087 Inst.addOperand(MCOperand::createImm(Val));
3090 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
3091 assert(N == 1 && "Invalid number of operands!");
3092 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3093 assert(CE && "non-constant post-idx-imm8 operand!");
3094 int Imm = CE->getValue();
3095 bool isAdd = Imm >= 0;
3096 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3097 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
3098 Inst.addOperand(MCOperand::createImm(Imm));
3101 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
3102 assert(N == 1 && "Invalid number of operands!");
3103 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
3104 assert(CE && "non-constant post-idx-imm8s4 operand!");
3105 int Imm = CE->getValue();
3106 bool isAdd = Imm >= 0;
3107 if (Imm == std::numeric_limits<int32_t>::min()) Imm = 0;
3108 // Immediate is scaled by 4.
3109 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
3110 Inst.addOperand(MCOperand::createImm(Imm));
3113 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
3114 assert(N == 2 && "Invalid number of operands!");
3115 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3116 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
3119 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
3120 assert(N == 2 && "Invalid number of operands!");
3121 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
3122 // The sign, shift type, and shift amount are encoded in a single operand
3123 // using the AM2 encoding helpers.
3124 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3125 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3126 PostIdxReg.ShiftTy);
3127 Inst.addOperand(MCOperand::createImm(Imm));
3130 void addPowerTwoOperands(MCInst &Inst, unsigned N) const {
3131 assert(N == 1 && "Invalid number of operands!");
3132 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3133 Inst.addOperand(MCOperand::createImm(CE->getValue()));
3136 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
3137 assert(N == 1 && "Invalid number of operands!");
3138 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
3141 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
3142 assert(N == 1 && "Invalid number of operands!");
3143 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
3146 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
3147 assert(N == 1 && "Invalid number of operands!");
3148 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
3151 void addVecListOperands(MCInst &Inst, unsigned N) const {
3152 assert(N == 1 && "Invalid number of operands!");
3153 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3156 void addMVEVecListOperands(MCInst &Inst, unsigned N) const {
3157 assert(N == 1 && "Invalid number of operands!");
3159 // When we come here, the VectorList field will identify a range
3160 // of q-registers by its base register and length, and it will
3161 // have already been error-checked to be the expected length of
3162 // range and contain only q-regs in the range q0-q7. So we can
3163 // count on the base register being in the range q0-q6 (for 2
3164 // regs) or q0-q4 (for 4)
3166 // The MVE instructions taking a register range of this kind will
3167 // need an operand in the QQPR or QQQQPR class, representing the
3168 // entire range as a unit. So we must translate into that class,
3169 // by finding the index of the base register in the MQPR reg
3170 // class, and returning the super-register at the corresponding
3171 // index in the target class.
3173 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3174 const MCRegisterClass *RC_out = (VectorList.Count == 2) ?
3175 &ARMMCRegisterClasses[ARM::QQPRRegClassID] :
3176 &ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
3178 unsigned I, E = RC_out->getNumRegs();
3179 for (I = 0; I < E; I++)
3180 if (RC_in->getRegister(I) == VectorList.RegNum)
3181 break;
3182 assert(I < E && "Invalid vector list start register!");
3184 Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I)));
3187 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
3188 assert(N == 2 && "Invalid number of operands!");
3189 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
3190 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
3193 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
3194 assert(N == 1 && "Invalid number of operands!");
3195 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3198 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
3199 assert(N == 1 && "Invalid number of operands!");
3200 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3203 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
3204 assert(N == 1 && "Invalid number of operands!");
3205 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3208 void addVectorIndex64Operands(MCInst &Inst, unsigned N) const {
3209 assert(N == 1 && "Invalid number of operands!");
3210 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3213 void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const {
3214 assert(N == 1 && "Invalid number of operands!");
3215 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3218 void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const {
3219 assert(N == 1 && "Invalid number of operands!");
3220 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
3223 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
3224 assert(N == 1 && "Invalid number of operands!");
3225 // The immediate encodes the type of constant as well as the value.
3226 // Mask in that this is an i8 splat.
3227 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3228 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
3231 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
3232 assert(N == 1 && "Invalid number of operands!");
3233 // The immediate encodes the type of constant as well as the value.
3234 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3235 unsigned Value = CE->getValue();
3236 Value = ARM_AM::encodeNEONi16splat(Value);
3237 Inst.addOperand(MCOperand::createImm(Value));
3240 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
3241 assert(N == 1 && "Invalid number of operands!");
3242 // The immediate encodes the type of constant as well as the value.
3243 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3244 unsigned Value = CE->getValue();
3245 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3246 Inst.addOperand(MCOperand::createImm(Value));
3249 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
3250 assert(N == 1 && "Invalid number of operands!");
3251 // The immediate encodes the type of constant as well as the value.
3252 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3253 unsigned Value = CE->getValue();
3254 Value = ARM_AM::encodeNEONi32splat(Value);
3255 Inst.addOperand(MCOperand::createImm(Value));
3258 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
3259 assert(N == 1 && "Invalid number of operands!");
3260 // The immediate encodes the type of constant as well as the value.
3261 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3262 unsigned Value = CE->getValue();
3263 Value = ARM_AM::encodeNEONi32splat(~Value);
3264 Inst.addOperand(MCOperand::createImm(Value));
3267 void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const {
3268 // The immediate encodes the type of constant as well as the value.
3269 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3270 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
3271 Inst.getOpcode() == ARM::VMOVv16i8) &&
3272 "All instructions that wants to replicate non-zero byte "
3273 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
3274 unsigned Value = CE->getValue();
3275 if (Inv)
3276 Value = ~Value;
3277 unsigned B = Value & 0xff;
3278 B |= 0xe00; // cmode = 0b1110
3279 Inst.addOperand(MCOperand::createImm(B));
3282 void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3283 assert(N == 1 && "Invalid number of operands!");
3284 addNEONi8ReplicateOperands(Inst, true);
3287 static unsigned encodeNeonVMOVImmediate(unsigned Value) {
3288 if (Value >= 256 && Value <= 0xffff)
3289 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
3290 else if (Value > 0xffff && Value <= 0xffffff)
3291 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
3292 else if (Value > 0xffffff)
3293 Value = (Value >> 24) | 0x600;
3294 return Value;
3297 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
3298 assert(N == 1 && "Invalid number of operands!");
3299 // The immediate encodes the type of constant as well as the value.
3300 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3301 unsigned Value = encodeNeonVMOVImmediate(CE->getValue());
3302 Inst.addOperand(MCOperand::createImm(Value));
3305 void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const {
3306 assert(N == 1 && "Invalid number of operands!");
3307 addNEONi8ReplicateOperands(Inst, false);
3310 void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const {
3311 assert(N == 1 && "Invalid number of operands!");
3312 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3313 assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
3314 Inst.getOpcode() == ARM::VMOVv8i16 ||
3315 Inst.getOpcode() == ARM::VMVNv4i16 ||
3316 Inst.getOpcode() == ARM::VMVNv8i16) &&
3317 "All instructions that want to replicate non-zero half-word "
3318 "always must be replaced with V{MOV,MVN}v{4,8}i16.");
3319 uint64_t Value = CE->getValue();
3320 unsigned Elem = Value & 0xffff;
3321 if (Elem >= 256)
3322 Elem = (Elem >> 8) | 0x200;
3323 Inst.addOperand(MCOperand::createImm(Elem));
3326 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
3327 assert(N == 1 && "Invalid number of operands!");
3328 // The immediate encodes the type of constant as well as the value.
3329 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3330 unsigned Value = encodeNeonVMOVImmediate(~CE->getValue());
3331 Inst.addOperand(MCOperand::createImm(Value));
3334 void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const {
3335 assert(N == 1 && "Invalid number of operands!");
3336 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3337 assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
3338 Inst.getOpcode() == ARM::VMOVv4i32 ||
3339 Inst.getOpcode() == ARM::VMVNv2i32 ||
3340 Inst.getOpcode() == ARM::VMVNv4i32) &&
3341 "All instructions that want to replicate non-zero word "
3342 "always must be replaced with V{MOV,MVN}v{2,4}i32.");
3343 uint64_t Value = CE->getValue();
3344 unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff);
3345 Inst.addOperand(MCOperand::createImm(Elem));
3348 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
3349 assert(N == 1 && "Invalid number of operands!");
3350 // The immediate encodes the type of constant as well as the value.
3351 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3352 uint64_t Value = CE->getValue();
3353 unsigned Imm = 0;
3354 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
3355 Imm |= (Value & 1) << i;
3357 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
3360 void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const {
3361 assert(N == 1 && "Invalid number of operands!");
3362 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3363 Inst.addOperand(MCOperand::createImm(CE->getValue() / 90));
3366 void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
3367 assert(N == 1 && "Invalid number of operands!");
3368 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3369 Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
3372 void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
3373 assert(N == 1 && "Invalid number of operands!");
3374 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
3375 unsigned Imm = CE->getValue();
3376 assert((Imm == 48 || Imm == 64) && "Invalid saturate operand");
3377 Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
3380 void print(raw_ostream &OS) const override;
3382 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
3383 auto Op = std::make_unique<ARMOperand>(k_ITCondMask);
3384 Op->ITMask.Mask = Mask;
3385 Op->StartLoc = S;
3386 Op->EndLoc = S;
3387 return Op;
3390 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
3391 SMLoc S) {
3392 auto Op = std::make_unique<ARMOperand>(k_CondCode);
3393 Op->CC.Val = CC;
3394 Op->StartLoc = S;
3395 Op->EndLoc = S;
3396 return Op;
3399 static std::unique_ptr<ARMOperand> CreateVPTPred(ARMVCC::VPTCodes CC,
3400 SMLoc S) {
3401 auto Op = std::make_unique<ARMOperand>(k_VPTPred);
3402 Op->VCC.Val = CC;
3403 Op->StartLoc = S;
3404 Op->EndLoc = S;
3405 return Op;
3408 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
3409 auto Op = std::make_unique<ARMOperand>(k_CoprocNum);
3410 Op->Cop.Val = CopVal;
3411 Op->StartLoc = S;
3412 Op->EndLoc = S;
3413 return Op;
3416 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
3417 auto Op = std::make_unique<ARMOperand>(k_CoprocReg);
3418 Op->Cop.Val = CopVal;
3419 Op->StartLoc = S;
3420 Op->EndLoc = S;
3421 return Op;
3424 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
3425 SMLoc E) {
3426 auto Op = std::make_unique<ARMOperand>(k_CoprocOption);
3427 Op->Cop.Val = Val;
3428 Op->StartLoc = S;
3429 Op->EndLoc = E;
3430 return Op;
3433 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
3434 auto Op = std::make_unique<ARMOperand>(k_CCOut);
3435 Op->Reg.RegNum = RegNum;
3436 Op->StartLoc = S;
3437 Op->EndLoc = S;
3438 return Op;
3441 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
3442 auto Op = std::make_unique<ARMOperand>(k_Token);
3443 Op->Tok.Data = Str.data();
3444 Op->Tok.Length = Str.size();
3445 Op->StartLoc = S;
3446 Op->EndLoc = S;
3447 return Op;
3450 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
3451 SMLoc E) {
3452 auto Op = std::make_unique<ARMOperand>(k_Register);
3453 Op->Reg.RegNum = RegNum;
3454 Op->StartLoc = S;
3455 Op->EndLoc = E;
3456 return Op;
3459 static std::unique_ptr<ARMOperand>
3460 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3461 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
3462 SMLoc E) {
3463 auto Op = std::make_unique<ARMOperand>(k_ShiftedRegister);
3464 Op->RegShiftedReg.ShiftTy = ShTy;
3465 Op->RegShiftedReg.SrcReg = SrcReg;
3466 Op->RegShiftedReg.ShiftReg = ShiftReg;
3467 Op->RegShiftedReg.ShiftImm = ShiftImm;
3468 Op->StartLoc = S;
3469 Op->EndLoc = E;
3470 return Op;
3473 static std::unique_ptr<ARMOperand>
3474 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3475 unsigned ShiftImm, SMLoc S, SMLoc E) {
3476 auto Op = std::make_unique<ARMOperand>(k_ShiftedImmediate);
3477 Op->RegShiftedImm.ShiftTy = ShTy;
3478 Op->RegShiftedImm.SrcReg = SrcReg;
3479 Op->RegShiftedImm.ShiftImm = ShiftImm;
3480 Op->StartLoc = S;
3481 Op->EndLoc = E;
3482 return Op;
3485 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
3486 SMLoc S, SMLoc E) {
3487 auto Op = std::make_unique<ARMOperand>(k_ShifterImmediate);
3488 Op->ShifterImm.isASR = isASR;
3489 Op->ShifterImm.Imm = Imm;
3490 Op->StartLoc = S;
3491 Op->EndLoc = E;
3492 return Op;
3495 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
3496 SMLoc E) {
3497 auto Op = std::make_unique<ARMOperand>(k_RotateImmediate);
3498 Op->RotImm.Imm = Imm;
3499 Op->StartLoc = S;
3500 Op->EndLoc = E;
3501 return Op;
3504 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
3505 SMLoc S, SMLoc E) {
3506 auto Op = std::make_unique<ARMOperand>(k_ModifiedImmediate);
3507 Op->ModImm.Bits = Bits;
3508 Op->ModImm.Rot = Rot;
3509 Op->StartLoc = S;
3510 Op->EndLoc = E;
3511 return Op;
3514 static std::unique_ptr<ARMOperand>
3515 CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
3516 auto Op = std::make_unique<ARMOperand>(k_ConstantPoolImmediate);
3517 Op->Imm.Val = Val;
3518 Op->StartLoc = S;
3519 Op->EndLoc = E;
3520 return Op;
3523 static std::unique_ptr<ARMOperand>
3524 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
3525 auto Op = std::make_unique<ARMOperand>(k_BitfieldDescriptor);
3526 Op->Bitfield.LSB = LSB;
3527 Op->Bitfield.Width = Width;
3528 Op->StartLoc = S;
3529 Op->EndLoc = E;
3530 return Op;
3533 static std::unique_ptr<ARMOperand>
3534 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
3535 SMLoc StartLoc, SMLoc EndLoc) {
3536 assert(Regs.size() > 0 && "RegList contains no registers?");
3537 KindTy Kind = k_RegisterList;
3539 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
3540 Regs.front().second)) {
3541 if (Regs.back().second == ARM::VPR)
3542 Kind = k_FPDRegisterListWithVPR;
3543 else
3544 Kind = k_DPRRegisterList;
3545 } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
3546 Regs.front().second)) {
3547 if (Regs.back().second == ARM::VPR)
3548 Kind = k_FPSRegisterListWithVPR;
3549 else
3550 Kind = k_SPRRegisterList;
3553 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR)
3554 Kind = k_RegisterListWithAPSR;
3556 assert(std::is_sorted(Regs.begin(), Regs.end()) &&
3557 "Register list must be sorted by encoding");
3559 auto Op = std::make_unique<ARMOperand>(Kind);
3560 for (const auto &P : Regs)
3561 Op->Registers.push_back(P.second);
3563 Op->StartLoc = StartLoc;
3564 Op->EndLoc = EndLoc;
3565 return Op;
3568 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
3569 unsigned Count,
3570 bool isDoubleSpaced,
3571 SMLoc S, SMLoc E) {
3572 auto Op = std::make_unique<ARMOperand>(k_VectorList);
3573 Op->VectorList.RegNum = RegNum;
3574 Op->VectorList.Count = Count;
3575 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3576 Op->StartLoc = S;
3577 Op->EndLoc = E;
3578 return Op;
3581 static std::unique_ptr<ARMOperand>
3582 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
3583 SMLoc S, SMLoc E) {
3584 auto Op = std::make_unique<ARMOperand>(k_VectorListAllLanes);
3585 Op->VectorList.RegNum = RegNum;
3586 Op->VectorList.Count = Count;
3587 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3588 Op->StartLoc = S;
3589 Op->EndLoc = E;
3590 return Op;
3593 static std::unique_ptr<ARMOperand>
3594 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
3595 bool isDoubleSpaced, SMLoc S, SMLoc E) {
3596 auto Op = std::make_unique<ARMOperand>(k_VectorListIndexed);
3597 Op->VectorList.RegNum = RegNum;
3598 Op->VectorList.Count = Count;
3599 Op->VectorList.LaneIndex = Index;
3600 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
3601 Op->StartLoc = S;
3602 Op->EndLoc = E;
3603 return Op;
3606 static std::unique_ptr<ARMOperand>
3607 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
3608 auto Op = std::make_unique<ARMOperand>(k_VectorIndex);
3609 Op->VectorIndex.Val = Idx;
3610 Op->StartLoc = S;
3611 Op->EndLoc = E;
3612 return Op;
3615 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
3616 SMLoc E) {
3617 auto Op = std::make_unique<ARMOperand>(k_Immediate);
3618 Op->Imm.Val = Val;
3619 Op->StartLoc = S;
3620 Op->EndLoc = E;
3621 return Op;
3624 static std::unique_ptr<ARMOperand>
3625 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
3626 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
3627 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
3628 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
3629 auto Op = std::make_unique<ARMOperand>(k_Memory);
3630 Op->Memory.BaseRegNum = BaseRegNum;
3631 Op->Memory.OffsetImm = OffsetImm;
3632 Op->Memory.OffsetRegNum = OffsetRegNum;
3633 Op->Memory.ShiftType = ShiftType;
3634 Op->Memory.ShiftImm = ShiftImm;
3635 Op->Memory.Alignment = Alignment;
3636 Op->Memory.isNegative = isNegative;
3637 Op->StartLoc = S;
3638 Op->EndLoc = E;
3639 Op->AlignmentLoc = AlignmentLoc;
3640 return Op;
3643 static std::unique_ptr<ARMOperand>
3644 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3645 unsigned ShiftImm, SMLoc S, SMLoc E) {
3646 auto Op = std::make_unique<ARMOperand>(k_PostIndexRegister);
3647 Op->PostIdxReg.RegNum = RegNum;
3648 Op->PostIdxReg.isAdd = isAdd;
3649 Op->PostIdxReg.ShiftTy = ShiftTy;
3650 Op->PostIdxReg.ShiftImm = ShiftImm;
3651 Op->StartLoc = S;
3652 Op->EndLoc = E;
3653 return Op;
3656 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
3657 SMLoc S) {
3658 auto Op = std::make_unique<ARMOperand>(k_MemBarrierOpt);
3659 Op->MBOpt.Val = Opt;
3660 Op->StartLoc = S;
3661 Op->EndLoc = S;
3662 return Op;
3665 static std::unique_ptr<ARMOperand>
3666 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
3667 auto Op = std::make_unique<ARMOperand>(k_InstSyncBarrierOpt);
3668 Op->ISBOpt.Val = Opt;
3669 Op->StartLoc = S;
3670 Op->EndLoc = S;
3671 return Op;
3674 static std::unique_ptr<ARMOperand>
3675 CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) {
3676 auto Op = std::make_unique<ARMOperand>(k_TraceSyncBarrierOpt);
3677 Op->TSBOpt.Val = Opt;
3678 Op->StartLoc = S;
3679 Op->EndLoc = S;
3680 return Op;
3683 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
3684 SMLoc S) {
3685 auto Op = std::make_unique<ARMOperand>(k_ProcIFlags);
3686 Op->IFlags.Val = IFlags;
3687 Op->StartLoc = S;
3688 Op->EndLoc = S;
3689 return Op;
3692 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
3693 auto Op = std::make_unique<ARMOperand>(k_MSRMask);
3694 Op->MMask.Val = MMask;
3695 Op->StartLoc = S;
3696 Op->EndLoc = S;
3697 return Op;
3700 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
3701 auto Op = std::make_unique<ARMOperand>(k_BankedReg);
3702 Op->BankedReg.Val = Reg;
3703 Op->StartLoc = S;
3704 Op->EndLoc = S;
3705 return Op;
3709 } // end anonymous namespace.
3711 void ARMOperand::print(raw_ostream &OS) const {
3712 auto RegName = [](unsigned Reg) {
3713 if (Reg)
3714 return ARMInstPrinter::getRegisterName(Reg);
3715 else
3716 return "noreg";
3719 switch (Kind) {
3720 case k_CondCode:
3721 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
3722 break;
3723 case k_VPTPred:
3724 OS << "<ARMVCC::" << ARMVPTPredToString(getVPTPred()) << ">";
3725 break;
3726 case k_CCOut:
3727 OS << "<ccout " << RegName(getReg()) << ">";
3728 break;
3729 case k_ITCondMask: {
3730 static const char *const MaskStr[] = {
3731 "(invalid)", "(tttt)", "(ttt)", "(ttte)",
3732 "(tt)", "(ttet)", "(tte)", "(ttee)",
3733 "(t)", "(tett)", "(tet)", "(tete)",
3734 "(te)", "(teet)", "(tee)", "(teee)",
3736 assert((ITMask.Mask & 0xf) == ITMask.Mask);
3737 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
3738 break;
3740 case k_CoprocNum:
3741 OS << "<coprocessor number: " << getCoproc() << ">";
3742 break;
3743 case k_CoprocReg:
3744 OS << "<coprocessor register: " << getCoproc() << ">";
3745 break;
3746 case k_CoprocOption:
3747 OS << "<coprocessor option: " << CoprocOption.Val << ">";
3748 break;
3749 case k_MSRMask:
3750 OS << "<mask: " << getMSRMask() << ">";
3751 break;
3752 case k_BankedReg:
3753 OS << "<banked reg: " << getBankedReg() << ">";
3754 break;
3755 case k_Immediate:
3756 OS << *getImm();
3757 break;
3758 case k_MemBarrierOpt:
3759 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
3760 break;
3761 case k_InstSyncBarrierOpt:
3762 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
3763 break;
3764 case k_TraceSyncBarrierOpt:
3765 OS << "<ARM_TSB::" << TraceSyncBOptToString(getTraceSyncBarrierOpt()) << ">";
3766 break;
3767 case k_Memory:
3768 OS << "<memory";
3769 if (Memory.BaseRegNum)
3770 OS << " base:" << RegName(Memory.BaseRegNum);
3771 if (Memory.OffsetImm)
3772 OS << " offset-imm:" << *Memory.OffsetImm;
3773 if (Memory.OffsetRegNum)
3774 OS << " offset-reg:" << (Memory.isNegative ? "-" : "")
3775 << RegName(Memory.OffsetRegNum);
3776 if (Memory.ShiftType != ARM_AM::no_shift) {
3777 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3778 OS << " shift-imm:" << Memory.ShiftImm;
3780 if (Memory.Alignment)
3781 OS << " alignment:" << Memory.Alignment;
3782 OS << ">";
3783 break;
3784 case k_PostIndexRegister:
3785 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
3786 << RegName(PostIdxReg.RegNum);
3787 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3788 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3789 << PostIdxReg.ShiftImm;
3790 OS << ">";
3791 break;
3792 case k_ProcIFlags: {
3793 OS << "<ARM_PROC::";
3794 unsigned IFlags = getProcIFlags();
3795 for (int i=2; i >= 0; --i)
3796 if (IFlags & (1 << i))
3797 OS << ARM_PROC::IFlagsToString(1 << i);
3798 OS << ">";
3799 break;
3801 case k_Register:
3802 OS << "<register " << RegName(getReg()) << ">";
3803 break;
3804 case k_ShifterImmediate:
3805 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
3806 << " #" << ShifterImm.Imm << ">";
3807 break;
3808 case k_ShiftedRegister:
3809 OS << "<so_reg_reg " << RegName(RegShiftedReg.SrcReg) << " "
3810 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3811 << RegName(RegShiftedReg.ShiftReg) << ">";
3812 break;
3813 case k_ShiftedImmediate:
3814 OS << "<so_reg_imm " << RegName(RegShiftedImm.SrcReg) << " "
3815 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
3816 << RegShiftedImm.ShiftImm << ">";
3817 break;
3818 case k_RotateImmediate:
3819 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
3820 break;
3821 case k_ModifiedImmediate:
3822 OS << "<mod_imm #" << ModImm.Bits << ", #"
3823 << ModImm.Rot << ")>";
3824 break;
3825 case k_ConstantPoolImmediate:
3826 OS << "<constant_pool_imm #" << *getConstantPoolImm();
3827 break;
3828 case k_BitfieldDescriptor:
3829 OS << "<bitfield " << "lsb: " << Bitfield.LSB
3830 << ", width: " << Bitfield.Width << ">";
3831 break;
3832 case k_RegisterList:
3833 case k_RegisterListWithAPSR:
3834 case k_DPRRegisterList:
3835 case k_SPRRegisterList:
3836 case k_FPSRegisterListWithVPR:
3837 case k_FPDRegisterListWithVPR: {
3838 OS << "<register_list ";
3840 const SmallVectorImpl<unsigned> &RegList = getRegList();
3841 for (SmallVectorImpl<unsigned>::const_iterator
3842 I = RegList.begin(), E = RegList.end(); I != E; ) {
3843 OS << RegName(*I);
3844 if (++I < E) OS << ", ";
3847 OS << ">";
3848 break;
3850 case k_VectorList:
3851 OS << "<vector_list " << VectorList.Count << " * "
3852 << RegName(VectorList.RegNum) << ">";
3853 break;
3854 case k_VectorListAllLanes:
3855 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
3856 << RegName(VectorList.RegNum) << ">";
3857 break;
3858 case k_VectorListIndexed:
3859 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
3860 << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";
3861 break;
3862 case k_Token:
3863 OS << "'" << getToken() << "'";
3864 break;
3865 case k_VectorIndex:
3866 OS << "<vectorindex " << getVectorIndex() << ">";
3867 break;
3871 /// @name Auto-generated Match Functions
3872 /// {
3874 static unsigned MatchRegisterName(StringRef Name);
3876 /// }
3878 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
3879 SMLoc &StartLoc, SMLoc &EndLoc) {
3880 const AsmToken &Tok = getParser().getTok();
3881 StartLoc = Tok.getLoc();
3882 EndLoc = Tok.getEndLoc();
3883 RegNo = tryParseRegister();
3885 return (RegNo == (unsigned)-1);
3888 /// Try to parse a register name. The token must be an Identifier when called,
3889 /// and if it is a register name the token is eaten and the register number is
3890 /// returned. Otherwise return -1.
3891 int ARMAsmParser::tryParseRegister() {
3892 MCAsmParser &Parser = getParser();
3893 const AsmToken &Tok = Parser.getTok();
3894 if (Tok.isNot(AsmToken::Identifier)) return -1;
3896 std::string lowerCase = Tok.getString().lower();
3897 unsigned RegNum = MatchRegisterName(lowerCase);
3898 if (!RegNum) {
3899 RegNum = StringSwitch<unsigned>(lowerCase)
3900 .Case("r13", ARM::SP)
3901 .Case("r14", ARM::LR)
3902 .Case("r15", ARM::PC)
3903 .Case("ip", ARM::R12)
3904 // Additional register name aliases for 'gas' compatibility.
3905 .Case("a1", ARM::R0)
3906 .Case("a2", ARM::R1)
3907 .Case("a3", ARM::R2)
3908 .Case("a4", ARM::R3)
3909 .Case("v1", ARM::R4)
3910 .Case("v2", ARM::R5)
3911 .Case("v3", ARM::R6)
3912 .Case("v4", ARM::R7)
3913 .Case("v5", ARM::R8)
3914 .Case("v6", ARM::R9)
3915 .Case("v7", ARM::R10)
3916 .Case("v8", ARM::R11)
3917 .Case("sb", ARM::R9)
3918 .Case("sl", ARM::R10)
3919 .Case("fp", ARM::R11)
3920 .Default(0);
3922 if (!RegNum) {
3923 // Check for aliases registered via .req. Canonicalize to lower case.
3924 // That's more consistent since register names are case insensitive, and
3925 // it's how the original entry was passed in from MC/MCParser/AsmParser.
3926 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3927 // If no match, return failure.
3928 if (Entry == RegisterReqs.end())
3929 return -1;
3930 Parser.Lex(); // Eat identifier token.
3931 return Entry->getValue();
3934 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3935 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3936 return -1;
3938 Parser.Lex(); // Eat identifier token.
3940 return RegNum;
3943 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3944 // If a recoverable error occurs, return 1. If an irrecoverable error
3945 // occurs, return -1. An irrecoverable error is one where tokens have been
3946 // consumed in the process of trying to parse the shifter (i.e., when it is
3947 // indeed a shifter operand, but malformed).
3948 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3949 MCAsmParser &Parser = getParser();
3950 SMLoc S = Parser.getTok().getLoc();
3951 const AsmToken &Tok = Parser.getTok();
3952 if (Tok.isNot(AsmToken::Identifier))
3953 return -1;
3955 std::string lowerCase = Tok.getString().lower();
3956 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3957 .Case("asl", ARM_AM::lsl)
3958 .Case("lsl", ARM_AM::lsl)
3959 .Case("lsr", ARM_AM::lsr)
3960 .Case("asr", ARM_AM::asr)
3961 .Case("ror", ARM_AM::ror)
3962 .Case("rrx", ARM_AM::rrx)
3963 .Default(ARM_AM::no_shift);
3965 if (ShiftTy == ARM_AM::no_shift)
3966 return 1;
3968 Parser.Lex(); // Eat the operator.
3970 // The source register for the shift has already been added to the
3971 // operand list, so we need to pop it off and combine it into the shifted
3972 // register operand instead.
3973 std::unique_ptr<ARMOperand> PrevOp(
3974 (ARMOperand *)Operands.pop_back_val().release());
3975 if (!PrevOp->isReg())
3976 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3977 int SrcReg = PrevOp->getReg();
3979 SMLoc EndLoc;
3980 int64_t Imm = 0;
3981 int ShiftReg = 0;
3982 if (ShiftTy == ARM_AM::rrx) {
3983 // RRX Doesn't have an explicit shift amount. The encoder expects
3984 // the shift register to be the same as the source register. Seems odd,
3985 // but OK.
3986 ShiftReg = SrcReg;
3987 } else {
3988 // Figure out if this is shifted by a constant or a register (for non-RRX).
3989 if (Parser.getTok().is(AsmToken::Hash) ||
3990 Parser.getTok().is(AsmToken::Dollar)) {
3991 Parser.Lex(); // Eat hash.
3992 SMLoc ImmLoc = Parser.getTok().getLoc();
3993 const MCExpr *ShiftExpr = nullptr;
3994 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3995 Error(ImmLoc, "invalid immediate shift value");
3996 return -1;
3998 // The expression must be evaluatable as an immediate.
3999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
4000 if (!CE) {
4001 Error(ImmLoc, "invalid immediate shift value");
4002 return -1;
4004 // Range check the immediate.
4005 // lsl, ror: 0 <= imm <= 31
4006 // lsr, asr: 0 <= imm <= 32
4007 Imm = CE->getValue();
4008 if (Imm < 0 ||
4009 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4010 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4011 Error(ImmLoc, "immediate shift value out of range");
4012 return -1;
4014 // shift by zero is a nop. Always send it through as lsl.
4015 // ('as' compatibility)
4016 if (Imm == 0)
4017 ShiftTy = ARM_AM::lsl;
4018 } else if (Parser.getTok().is(AsmToken::Identifier)) {
4019 SMLoc L = Parser.getTok().getLoc();
4020 EndLoc = Parser.getTok().getEndLoc();
4021 ShiftReg = tryParseRegister();
4022 if (ShiftReg == -1) {
4023 Error(L, "expected immediate or register in shift operand");
4024 return -1;
4026 } else {
4027 Error(Parser.getTok().getLoc(),
4028 "expected immediate or register in shift operand");
4029 return -1;
4033 if (ShiftReg && ShiftTy != ARM_AM::rrx)
4034 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
4035 ShiftReg, Imm,
4036 S, EndLoc));
4037 else
4038 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
4039 S, EndLoc));
4041 return 0;
4044 /// Try to parse a register name. The token must be an Identifier when called.
4045 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
4046 /// if there is a "writeback". 'true' if it's not a register.
4048 /// TODO this is likely to change to allow different register types and or to
4049 /// parse for a specific register type.
4050 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
4051 MCAsmParser &Parser = getParser();
4052 SMLoc RegStartLoc = Parser.getTok().getLoc();
4053 SMLoc RegEndLoc = Parser.getTok().getEndLoc();
4054 int RegNo = tryParseRegister();
4055 if (RegNo == -1)
4056 return true;
4058 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc));
4060 const AsmToken &ExclaimTok = Parser.getTok();
4061 if (ExclaimTok.is(AsmToken::Exclaim)) {
4062 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
4063 ExclaimTok.getLoc()));
4064 Parser.Lex(); // Eat exclaim token
4065 return false;
4068 // Also check for an index operand. This is only legal for vector registers,
4069 // but that'll get caught OK in operand matching, so we don't need to
4070 // explicitly filter everything else out here.
4071 if (Parser.getTok().is(AsmToken::LBrac)) {
4072 SMLoc SIdx = Parser.getTok().getLoc();
4073 Parser.Lex(); // Eat left bracket token.
4075 const MCExpr *ImmVal;
4076 if (getParser().parseExpression(ImmVal))
4077 return true;
4078 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
4079 if (!MCE)
4080 return TokError("immediate value expected for vector index");
4082 if (Parser.getTok().isNot(AsmToken::RBrac))
4083 return Error(Parser.getTok().getLoc(), "']' expected");
4085 SMLoc E = Parser.getTok().getEndLoc();
4086 Parser.Lex(); // Eat right bracket token.
4088 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
4089 SIdx, E,
4090 getContext()));
4093 return false;
4096 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
4097 /// instruction with a symbolic operand name.
4098 /// We accept "crN" syntax for GAS compatibility.
4099 /// <operand-name> ::= <prefix><number>
4100 /// If CoprocOp is 'c', then:
4101 /// <prefix> ::= c | cr
4102 /// If CoprocOp is 'p', then :
4103 /// <prefix> ::= p
4104 /// <number> ::= integer in range [0, 15]
4105 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
4106 // Use the same layout as the tablegen'erated register name matcher. Ugly,
4107 // but efficient.
4108 if (Name.size() < 2 || Name[0] != CoprocOp)
4109 return -1;
4110 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
4112 switch (Name.size()) {
4113 default: return -1;
4114 case 1:
4115 switch (Name[0]) {
4116 default: return -1;
4117 case '0': return 0;
4118 case '1': return 1;
4119 case '2': return 2;
4120 case '3': return 3;
4121 case '4': return 4;
4122 case '5': return 5;
4123 case '6': return 6;
4124 case '7': return 7;
4125 case '8': return 8;
4126 case '9': return 9;
4128 case 2:
4129 if (Name[0] != '1')
4130 return -1;
4131 switch (Name[1]) {
4132 default: return -1;
4133 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
4134 // However, old cores (v5/v6) did use them in that way.
4135 case '0': return 10;
4136 case '1': return 11;
4137 case '2': return 12;
4138 case '3': return 13;
4139 case '4': return 14;
4140 case '5': return 15;
4145 /// parseITCondCode - Try to parse a condition code for an IT instruction.
4146 OperandMatchResultTy
4147 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
4148 MCAsmParser &Parser = getParser();
4149 SMLoc S = Parser.getTok().getLoc();
4150 const AsmToken &Tok = Parser.getTok();
4151 if (!Tok.is(AsmToken::Identifier))
4152 return MatchOperand_NoMatch;
4153 unsigned CC = ARMCondCodeFromString(Tok.getString());
4154 if (CC == ~0U)
4155 return MatchOperand_NoMatch;
4156 Parser.Lex(); // Eat the token.
4158 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
4160 return MatchOperand_Success;
4163 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
4164 /// token must be an Identifier when called, and if it is a coprocessor
4165 /// number, the token is eaten and the operand is added to the operand list.
4166 OperandMatchResultTy
4167 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
4168 MCAsmParser &Parser = getParser();
4169 SMLoc S = Parser.getTok().getLoc();
4170 const AsmToken &Tok = Parser.getTok();
4171 if (Tok.isNot(AsmToken::Identifier))
4172 return MatchOperand_NoMatch;
4174 int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
4175 if (Num == -1)
4176 return MatchOperand_NoMatch;
4177 if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
4178 return MatchOperand_NoMatch;
4180 Parser.Lex(); // Eat identifier token.
4181 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
4182 return MatchOperand_Success;
4185 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
4186 /// token must be an Identifier when called, and if it is a coprocessor
4187 /// number, the token is eaten and the operand is added to the operand list.
4188 OperandMatchResultTy
4189 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
4190 MCAsmParser &Parser = getParser();
4191 SMLoc S = Parser.getTok().getLoc();
4192 const AsmToken &Tok = Parser.getTok();
4193 if (Tok.isNot(AsmToken::Identifier))
4194 return MatchOperand_NoMatch;
4196 int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
4197 if (Reg == -1)
4198 return MatchOperand_NoMatch;
4200 Parser.Lex(); // Eat identifier token.
4201 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
4202 return MatchOperand_Success;
4205 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
4206 /// coproc_option : '{' imm0_255 '}'
4207 OperandMatchResultTy
4208 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
4209 MCAsmParser &Parser = getParser();
4210 SMLoc S = Parser.getTok().getLoc();
4212 // If this isn't a '{', this isn't a coprocessor immediate operand.
4213 if (Parser.getTok().isNot(AsmToken::LCurly))
4214 return MatchOperand_NoMatch;
4215 Parser.Lex(); // Eat the '{'
4217 const MCExpr *Expr;
4218 SMLoc Loc = Parser.getTok().getLoc();
4219 if (getParser().parseExpression(Expr)) {
4220 Error(Loc, "illegal expression");
4221 return MatchOperand_ParseFail;
4223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4224 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
4225 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
4226 return MatchOperand_ParseFail;
4228 int Val = CE->getValue();
4230 // Check for and consume the closing '}'
4231 if (Parser.getTok().isNot(AsmToken::RCurly))
4232 return MatchOperand_ParseFail;
4233 SMLoc E = Parser.getTok().getEndLoc();
4234 Parser.Lex(); // Eat the '}'
4236 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
4237 return MatchOperand_Success;
4240 // For register list parsing, we need to map from raw GPR register numbering
4241 // to the enumeration values. The enumeration values aren't sorted by
4242 // register number due to our using "sp", "lr" and "pc" as canonical names.
4243 static unsigned getNextRegister(unsigned Reg) {
4244 // If this is a GPR, we need to do it manually, otherwise we can rely
4245 // on the sort ordering of the enumeration since the other reg-classes
4246 // are sane.
4247 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4248 return Reg + 1;
4249 switch(Reg) {
4250 default: llvm_unreachable("Invalid GPR number!");
4251 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
4252 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
4253 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
4254 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
4255 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
4256 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
4257 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
4258 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
4262 // Insert an <Encoding, Register> pair in an ordered vector. Return true on
4263 // success, or false, if duplicate encoding found.
4264 static bool
4265 insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
4266 unsigned Enc, unsigned Reg) {
4267 Regs.emplace_back(Enc, Reg);
4268 for (auto I = Regs.rbegin(), J = I + 1, E = Regs.rend(); J != E; ++I, ++J) {
4269 if (J->first == Enc) {
4270 Regs.erase(J.base());
4271 return false;
4273 if (J->first < Enc)
4274 break;
4275 std::swap(*I, *J);
4277 return true;
4280 /// Parse a register list.
4281 bool ARMAsmParser::parseRegisterList(OperandVector &Operands,
4282 bool EnforceOrder) {
4283 MCAsmParser &Parser = getParser();
4284 if (Parser.getTok().isNot(AsmToken::LCurly))
4285 return TokError("Token is not a Left Curly Brace");
4286 SMLoc S = Parser.getTok().getLoc();
4287 Parser.Lex(); // Eat '{' token.
4288 SMLoc RegLoc = Parser.getTok().getLoc();
4290 // Check the first register in the list to see what register class
4291 // this is a list of.
4292 int Reg = tryParseRegister();
4293 if (Reg == -1)
4294 return Error(RegLoc, "register expected");
4296 // The reglist instructions have at most 16 registers, so reserve
4297 // space for that many.
4298 int EReg = 0;
4299 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
4301 // Allow Q regs and just interpret them as the two D sub-registers.
4302 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4303 Reg = getDRegFromQReg(Reg);
4304 EReg = MRI->getEncodingValue(Reg);
4305 Registers.emplace_back(EReg, Reg);
4306 ++Reg;
4308 const MCRegisterClass *RC;
4309 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4310 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
4311 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
4312 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
4313 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
4314 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
4315 else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4316 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4317 else
4318 return Error(RegLoc, "invalid register in register list");
4320 // Store the register.
4321 EReg = MRI->getEncodingValue(Reg);
4322 Registers.emplace_back(EReg, Reg);
4324 // This starts immediately after the first register token in the list,
4325 // so we can see either a comma or a minus (range separator) as a legal
4326 // next token.
4327 while (Parser.getTok().is(AsmToken::Comma) ||
4328 Parser.getTok().is(AsmToken::Minus)) {
4329 if (Parser.getTok().is(AsmToken::Minus)) {
4330 Parser.Lex(); // Eat the minus.
4331 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4332 int EndReg = tryParseRegister();
4333 if (EndReg == -1)
4334 return Error(AfterMinusLoc, "register expected");
4335 // Allow Q regs and just interpret them as the two D sub-registers.
4336 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4337 EndReg = getDRegFromQReg(EndReg) + 1;
4338 // If the register is the same as the start reg, there's nothing
4339 // more to do.
4340 if (Reg == EndReg)
4341 continue;
4342 // The register must be in the same register class as the first.
4343 if (!RC->contains(EndReg))
4344 return Error(AfterMinusLoc, "invalid register in register list");
4345 // Ranges must go from low to high.
4346 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
4347 return Error(AfterMinusLoc, "bad range in register list");
4349 // Add all the registers in the range to the register list.
4350 while (Reg != EndReg) {
4351 Reg = getNextRegister(Reg);
4352 EReg = MRI->getEncodingValue(Reg);
4353 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4354 Warning(AfterMinusLoc, StringRef("duplicated register (") +
4355 ARMInstPrinter::getRegisterName(Reg) +
4356 ") in register list");
4359 continue;
4361 Parser.Lex(); // Eat the comma.
4362 RegLoc = Parser.getTok().getLoc();
4363 int OldReg = Reg;
4364 const AsmToken RegTok = Parser.getTok();
4365 Reg = tryParseRegister();
4366 if (Reg == -1)
4367 return Error(RegLoc, "register expected");
4368 // Allow Q regs and just interpret them as the two D sub-registers.
4369 bool isQReg = false;
4370 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4371 Reg = getDRegFromQReg(Reg);
4372 isQReg = true;
4374 if (!RC->contains(Reg) &&
4375 RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() &&
4376 ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) {
4377 // switch the register classes, as GPRwithAPSRnospRegClassID is a partial
4378 // subset of GPRRegClassId except it contains APSR as well.
4379 RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID];
4381 if (Reg == ARM::VPR &&
4382 (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] ||
4383 RC == &ARMMCRegisterClasses[ARM::DPRRegClassID] ||
4384 RC == &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID])) {
4385 RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID];
4386 EReg = MRI->getEncodingValue(Reg);
4387 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4388 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4389 ") in register list");
4391 continue;
4393 // The register must be in the same register class as the first.
4394 if (!RC->contains(Reg))
4395 return Error(RegLoc, "invalid register in register list");
4396 // In most cases, the list must be monotonically increasing. An
4397 // exception is CLRM, which is order-independent anyway, so
4398 // there's no potential for confusion if you write clrm {r2,r1}
4399 // instead of clrm {r1,r2}.
4400 if (EnforceOrder &&
4401 MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
4402 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
4403 Warning(RegLoc, "register list not in ascending order");
4404 else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg))
4405 return Error(RegLoc, "register list not in ascending order");
4407 // VFP register lists must also be contiguous.
4408 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
4409 RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] &&
4410 Reg != OldReg + 1)
4411 return Error(RegLoc, "non-contiguous register range");
4412 EReg = MRI->getEncodingValue(Reg);
4413 if (!insertNoDuplicates(Registers, EReg, Reg)) {
4414 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
4415 ") in register list");
4417 if (isQReg) {
4418 EReg = MRI->getEncodingValue(++Reg);
4419 Registers.emplace_back(EReg, Reg);
4423 if (Parser.getTok().isNot(AsmToken::RCurly))
4424 return Error(Parser.getTok().getLoc(), "'}' expected");
4425 SMLoc E = Parser.getTok().getEndLoc();
4426 Parser.Lex(); // Eat '}' token.
4428 // Push the register list operand.
4429 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
4431 // The ARM system instruction variants for LDM/STM have a '^' token here.
4432 if (Parser.getTok().is(AsmToken::Caret)) {
4433 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
4434 Parser.Lex(); // Eat '^' token.
4437 return false;
4440 // Helper function to parse the lane index for vector lists.
4441 OperandMatchResultTy ARMAsmParser::
4442 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
4443 MCAsmParser &Parser = getParser();
4444 Index = 0; // Always return a defined index value.
4445 if (Parser.getTok().is(AsmToken::LBrac)) {
4446 Parser.Lex(); // Eat the '['.
4447 if (Parser.getTok().is(AsmToken::RBrac)) {
4448 // "Dn[]" is the 'all lanes' syntax.
4449 LaneKind = AllLanes;
4450 EndLoc = Parser.getTok().getEndLoc();
4451 Parser.Lex(); // Eat the ']'.
4452 return MatchOperand_Success;
4455 // There's an optional '#' token here. Normally there wouldn't be, but
4456 // inline assemble puts one in, and it's friendly to accept that.
4457 if (Parser.getTok().is(AsmToken::Hash))
4458 Parser.Lex(); // Eat '#' or '$'.
4460 const MCExpr *LaneIndex;
4461 SMLoc Loc = Parser.getTok().getLoc();
4462 if (getParser().parseExpression(LaneIndex)) {
4463 Error(Loc, "illegal expression");
4464 return MatchOperand_ParseFail;
4466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
4467 if (!CE) {
4468 Error(Loc, "lane index must be empty or an integer");
4469 return MatchOperand_ParseFail;
4471 if (Parser.getTok().isNot(AsmToken::RBrac)) {
4472 Error(Parser.getTok().getLoc(), "']' expected");
4473 return MatchOperand_ParseFail;
4475 EndLoc = Parser.getTok().getEndLoc();
4476 Parser.Lex(); // Eat the ']'.
4477 int64_t Val = CE->getValue();
4479 // FIXME: Make this range check context sensitive for .8, .16, .32.
4480 if (Val < 0 || Val > 7) {
4481 Error(Parser.getTok().getLoc(), "lane index out of range");
4482 return MatchOperand_ParseFail;
4484 Index = Val;
4485 LaneKind = IndexedLane;
4486 return MatchOperand_Success;
4488 LaneKind = NoLanes;
4489 return MatchOperand_Success;
4492 // parse a vector register list
4493 OperandMatchResultTy
4494 ARMAsmParser::parseVectorList(OperandVector &Operands) {
4495 MCAsmParser &Parser = getParser();
4496 VectorLaneTy LaneKind;
4497 unsigned LaneIndex;
4498 SMLoc S = Parser.getTok().getLoc();
4499 // As an extension (to match gas), support a plain D register or Q register
4500 // (without encosing curly braces) as a single or double entry list,
4501 // respectively.
4502 if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) {
4503 SMLoc E = Parser.getTok().getEndLoc();
4504 int Reg = tryParseRegister();
4505 if (Reg == -1)
4506 return MatchOperand_NoMatch;
4507 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
4508 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4509 if (Res != MatchOperand_Success)
4510 return Res;
4511 switch (LaneKind) {
4512 case NoLanes:
4513 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
4514 break;
4515 case AllLanes:
4516 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
4517 S, E));
4518 break;
4519 case IndexedLane:
4520 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
4521 LaneIndex,
4522 false, S, E));
4523 break;
4525 return MatchOperand_Success;
4527 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4528 Reg = getDRegFromQReg(Reg);
4529 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
4530 if (Res != MatchOperand_Success)
4531 return Res;
4532 switch (LaneKind) {
4533 case NoLanes:
4534 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4535 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4536 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
4537 break;
4538 case AllLanes:
4539 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
4540 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
4541 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
4542 S, E));
4543 break;
4544 case IndexedLane:
4545 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
4546 LaneIndex,
4547 false, S, E));
4548 break;
4550 return MatchOperand_Success;
4552 Error(S, "vector register expected");
4553 return MatchOperand_ParseFail;
4556 if (Parser.getTok().isNot(AsmToken::LCurly))
4557 return MatchOperand_NoMatch;
4559 Parser.Lex(); // Eat '{' token.
4560 SMLoc RegLoc = Parser.getTok().getLoc();
4562 int Reg = tryParseRegister();
4563 if (Reg == -1) {
4564 Error(RegLoc, "register expected");
4565 return MatchOperand_ParseFail;
4567 unsigned Count = 1;
4568 int Spacing = 0;
4569 unsigned FirstReg = Reg;
4571 if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4572 Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
4573 return MatchOperand_ParseFail;
4575 // The list is of D registers, but we also allow Q regs and just interpret
4576 // them as the two D sub-registers.
4577 else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4578 FirstReg = Reg = getDRegFromQReg(Reg);
4579 Spacing = 1; // double-spacing requires explicit D registers, otherwise
4580 // it's ambiguous with four-register single spaced.
4581 ++Reg;
4582 ++Count;
4585 SMLoc E;
4586 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
4587 return MatchOperand_ParseFail;
4589 while (Parser.getTok().is(AsmToken::Comma) ||
4590 Parser.getTok().is(AsmToken::Minus)) {
4591 if (Parser.getTok().is(AsmToken::Minus)) {
4592 if (!Spacing)
4593 Spacing = 1; // Register range implies a single spaced list.
4594 else if (Spacing == 2) {
4595 Error(Parser.getTok().getLoc(),
4596 "sequential registers in double spaced list");
4597 return MatchOperand_ParseFail;
4599 Parser.Lex(); // Eat the minus.
4600 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
4601 int EndReg = tryParseRegister();
4602 if (EndReg == -1) {
4603 Error(AfterMinusLoc, "register expected");
4604 return MatchOperand_ParseFail;
4606 // Allow Q regs and just interpret them as the two D sub-registers.
4607 if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
4608 EndReg = getDRegFromQReg(EndReg) + 1;
4609 // If the register is the same as the start reg, there's nothing
4610 // more to do.
4611 if (Reg == EndReg)
4612 continue;
4613 // The register must be in the same register class as the first.
4614 if ((hasMVE() &&
4615 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
4616 (!hasMVE() &&
4617 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
4618 Error(AfterMinusLoc, "invalid register in register list");
4619 return MatchOperand_ParseFail;
4621 // Ranges must go from low to high.
4622 if (Reg > EndReg) {
4623 Error(AfterMinusLoc, "bad range in register list");
4624 return MatchOperand_ParseFail;
4626 // Parse the lane specifier if present.
4627 VectorLaneTy NextLaneKind;
4628 unsigned NextLaneIndex;
4629 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4630 MatchOperand_Success)
4631 return MatchOperand_ParseFail;
4632 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4633 Error(AfterMinusLoc, "mismatched lane index in register list");
4634 return MatchOperand_ParseFail;
4637 // Add all the registers in the range to the register list.
4638 Count += EndReg - Reg;
4639 Reg = EndReg;
4640 continue;
4642 Parser.Lex(); // Eat the comma.
4643 RegLoc = Parser.getTok().getLoc();
4644 int OldReg = Reg;
4645 Reg = tryParseRegister();
4646 if (Reg == -1) {
4647 Error(RegLoc, "register expected");
4648 return MatchOperand_ParseFail;
4651 if (hasMVE()) {
4652 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
4653 Error(RegLoc, "vector register in range Q0-Q7 expected");
4654 return MatchOperand_ParseFail;
4656 Spacing = 1;
4658 // vector register lists must be contiguous.
4659 // It's OK to use the enumeration values directly here rather, as the
4660 // VFP register classes have the enum sorted properly.
4662 // The list is of D registers, but we also allow Q regs and just interpret
4663 // them as the two D sub-registers.
4664 else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
4665 if (!Spacing)
4666 Spacing = 1; // Register range implies a single spaced list.
4667 else if (Spacing == 2) {
4668 Error(RegLoc,
4669 "invalid register in double-spaced list (must be 'D' register')");
4670 return MatchOperand_ParseFail;
4672 Reg = getDRegFromQReg(Reg);
4673 if (Reg != OldReg + 1) {
4674 Error(RegLoc, "non-contiguous register range");
4675 return MatchOperand_ParseFail;
4677 ++Reg;
4678 Count += 2;
4679 // Parse the lane specifier if present.
4680 VectorLaneTy NextLaneKind;
4681 unsigned NextLaneIndex;
4682 SMLoc LaneLoc = Parser.getTok().getLoc();
4683 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
4684 MatchOperand_Success)
4685 return MatchOperand_ParseFail;
4686 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4687 Error(LaneLoc, "mismatched lane index in register list");
4688 return MatchOperand_ParseFail;
4690 continue;
4692 // Normal D register.
4693 // Figure out the register spacing (single or double) of the list if
4694 // we don't know it already.
4695 if (!Spacing)
4696 Spacing = 1 + (Reg == OldReg + 2);
4698 // Just check that it's contiguous and keep going.
4699 if (Reg != OldReg + Spacing) {
4700 Error(RegLoc, "non-contiguous register range");
4701 return MatchOperand_ParseFail;
4703 ++Count;
4704 // Parse the lane specifier if present.
4705 VectorLaneTy NextLaneKind;
4706 unsigned NextLaneIndex;
4707 SMLoc EndLoc = Parser.getTok().getLoc();
4708 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
4709 return MatchOperand_ParseFail;
4710 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
4711 Error(EndLoc, "mismatched lane index in register list");
4712 return MatchOperand_ParseFail;
4716 if (Parser.getTok().isNot(AsmToken::RCurly)) {
4717 Error(Parser.getTok().getLoc(), "'}' expected");
4718 return MatchOperand_ParseFail;
4720 E = Parser.getTok().getEndLoc();
4721 Parser.Lex(); // Eat '}' token.
4723 switch (LaneKind) {
4724 case NoLanes:
4725 case AllLanes: {
4726 // Two-register operands have been converted to the
4727 // composite register classes.
4728 if (Count == 2 && !hasMVE()) {
4729 const MCRegisterClass *RC = (Spacing == 1) ?
4730 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
4731 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
4732 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
4734 auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList :
4735 ARMOperand::CreateVectorListAllLanes);
4736 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E));
4737 break;
4739 case IndexedLane:
4740 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
4741 LaneIndex,
4742 (Spacing == 2),
4743 S, E));
4744 break;
4746 return MatchOperand_Success;
4749 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
4750 OperandMatchResultTy
4751 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
4752 MCAsmParser &Parser = getParser();
4753 SMLoc S = Parser.getTok().getLoc();
4754 const AsmToken &Tok = Parser.getTok();
4755 unsigned Opt;
4757 if (Tok.is(AsmToken::Identifier)) {
4758 StringRef OptStr = Tok.getString();
4760 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
4761 .Case("sy", ARM_MB::SY)
4762 .Case("st", ARM_MB::ST)
4763 .Case("ld", ARM_MB::LD)
4764 .Case("sh", ARM_MB::ISH)
4765 .Case("ish", ARM_MB::ISH)
4766 .Case("shst", ARM_MB::ISHST)
4767 .Case("ishst", ARM_MB::ISHST)
4768 .Case("ishld", ARM_MB::ISHLD)
4769 .Case("nsh", ARM_MB::NSH)
4770 .Case("un", ARM_MB::NSH)
4771 .Case("nshst", ARM_MB::NSHST)
4772 .Case("nshld", ARM_MB::NSHLD)
4773 .Case("unst", ARM_MB::NSHST)
4774 .Case("osh", ARM_MB::OSH)
4775 .Case("oshst", ARM_MB::OSHST)
4776 .Case("oshld", ARM_MB::OSHLD)
4777 .Default(~0U);
4779 // ishld, oshld, nshld and ld are only available from ARMv8.
4780 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
4781 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
4782 Opt = ~0U;
4784 if (Opt == ~0U)
4785 return MatchOperand_NoMatch;
4787 Parser.Lex(); // Eat identifier token.
4788 } else if (Tok.is(AsmToken::Hash) ||
4789 Tok.is(AsmToken::Dollar) ||
4790 Tok.is(AsmToken::Integer)) {
4791 if (Parser.getTok().isNot(AsmToken::Integer))
4792 Parser.Lex(); // Eat '#' or '$'.
4793 SMLoc Loc = Parser.getTok().getLoc();
4795 const MCExpr *MemBarrierID;
4796 if (getParser().parseExpression(MemBarrierID)) {
4797 Error(Loc, "illegal expression");
4798 return MatchOperand_ParseFail;
4801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
4802 if (!CE) {
4803 Error(Loc, "constant expression expected");
4804 return MatchOperand_ParseFail;
4807 int Val = CE->getValue();
4808 if (Val & ~0xf) {
4809 Error(Loc, "immediate value out of range");
4810 return MatchOperand_ParseFail;
4813 Opt = ARM_MB::RESERVED_0 + Val;
4814 } else
4815 return MatchOperand_ParseFail;
4817 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
4818 return MatchOperand_Success;
4821 OperandMatchResultTy
4822 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
4823 MCAsmParser &Parser = getParser();
4824 SMLoc S = Parser.getTok().getLoc();
4825 const AsmToken &Tok = Parser.getTok();
4827 if (Tok.isNot(AsmToken::Identifier))
4828 return MatchOperand_NoMatch;
4830 if (!Tok.getString().equals_lower("csync"))
4831 return MatchOperand_NoMatch;
4833 Parser.Lex(); // Eat identifier token.
4835 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
4836 return MatchOperand_Success;
4839 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
4840 OperandMatchResultTy
4841 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
4842 MCAsmParser &Parser = getParser();
4843 SMLoc S = Parser.getTok().getLoc();
4844 const AsmToken &Tok = Parser.getTok();
4845 unsigned Opt;
4847 if (Tok.is(AsmToken::Identifier)) {
4848 StringRef OptStr = Tok.getString();
4850 if (OptStr.equals_lower("sy"))
4851 Opt = ARM_ISB::SY;
4852 else
4853 return MatchOperand_NoMatch;
4855 Parser.Lex(); // Eat identifier token.
4856 } else if (Tok.is(AsmToken::Hash) ||
4857 Tok.is(AsmToken::Dollar) ||
4858 Tok.is(AsmToken::Integer)) {
4859 if (Parser.getTok().isNot(AsmToken::Integer))
4860 Parser.Lex(); // Eat '#' or '$'.
4861 SMLoc Loc = Parser.getTok().getLoc();
4863 const MCExpr *ISBarrierID;
4864 if (getParser().parseExpression(ISBarrierID)) {
4865 Error(Loc, "illegal expression");
4866 return MatchOperand_ParseFail;
4869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
4870 if (!CE) {
4871 Error(Loc, "constant expression expected");
4872 return MatchOperand_ParseFail;
4875 int Val = CE->getValue();
4876 if (Val & ~0xf) {
4877 Error(Loc, "immediate value out of range");
4878 return MatchOperand_ParseFail;
4881 Opt = ARM_ISB::RESERVED_0 + Val;
4882 } else
4883 return MatchOperand_ParseFail;
4885 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
4886 (ARM_ISB::InstSyncBOpt)Opt, S));
4887 return MatchOperand_Success;
4891 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
4892 OperandMatchResultTy
4893 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
4894 MCAsmParser &Parser = getParser();
4895 SMLoc S = Parser.getTok().getLoc();
4896 const AsmToken &Tok = Parser.getTok();
4897 if (!Tok.is(AsmToken::Identifier))
4898 return MatchOperand_NoMatch;
4899 StringRef IFlagsStr = Tok.getString();
4901 // An iflags string of "none" is interpreted to mean that none of the AIF
4902 // bits are set. Not a terribly useful instruction, but a valid encoding.
4903 unsigned IFlags = 0;
4904 if (IFlagsStr != "none") {
4905 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
4906 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1).lower())
4907 .Case("a", ARM_PROC::A)
4908 .Case("i", ARM_PROC::I)
4909 .Case("f", ARM_PROC::F)
4910 .Default(~0U);
4912 // If some specific iflag is already set, it means that some letter is
4913 // present more than once, this is not acceptable.
4914 if (Flag == ~0U || (IFlags & Flag))
4915 return MatchOperand_NoMatch;
4917 IFlags |= Flag;
4921 Parser.Lex(); // Eat identifier token.
4922 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
4923 return MatchOperand_Success;
4926 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
4927 OperandMatchResultTy
4928 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4929 MCAsmParser &Parser = getParser();
4930 SMLoc S = Parser.getTok().getLoc();
4931 const AsmToken &Tok = Parser.getTok();
4933 if (Tok.is(AsmToken::Integer)) {
4934 int64_t Val = Tok.getIntVal();
4935 if (Val > 255 || Val < 0) {
4936 return MatchOperand_NoMatch;
4938 unsigned SYSmvalue = Val & 0xFF;
4939 Parser.Lex();
4940 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4941 return MatchOperand_Success;
4944 if (!Tok.is(AsmToken::Identifier))
4945 return MatchOperand_NoMatch;
4946 StringRef Mask = Tok.getString();
4948 if (isMClass()) {
4949 auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
4950 if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
4951 return MatchOperand_NoMatch;
4953 unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
4955 Parser.Lex(); // Eat identifier token.
4956 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
4957 return MatchOperand_Success;
4960 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4961 size_t Start = 0, Next = Mask.find('_');
4962 StringRef Flags = "";
4963 std::string SpecReg = Mask.slice(Start, Next).lower();
4964 if (Next != StringRef::npos)
4965 Flags = Mask.slice(Next+1, Mask.size());
4967 // FlagsVal contains the complete mask:
4968 // 3-0: Mask
4969 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4970 unsigned FlagsVal = 0;
4972 if (SpecReg == "apsr") {
4973 FlagsVal = StringSwitch<unsigned>(Flags)
4974 .Case("nzcvq", 0x8) // same as CPSR_f
4975 .Case("g", 0x4) // same as CPSR_s
4976 .Case("nzcvqg", 0xc) // same as CPSR_fs
4977 .Default(~0U);
4979 if (FlagsVal == ~0U) {
4980 if (!Flags.empty())
4981 return MatchOperand_NoMatch;
4982 else
4983 FlagsVal = 8; // No flag
4985 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4986 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4987 if (Flags == "all" || Flags == "")
4988 Flags = "fc";
4989 for (int i = 0, e = Flags.size(); i != e; ++i) {
4990 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4991 .Case("c", 1)
4992 .Case("x", 2)
4993 .Case("s", 4)
4994 .Case("f", 8)
4995 .Default(~0U);
4997 // If some specific flag is already set, it means that some letter is
4998 // present more than once, this is not acceptable.
4999 if (Flag == ~0U || (FlagsVal & Flag))
5000 return MatchOperand_NoMatch;
5001 FlagsVal |= Flag;
5003 } else // No match for special register.
5004 return MatchOperand_NoMatch;
5006 // Special register without flags is NOT equivalent to "fc" flags.
5007 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
5008 // two lines would enable gas compatibility at the expense of breaking
5009 // round-tripping.
5011 // if (!FlagsVal)
5012 // FlagsVal = 0x9;
5014 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
5015 if (SpecReg == "spsr")
5016 FlagsVal |= 16;
5018 Parser.Lex(); // Eat identifier token.
5019 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
5020 return MatchOperand_Success;
5023 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
5024 /// use in the MRS/MSR instructions added to support virtualization.
5025 OperandMatchResultTy
5026 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
5027 MCAsmParser &Parser = getParser();
5028 SMLoc S = Parser.getTok().getLoc();
5029 const AsmToken &Tok = Parser.getTok();
5030 if (!Tok.is(AsmToken::Identifier))
5031 return MatchOperand_NoMatch;
5032 StringRef RegName = Tok.getString();
5034 auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
5035 if (!TheReg)
5036 return MatchOperand_NoMatch;
5037 unsigned Encoding = TheReg->Encoding;
5039 Parser.Lex(); // Eat identifier token.
5040 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
5041 return MatchOperand_Success;
5044 OperandMatchResultTy
5045 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
5046 int High) {
5047 MCAsmParser &Parser = getParser();
5048 const AsmToken &Tok = Parser.getTok();
5049 if (Tok.isNot(AsmToken::Identifier)) {
5050 Error(Parser.getTok().getLoc(), Op + " operand expected.");
5051 return MatchOperand_ParseFail;
5053 StringRef ShiftName = Tok.getString();
5054 std::string LowerOp = Op.lower();
5055 std::string UpperOp = Op.upper();
5056 if (ShiftName != LowerOp && ShiftName != UpperOp) {
5057 Error(Parser.getTok().getLoc(), Op + " operand expected.");
5058 return MatchOperand_ParseFail;
5060 Parser.Lex(); // Eat shift type token.
5062 // There must be a '#' and a shift amount.
5063 if (Parser.getTok().isNot(AsmToken::Hash) &&
5064 Parser.getTok().isNot(AsmToken::Dollar)) {
5065 Error(Parser.getTok().getLoc(), "'#' expected");
5066 return MatchOperand_ParseFail;
5068 Parser.Lex(); // Eat hash token.
5070 const MCExpr *ShiftAmount;
5071 SMLoc Loc = Parser.getTok().getLoc();
5072 SMLoc EndLoc;
5073 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5074 Error(Loc, "illegal expression");
5075 return MatchOperand_ParseFail;
5077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5078 if (!CE) {
5079 Error(Loc, "constant expression expected");
5080 return MatchOperand_ParseFail;
5082 int Val = CE->getValue();
5083 if (Val < Low || Val > High) {
5084 Error(Loc, "immediate value out of range");
5085 return MatchOperand_ParseFail;
5088 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
5090 return MatchOperand_Success;
5093 OperandMatchResultTy
5094 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
5095 MCAsmParser &Parser = getParser();
5096 const AsmToken &Tok = Parser.getTok();
5097 SMLoc S = Tok.getLoc();
5098 if (Tok.isNot(AsmToken::Identifier)) {
5099 Error(S, "'be' or 'le' operand expected");
5100 return MatchOperand_ParseFail;
5102 int Val = StringSwitch<int>(Tok.getString().lower())
5103 .Case("be", 1)
5104 .Case("le", 0)
5105 .Default(-1);
5106 Parser.Lex(); // Eat the token.
5108 if (Val == -1) {
5109 Error(S, "'be' or 'le' operand expected");
5110 return MatchOperand_ParseFail;
5112 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
5113 getContext()),
5114 S, Tok.getEndLoc()));
5115 return MatchOperand_Success;
5118 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
5119 /// instructions. Legal values are:
5120 /// lsl #n 'n' in [0,31]
5121 /// asr #n 'n' in [1,32]
5122 /// n == 32 encoded as n == 0.
5123 OperandMatchResultTy
5124 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
5125 MCAsmParser &Parser = getParser();
5126 const AsmToken &Tok = Parser.getTok();
5127 SMLoc S = Tok.getLoc();
5128 if (Tok.isNot(AsmToken::Identifier)) {
5129 Error(S, "shift operator 'asr' or 'lsl' expected");
5130 return MatchOperand_ParseFail;
5132 StringRef ShiftName = Tok.getString();
5133 bool isASR;
5134 if (ShiftName == "lsl" || ShiftName == "LSL")
5135 isASR = false;
5136 else if (ShiftName == "asr" || ShiftName == "ASR")
5137 isASR = true;
5138 else {
5139 Error(S, "shift operator 'asr' or 'lsl' expected");
5140 return MatchOperand_ParseFail;
5142 Parser.Lex(); // Eat the operator.
5144 // A '#' and a shift amount.
5145 if (Parser.getTok().isNot(AsmToken::Hash) &&
5146 Parser.getTok().isNot(AsmToken::Dollar)) {
5147 Error(Parser.getTok().getLoc(), "'#' expected");
5148 return MatchOperand_ParseFail;
5150 Parser.Lex(); // Eat hash token.
5151 SMLoc ExLoc = Parser.getTok().getLoc();
5153 const MCExpr *ShiftAmount;
5154 SMLoc EndLoc;
5155 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5156 Error(ExLoc, "malformed shift expression");
5157 return MatchOperand_ParseFail;
5159 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5160 if (!CE) {
5161 Error(ExLoc, "shift amount must be an immediate");
5162 return MatchOperand_ParseFail;
5165 int64_t Val = CE->getValue();
5166 if (isASR) {
5167 // Shift amount must be in [1,32]
5168 if (Val < 1 || Val > 32) {
5169 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
5170 return MatchOperand_ParseFail;
5172 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
5173 if (isThumb() && Val == 32) {
5174 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
5175 return MatchOperand_ParseFail;
5177 if (Val == 32) Val = 0;
5178 } else {
5179 // Shift amount must be in [1,32]
5180 if (Val < 0 || Val > 31) {
5181 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
5182 return MatchOperand_ParseFail;
5186 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
5188 return MatchOperand_Success;
5191 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
5192 /// of instructions. Legal values are:
5193 /// ror #n 'n' in {0, 8, 16, 24}
5194 OperandMatchResultTy
5195 ARMAsmParser::parseRotImm(OperandVector &Operands) {
5196 MCAsmParser &Parser = getParser();
5197 const AsmToken &Tok = Parser.getTok();
5198 SMLoc S = Tok.getLoc();
5199 if (Tok.isNot(AsmToken::Identifier))
5200 return MatchOperand_NoMatch;
5201 StringRef ShiftName = Tok.getString();
5202 if (ShiftName != "ror" && ShiftName != "ROR")
5203 return MatchOperand_NoMatch;
5204 Parser.Lex(); // Eat the operator.
5206 // A '#' and a rotate amount.
5207 if (Parser.getTok().isNot(AsmToken::Hash) &&
5208 Parser.getTok().isNot(AsmToken::Dollar)) {
5209 Error(Parser.getTok().getLoc(), "'#' expected");
5210 return MatchOperand_ParseFail;
5212 Parser.Lex(); // Eat hash token.
5213 SMLoc ExLoc = Parser.getTok().getLoc();
5215 const MCExpr *ShiftAmount;
5216 SMLoc EndLoc;
5217 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5218 Error(ExLoc, "malformed rotate expression");
5219 return MatchOperand_ParseFail;
5221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5222 if (!CE) {
5223 Error(ExLoc, "rotate amount must be an immediate");
5224 return MatchOperand_ParseFail;
5227 int64_t Val = CE->getValue();
5228 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
5229 // normally, zero is represented in asm by omitting the rotate operand
5230 // entirely.
5231 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
5232 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
5233 return MatchOperand_ParseFail;
5236 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
5238 return MatchOperand_Success;
5241 OperandMatchResultTy
5242 ARMAsmParser::parseModImm(OperandVector &Operands) {
5243 MCAsmParser &Parser = getParser();
5244 MCAsmLexer &Lexer = getLexer();
5245 int64_t Imm1, Imm2;
5247 SMLoc S = Parser.getTok().getLoc();
5249 // 1) A mod_imm operand can appear in the place of a register name:
5250 // add r0, #mod_imm
5251 // add r0, r0, #mod_imm
5252 // to correctly handle the latter, we bail out as soon as we see an
5253 // identifier.
5255 // 2) Similarly, we do not want to parse into complex operands:
5256 // mov r0, #mod_imm
5257 // mov r0, :lower16:(_foo)
5258 if (Parser.getTok().is(AsmToken::Identifier) ||
5259 Parser.getTok().is(AsmToken::Colon))
5260 return MatchOperand_NoMatch;
5262 // Hash (dollar) is optional as per the ARMARM
5263 if (Parser.getTok().is(AsmToken::Hash) ||
5264 Parser.getTok().is(AsmToken::Dollar)) {
5265 // Avoid parsing into complex operands (#:)
5266 if (Lexer.peekTok().is(AsmToken::Colon))
5267 return MatchOperand_NoMatch;
5269 // Eat the hash (dollar)
5270 Parser.Lex();
5273 SMLoc Sx1, Ex1;
5274 Sx1 = Parser.getTok().getLoc();
5275 const MCExpr *Imm1Exp;
5276 if (getParser().parseExpression(Imm1Exp, Ex1)) {
5277 Error(Sx1, "malformed expression");
5278 return MatchOperand_ParseFail;
5281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
5283 if (CE) {
5284 // Immediate must fit within 32-bits
5285 Imm1 = CE->getValue();
5286 int Enc = ARM_AM::getSOImmVal(Imm1);
5287 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
5288 // We have a match!
5289 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
5290 (Enc & 0xF00) >> 7,
5291 Sx1, Ex1));
5292 return MatchOperand_Success;
5295 // We have parsed an immediate which is not for us, fallback to a plain
5296 // immediate. This can happen for instruction aliases. For an example,
5297 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
5298 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
5299 // instruction with a mod_imm operand. The alias is defined such that the
5300 // parser method is shared, that's why we have to do this here.
5301 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
5302 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5303 return MatchOperand_Success;
5305 } else {
5306 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
5307 // MCFixup). Fallback to a plain immediate.
5308 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
5309 return MatchOperand_Success;
5312 // From this point onward, we expect the input to be a (#bits, #rot) pair
5313 if (Parser.getTok().isNot(AsmToken::Comma)) {
5314 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
5315 return MatchOperand_ParseFail;
5318 if (Imm1 & ~0xFF) {
5319 Error(Sx1, "immediate operand must a number in the range [0, 255]");
5320 return MatchOperand_ParseFail;
5323 // Eat the comma
5324 Parser.Lex();
5326 // Repeat for #rot
5327 SMLoc Sx2, Ex2;
5328 Sx2 = Parser.getTok().getLoc();
5330 // Eat the optional hash (dollar)
5331 if (Parser.getTok().is(AsmToken::Hash) ||
5332 Parser.getTok().is(AsmToken::Dollar))
5333 Parser.Lex();
5335 const MCExpr *Imm2Exp;
5336 if (getParser().parseExpression(Imm2Exp, Ex2)) {
5337 Error(Sx2, "malformed expression");
5338 return MatchOperand_ParseFail;
5341 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
5343 if (CE) {
5344 Imm2 = CE->getValue();
5345 if (!(Imm2 & ~0x1E)) {
5346 // We have a match!
5347 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
5348 return MatchOperand_Success;
5350 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
5351 return MatchOperand_ParseFail;
5352 } else {
5353 Error(Sx2, "constant expression expected");
5354 return MatchOperand_ParseFail;
5358 OperandMatchResultTy
5359 ARMAsmParser::parseBitfield(OperandVector &Operands) {
5360 MCAsmParser &Parser = getParser();
5361 SMLoc S = Parser.getTok().getLoc();
5362 // The bitfield descriptor is really two operands, the LSB and the width.
5363 if (Parser.getTok().isNot(AsmToken::Hash) &&
5364 Parser.getTok().isNot(AsmToken::Dollar)) {
5365 Error(Parser.getTok().getLoc(), "'#' expected");
5366 return MatchOperand_ParseFail;
5368 Parser.Lex(); // Eat hash token.
5370 const MCExpr *LSBExpr;
5371 SMLoc E = Parser.getTok().getLoc();
5372 if (getParser().parseExpression(LSBExpr)) {
5373 Error(E, "malformed immediate expression");
5374 return MatchOperand_ParseFail;
5376 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
5377 if (!CE) {
5378 Error(E, "'lsb' operand must be an immediate");
5379 return MatchOperand_ParseFail;
5382 int64_t LSB = CE->getValue();
5383 // The LSB must be in the range [0,31]
5384 if (LSB < 0 || LSB > 31) {
5385 Error(E, "'lsb' operand must be in the range [0,31]");
5386 return MatchOperand_ParseFail;
5388 E = Parser.getTok().getLoc();
5390 // Expect another immediate operand.
5391 if (Parser.getTok().isNot(AsmToken::Comma)) {
5392 Error(Parser.getTok().getLoc(), "too few operands");
5393 return MatchOperand_ParseFail;
5395 Parser.Lex(); // Eat hash token.
5396 if (Parser.getTok().isNot(AsmToken::Hash) &&
5397 Parser.getTok().isNot(AsmToken::Dollar)) {
5398 Error(Parser.getTok().getLoc(), "'#' expected");
5399 return MatchOperand_ParseFail;
5401 Parser.Lex(); // Eat hash token.
5403 const MCExpr *WidthExpr;
5404 SMLoc EndLoc;
5405 if (getParser().parseExpression(WidthExpr, EndLoc)) {
5406 Error(E, "malformed immediate expression");
5407 return MatchOperand_ParseFail;
5409 CE = dyn_cast<MCConstantExpr>(WidthExpr);
5410 if (!CE) {
5411 Error(E, "'width' operand must be an immediate");
5412 return MatchOperand_ParseFail;
5415 int64_t Width = CE->getValue();
5416 // The LSB must be in the range [1,32-lsb]
5417 if (Width < 1 || Width > 32 - LSB) {
5418 Error(E, "'width' operand must be in the range [1,32-lsb]");
5419 return MatchOperand_ParseFail;
5422 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
5424 return MatchOperand_Success;
5427 OperandMatchResultTy
5428 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
5429 // Check for a post-index addressing register operand. Specifically:
5430 // postidx_reg := '+' register {, shift}
5431 // | '-' register {, shift}
5432 // | register {, shift}
5434 // This method must return MatchOperand_NoMatch without consuming any tokens
5435 // in the case where there is no match, as other alternatives take other
5436 // parse methods.
5437 MCAsmParser &Parser = getParser();
5438 AsmToken Tok = Parser.getTok();
5439 SMLoc S = Tok.getLoc();
5440 bool haveEaten = false;
5441 bool isAdd = true;
5442 if (Tok.is(AsmToken::Plus)) {
5443 Parser.Lex(); // Eat the '+' token.
5444 haveEaten = true;
5445 } else if (Tok.is(AsmToken::Minus)) {
5446 Parser.Lex(); // Eat the '-' token.
5447 isAdd = false;
5448 haveEaten = true;
5451 SMLoc E = Parser.getTok().getEndLoc();
5452 int Reg = tryParseRegister();
5453 if (Reg == -1) {
5454 if (!haveEaten)
5455 return MatchOperand_NoMatch;
5456 Error(Parser.getTok().getLoc(), "register expected");
5457 return MatchOperand_ParseFail;
5460 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5461 unsigned ShiftImm = 0;
5462 if (Parser.getTok().is(AsmToken::Comma)) {
5463 Parser.Lex(); // Eat the ','.
5464 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
5465 return MatchOperand_ParseFail;
5467 // FIXME: Only approximates end...may include intervening whitespace.
5468 E = Parser.getTok().getLoc();
5471 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
5472 ShiftImm, S, E));
5474 return MatchOperand_Success;
5477 OperandMatchResultTy
5478 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
5479 // Check for a post-index addressing register operand. Specifically:
5480 // am3offset := '+' register
5481 // | '-' register
5482 // | register
5483 // | # imm
5484 // | # + imm
5485 // | # - imm
5487 // This method must return MatchOperand_NoMatch without consuming any tokens
5488 // in the case where there is no match, as other alternatives take other
5489 // parse methods.
5490 MCAsmParser &Parser = getParser();
5491 AsmToken Tok = Parser.getTok();
5492 SMLoc S = Tok.getLoc();
5494 // Do immediates first, as we always parse those if we have a '#'.
5495 if (Parser.getTok().is(AsmToken::Hash) ||
5496 Parser.getTok().is(AsmToken::Dollar)) {
5497 Parser.Lex(); // Eat '#' or '$'.
5498 // Explicitly look for a '-', as we need to encode negative zero
5499 // differently.
5500 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5501 const MCExpr *Offset;
5502 SMLoc E;
5503 if (getParser().parseExpression(Offset, E))
5504 return MatchOperand_ParseFail;
5505 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5506 if (!CE) {
5507 Error(S, "constant expression expected");
5508 return MatchOperand_ParseFail;
5510 // Negative zero is encoded as the flag value
5511 // std::numeric_limits<int32_t>::min().
5512 int32_t Val = CE->getValue();
5513 if (isNegative && Val == 0)
5514 Val = std::numeric_limits<int32_t>::min();
5516 Operands.push_back(
5517 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
5519 return MatchOperand_Success;
5522 bool haveEaten = false;
5523 bool isAdd = true;
5524 if (Tok.is(AsmToken::Plus)) {
5525 Parser.Lex(); // Eat the '+' token.
5526 haveEaten = true;
5527 } else if (Tok.is(AsmToken::Minus)) {
5528 Parser.Lex(); // Eat the '-' token.
5529 isAdd = false;
5530 haveEaten = true;
5533 Tok = Parser.getTok();
5534 int Reg = tryParseRegister();
5535 if (Reg == -1) {
5536 if (!haveEaten)
5537 return MatchOperand_NoMatch;
5538 Error(Tok.getLoc(), "register expected");
5539 return MatchOperand_ParseFail;
5542 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5543 0, S, Tok.getEndLoc()));
5545 return MatchOperand_Success;
5548 /// Convert parsed operands to MCInst. Needed here because this instruction
5549 /// only has two register operands, but multiplication is commutative so
5550 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
5551 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
5552 const OperandVector &Operands) {
5553 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
5554 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
5555 // If we have a three-operand form, make sure to set Rn to be the operand
5556 // that isn't the same as Rd.
5557 unsigned RegOp = 4;
5558 if (Operands.size() == 6 &&
5559 ((ARMOperand &)*Operands[4]).getReg() ==
5560 ((ARMOperand &)*Operands[3]).getReg())
5561 RegOp = 5;
5562 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
5563 Inst.addOperand(Inst.getOperand(0));
5564 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
5567 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
5568 const OperandVector &Operands) {
5569 int CondOp = -1, ImmOp = -1;
5570 switch(Inst.getOpcode()) {
5571 case ARM::tB:
5572 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
5574 case ARM::t2B:
5575 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
5577 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
5579 // first decide whether or not the branch should be conditional
5580 // by looking at it's location relative to an IT block
5581 if(inITBlock()) {
5582 // inside an IT block we cannot have any conditional branches. any
5583 // such instructions needs to be converted to unconditional form
5584 switch(Inst.getOpcode()) {
5585 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5586 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5588 } else {
5589 // outside IT blocks we can only have unconditional branches with AL
5590 // condition code or conditional branches with non-AL condition code
5591 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
5592 switch(Inst.getOpcode()) {
5593 case ARM::tB:
5594 case ARM::tBcc:
5595 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5596 break;
5597 case ARM::t2B:
5598 case ARM::t2Bcc:
5599 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5600 break;
5604 // now decide on encoding size based on branch target range
5605 switch(Inst.getOpcode()) {
5606 // classify tB as either t2B or t1B based on range of immediate operand
5607 case ARM::tB: {
5608 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5609 if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
5610 Inst.setOpcode(ARM::t2B);
5611 break;
5613 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
5614 case ARM::tBcc: {
5615 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
5616 if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
5617 Inst.setOpcode(ARM::t2Bcc);
5618 break;
5621 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
5622 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5625 void ARMAsmParser::cvtMVEVMOVQtoDReg(
5626 MCInst &Inst, const OperandVector &Operands) {
5628 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5629 assert(Operands.size() == 8);
5631 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt
5632 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
5633 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd
5634 ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx
5635 // skip second copy of Qd in Operands[6]
5636 ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2
5637 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code
5640 /// Parse an ARM memory expression, return false if successful else return true
5641 /// or an error. The first token must be a '[' when called.
5642 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
5643 MCAsmParser &Parser = getParser();
5644 SMLoc S, E;
5645 if (Parser.getTok().isNot(AsmToken::LBrac))
5646 return TokError("Token is not a Left Bracket");
5647 S = Parser.getTok().getLoc();
5648 Parser.Lex(); // Eat left bracket token.
5650 const AsmToken &BaseRegTok = Parser.getTok();
5651 int BaseRegNum = tryParseRegister();
5652 if (BaseRegNum == -1)
5653 return Error(BaseRegTok.getLoc(), "register expected");
5655 // The next token must either be a comma, a colon or a closing bracket.
5656 const AsmToken &Tok = Parser.getTok();
5657 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
5658 !Tok.is(AsmToken::RBrac))
5659 return Error(Tok.getLoc(), "malformed memory operand");
5661 if (Tok.is(AsmToken::RBrac)) {
5662 E = Tok.getEndLoc();
5663 Parser.Lex(); // Eat right bracket token.
5665 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5666 ARM_AM::no_shift, 0, 0, false,
5667 S, E));
5669 // If there's a pre-indexing writeback marker, '!', just add it as a token
5670 // operand. It's rather odd, but syntactically valid.
5671 if (Parser.getTok().is(AsmToken::Exclaim)) {
5672 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5673 Parser.Lex(); // Eat the '!'.
5676 return false;
5679 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
5680 "Lost colon or comma in memory operand?!");
5681 if (Tok.is(AsmToken::Comma)) {
5682 Parser.Lex(); // Eat the comma.
5685 // If we have a ':', it's an alignment specifier.
5686 if (Parser.getTok().is(AsmToken::Colon)) {
5687 Parser.Lex(); // Eat the ':'.
5688 E = Parser.getTok().getLoc();
5689 SMLoc AlignmentLoc = Tok.getLoc();
5691 const MCExpr *Expr;
5692 if (getParser().parseExpression(Expr))
5693 return true;
5695 // The expression has to be a constant. Memory references with relocations
5696 // don't come through here, as they use the <label> forms of the relevant
5697 // instructions.
5698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5699 if (!CE)
5700 return Error (E, "constant expression expected");
5702 unsigned Align = 0;
5703 switch (CE->getValue()) {
5704 default:
5705 return Error(E,
5706 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
5707 case 16: Align = 2; break;
5708 case 32: Align = 4; break;
5709 case 64: Align = 8; break;
5710 case 128: Align = 16; break;
5711 case 256: Align = 32; break;
5714 // Now we should have the closing ']'
5715 if (Parser.getTok().isNot(AsmToken::RBrac))
5716 return Error(Parser.getTok().getLoc(), "']' expected");
5717 E = Parser.getTok().getEndLoc();
5718 Parser.Lex(); // Eat right bracket token.
5720 // Don't worry about range checking the value here. That's handled by
5721 // the is*() predicates.
5722 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
5723 ARM_AM::no_shift, 0, Align,
5724 false, S, E, AlignmentLoc));
5726 // If there's a pre-indexing writeback marker, '!', just add it as a token
5727 // operand.
5728 if (Parser.getTok().is(AsmToken::Exclaim)) {
5729 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5730 Parser.Lex(); // Eat the '!'.
5733 return false;
5736 // If we have a '#' or '$', it's an immediate offset, else assume it's a
5737 // register offset. Be friendly and also accept a plain integer or expression
5738 // (without a leading hash) for gas compatibility.
5739 if (Parser.getTok().is(AsmToken::Hash) ||
5740 Parser.getTok().is(AsmToken::Dollar) ||
5741 Parser.getTok().is(AsmToken::LParen) ||
5742 Parser.getTok().is(AsmToken::Integer)) {
5743 if (Parser.getTok().is(AsmToken::Hash) ||
5744 Parser.getTok().is(AsmToken::Dollar))
5745 Parser.Lex(); // Eat '#' or '$'
5746 E = Parser.getTok().getLoc();
5748 bool isNegative = getParser().getTok().is(AsmToken::Minus);
5749 const MCExpr *Offset;
5750 if (getParser().parseExpression(Offset))
5751 return true;
5753 // The expression has to be a constant. Memory references with relocations
5754 // don't come through here, as they use the <label> forms of the relevant
5755 // instructions.
5756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
5757 if (!CE)
5758 return Error (E, "constant expression expected");
5760 // If the constant was #-0, represent it as
5761 // std::numeric_limits<int32_t>::min().
5762 int32_t Val = CE->getValue();
5763 if (isNegative && Val == 0)
5764 CE = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
5765 getContext());
5767 // Now we should have the closing ']'
5768 if (Parser.getTok().isNot(AsmToken::RBrac))
5769 return Error(Parser.getTok().getLoc(), "']' expected");
5770 E = Parser.getTok().getEndLoc();
5771 Parser.Lex(); // Eat right bracket token.
5773 // Don't worry about range checking the value here. That's handled by
5774 // the is*() predicates.
5775 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
5776 ARM_AM::no_shift, 0, 0,
5777 false, S, E));
5779 // If there's a pre-indexing writeback marker, '!', just add it as a token
5780 // operand.
5781 if (Parser.getTok().is(AsmToken::Exclaim)) {
5782 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5783 Parser.Lex(); // Eat the '!'.
5786 return false;
5789 // The register offset is optionally preceded by a '+' or '-'
5790 bool isNegative = false;
5791 if (Parser.getTok().is(AsmToken::Minus)) {
5792 isNegative = true;
5793 Parser.Lex(); // Eat the '-'.
5794 } else if (Parser.getTok().is(AsmToken::Plus)) {
5795 // Nothing to do.
5796 Parser.Lex(); // Eat the '+'.
5799 E = Parser.getTok().getLoc();
5800 int OffsetRegNum = tryParseRegister();
5801 if (OffsetRegNum == -1)
5802 return Error(E, "register expected");
5804 // If there's a shift operator, handle it.
5805 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
5806 unsigned ShiftImm = 0;
5807 if (Parser.getTok().is(AsmToken::Comma)) {
5808 Parser.Lex(); // Eat the ','.
5809 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
5810 return true;
5813 // Now we should have the closing ']'
5814 if (Parser.getTok().isNot(AsmToken::RBrac))
5815 return Error(Parser.getTok().getLoc(), "']' expected");
5816 E = Parser.getTok().getEndLoc();
5817 Parser.Lex(); // Eat right bracket token.
5819 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
5820 ShiftType, ShiftImm, 0, isNegative,
5821 S, E));
5823 // If there's a pre-indexing writeback marker, '!', just add it as a token
5824 // operand.
5825 if (Parser.getTok().is(AsmToken::Exclaim)) {
5826 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
5827 Parser.Lex(); // Eat the '!'.
5830 return false;
5833 /// parseMemRegOffsetShift - one of these two:
5834 /// ( lsl | lsr | asr | ror ) , # shift_amount
5835 /// rrx
5836 /// return true if it parses a shift otherwise it returns false.
5837 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
5838 unsigned &Amount) {
5839 MCAsmParser &Parser = getParser();
5840 SMLoc Loc = Parser.getTok().getLoc();
5841 const AsmToken &Tok = Parser.getTok();
5842 if (Tok.isNot(AsmToken::Identifier))
5843 return Error(Loc, "illegal shift operator");
5844 StringRef ShiftName = Tok.getString();
5845 if (ShiftName == "lsl" || ShiftName == "LSL" ||
5846 ShiftName == "asl" || ShiftName == "ASL")
5847 St = ARM_AM::lsl;
5848 else if (ShiftName == "lsr" || ShiftName == "LSR")
5849 St = ARM_AM::lsr;
5850 else if (ShiftName == "asr" || ShiftName == "ASR")
5851 St = ARM_AM::asr;
5852 else if (ShiftName == "ror" || ShiftName == "ROR")
5853 St = ARM_AM::ror;
5854 else if (ShiftName == "rrx" || ShiftName == "RRX")
5855 St = ARM_AM::rrx;
5856 else if (ShiftName == "uxtw" || ShiftName == "UXTW")
5857 St = ARM_AM::uxtw;
5858 else
5859 return Error(Loc, "illegal shift operator");
5860 Parser.Lex(); // Eat shift type token.
5862 // rrx stands alone.
5863 Amount = 0;
5864 if (St != ARM_AM::rrx) {
5865 Loc = Parser.getTok().getLoc();
5866 // A '#' and a shift amount.
5867 const AsmToken &HashTok = Parser.getTok();
5868 if (HashTok.isNot(AsmToken::Hash) &&
5869 HashTok.isNot(AsmToken::Dollar))
5870 return Error(HashTok.getLoc(), "'#' expected");
5871 Parser.Lex(); // Eat hash token.
5873 const MCExpr *Expr;
5874 if (getParser().parseExpression(Expr))
5875 return true;
5876 // Range check the immediate.
5877 // lsl, ror: 0 <= imm <= 31
5878 // lsr, asr: 0 <= imm <= 32
5879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5880 if (!CE)
5881 return Error(Loc, "shift amount must be an immediate");
5882 int64_t Imm = CE->getValue();
5883 if (Imm < 0 ||
5884 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5885 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5886 return Error(Loc, "immediate shift value out of range");
5887 // If <ShiftTy> #0, turn it into a no_shift.
5888 if (Imm == 0)
5889 St = ARM_AM::lsl;
5890 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5891 if (Imm == 32)
5892 Imm = 0;
5893 Amount = Imm;
5896 return false;
5899 /// parseFPImm - A floating point immediate expression operand.
5900 OperandMatchResultTy
5901 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5902 MCAsmParser &Parser = getParser();
5903 // Anything that can accept a floating point constant as an operand
5904 // needs to go through here, as the regular parseExpression is
5905 // integer only.
5907 // This routine still creates a generic Immediate operand, containing
5908 // a bitcast of the 64-bit floating point value. The various operands
5909 // that accept floats can check whether the value is valid for them
5910 // via the standard is*() predicates.
5912 SMLoc S = Parser.getTok().getLoc();
5914 if (Parser.getTok().isNot(AsmToken::Hash) &&
5915 Parser.getTok().isNot(AsmToken::Dollar))
5916 return MatchOperand_NoMatch;
5918 // Disambiguate the VMOV forms that can accept an FP immediate.
5919 // vmov.f32 <sreg>, #imm
5920 // vmov.f64 <dreg>, #imm
5921 // vmov.f32 <dreg>, #imm @ vector f32x2
5922 // vmov.f32 <qreg>, #imm @ vector f32x4
5924 // There are also the NEON VMOV instructions which expect an
5925 // integer constant. Make sure we don't try to parse an FPImm
5926 // for these:
5927 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5928 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5929 bool isVmovf = TyOp.isToken() &&
5930 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5931 TyOp.getToken() == ".f16");
5932 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5933 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5934 Mnemonic.getToken() == "fconsts");
5935 if (!(isVmovf || isFconst))
5936 return MatchOperand_NoMatch;
5938 Parser.Lex(); // Eat '#' or '$'.
5940 // Handle negation, as that still comes through as a separate token.
5941 bool isNegative = false;
5942 if (Parser.getTok().is(AsmToken::Minus)) {
5943 isNegative = true;
5944 Parser.Lex();
5946 const AsmToken &Tok = Parser.getTok();
5947 SMLoc Loc = Tok.getLoc();
5948 if (Tok.is(AsmToken::Real) && isVmovf) {
5949 APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
5950 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5951 // If we had a '-' in front, toggle the sign bit.
5952 IntVal ^= (uint64_t)isNegative << 31;
5953 Parser.Lex(); // Eat the token.
5954 Operands.push_back(ARMOperand::CreateImm(
5955 MCConstantExpr::create(IntVal, getContext()),
5956 S, Parser.getTok().getLoc()));
5957 return MatchOperand_Success;
5959 // Also handle plain integers. Instructions which allow floating point
5960 // immediates also allow a raw encoded 8-bit value.
5961 if (Tok.is(AsmToken::Integer) && isFconst) {
5962 int64_t Val = Tok.getIntVal();
5963 Parser.Lex(); // Eat the token.
5964 if (Val > 255 || Val < 0) {
5965 Error(Loc, "encoded floating point value out of range");
5966 return MatchOperand_ParseFail;
5968 float RealVal = ARM_AM::getFPImmFloat(Val);
5969 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5971 Operands.push_back(ARMOperand::CreateImm(
5972 MCConstantExpr::create(Val, getContext()), S,
5973 Parser.getTok().getLoc()));
5974 return MatchOperand_Success;
5977 Error(Loc, "invalid floating point immediate");
5978 return MatchOperand_ParseFail;
5981 /// Parse a arm instruction operand. For now this parses the operand regardless
5982 /// of the mnemonic.
5983 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5984 MCAsmParser &Parser = getParser();
5985 SMLoc S, E;
5987 // Check if the current operand has a custom associated parser, if so, try to
5988 // custom parse the operand, or fallback to the general approach.
5989 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5990 if (ResTy == MatchOperand_Success)
5991 return false;
5992 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5993 // there was a match, but an error occurred, in which case, just return that
5994 // the operand parsing failed.
5995 if (ResTy == MatchOperand_ParseFail)
5996 return true;
5998 switch (getLexer().getKind()) {
5999 default:
6000 Error(Parser.getTok().getLoc(), "unexpected token in operand");
6001 return true;
6002 case AsmToken::Identifier: {
6003 // If we've seen a branch mnemonic, the next operand must be a label. This
6004 // is true even if the label is a register name. So "br r1" means branch to
6005 // label "r1".
6006 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
6007 if (!ExpectLabel) {
6008 if (!tryParseRegisterWithWriteBack(Operands))
6009 return false;
6010 int Res = tryParseShiftRegister(Operands);
6011 if (Res == 0) // success
6012 return false;
6013 else if (Res == -1) // irrecoverable error
6014 return true;
6015 // If this is VMRS, check for the apsr_nzcv operand.
6016 if (Mnemonic == "vmrs" &&
6017 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
6018 S = Parser.getTok().getLoc();
6019 Parser.Lex();
6020 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
6021 return false;
6025 // Fall though for the Identifier case that is not a register or a
6026 // special name.
6027 LLVM_FALLTHROUGH;
6029 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
6030 case AsmToken::Integer: // things like 1f and 2b as a branch targets
6031 case AsmToken::String: // quoted label names.
6032 case AsmToken::Dot: { // . as a branch target
6033 // This was not a register so parse other operands that start with an
6034 // identifier (like labels) as expressions and create them as immediates.
6035 const MCExpr *IdVal;
6036 S = Parser.getTok().getLoc();
6037 if (getParser().parseExpression(IdVal))
6038 return true;
6039 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6040 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
6041 return false;
6043 case AsmToken::LBrac:
6044 return parseMemory(Operands);
6045 case AsmToken::LCurly:
6046 return parseRegisterList(Operands, !Mnemonic.startswith("clr"));
6047 case AsmToken::Dollar:
6048 case AsmToken::Hash:
6049 // #42 -> immediate.
6050 S = Parser.getTok().getLoc();
6051 Parser.Lex();
6053 if (Parser.getTok().isNot(AsmToken::Colon)) {
6054 bool isNegative = Parser.getTok().is(AsmToken::Minus);
6055 const MCExpr *ImmVal;
6056 if (getParser().parseExpression(ImmVal))
6057 return true;
6058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
6059 if (CE) {
6060 int32_t Val = CE->getValue();
6061 if (isNegative && Val == 0)
6062 ImmVal = MCConstantExpr::create(std::numeric_limits<int32_t>::min(),
6063 getContext());
6065 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6066 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
6068 // There can be a trailing '!' on operands that we want as a separate
6069 // '!' Token operand. Handle that here. For example, the compatibility
6070 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
6071 if (Parser.getTok().is(AsmToken::Exclaim)) {
6072 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
6073 Parser.getTok().getLoc()));
6074 Parser.Lex(); // Eat exclaim token
6076 return false;
6078 // w/ a ':' after the '#', it's just like a plain ':'.
6079 LLVM_FALLTHROUGH;
6081 case AsmToken::Colon: {
6082 S = Parser.getTok().getLoc();
6083 // ":lower16:" and ":upper16:" expression prefixes
6084 // FIXME: Check it's an expression prefix,
6085 // e.g. (FOO - :lower16:BAR) isn't legal.
6086 ARMMCExpr::VariantKind RefKind;
6087 if (parsePrefix(RefKind))
6088 return true;
6090 const MCExpr *SubExprVal;
6091 if (getParser().parseExpression(SubExprVal))
6092 return true;
6094 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
6095 getContext());
6096 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6097 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
6098 return false;
6100 case AsmToken::Equal: {
6101 S = Parser.getTok().getLoc();
6102 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
6103 return Error(S, "unexpected token in operand");
6104 Parser.Lex(); // Eat '='
6105 const MCExpr *SubExprVal;
6106 if (getParser().parseExpression(SubExprVal))
6107 return true;
6108 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6110 // execute-only: we assume that assembly programmers know what they are
6111 // doing and allow literal pool creation here
6112 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
6113 return false;
6118 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
6119 // :lower16: and :upper16:.
6120 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
6121 MCAsmParser &Parser = getParser();
6122 RefKind = ARMMCExpr::VK_ARM_None;
6124 // consume an optional '#' (GNU compatibility)
6125 if (getLexer().is(AsmToken::Hash))
6126 Parser.Lex();
6128 // :lower16: and :upper16: modifiers
6129 assert(getLexer().is(AsmToken::Colon) && "expected a :");
6130 Parser.Lex(); // Eat ':'
6132 if (getLexer().isNot(AsmToken::Identifier)) {
6133 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
6134 return true;
6137 enum {
6138 COFF = (1 << MCObjectFileInfo::IsCOFF),
6139 ELF = (1 << MCObjectFileInfo::IsELF),
6140 MACHO = (1 << MCObjectFileInfo::IsMachO),
6141 WASM = (1 << MCObjectFileInfo::IsWasm),
6143 static const struct PrefixEntry {
6144 const char *Spelling;
6145 ARMMCExpr::VariantKind VariantKind;
6146 uint8_t SupportedFormats;
6147 } PrefixEntries[] = {
6148 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
6149 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
6152 StringRef IDVal = Parser.getTok().getIdentifier();
6154 const auto &Prefix =
6155 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
6156 [&IDVal](const PrefixEntry &PE) {
6157 return PE.Spelling == IDVal;
6159 if (Prefix == std::end(PrefixEntries)) {
6160 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
6161 return true;
6164 uint8_t CurrentFormat;
6165 switch (getContext().getObjectFileInfo()->getObjectFileType()) {
6166 case MCObjectFileInfo::IsMachO:
6167 CurrentFormat = MACHO;
6168 break;
6169 case MCObjectFileInfo::IsELF:
6170 CurrentFormat = ELF;
6171 break;
6172 case MCObjectFileInfo::IsCOFF:
6173 CurrentFormat = COFF;
6174 break;
6175 case MCObjectFileInfo::IsWasm:
6176 CurrentFormat = WASM;
6177 break;
6178 case MCObjectFileInfo::IsXCOFF:
6179 llvm_unreachable("unexpected object format");
6180 break;
6183 if (~Prefix->SupportedFormats & CurrentFormat) {
6184 Error(Parser.getTok().getLoc(),
6185 "cannot represent relocation in the current file format");
6186 return true;
6189 RefKind = Prefix->VariantKind;
6190 Parser.Lex();
6192 if (getLexer().isNot(AsmToken::Colon)) {
6193 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
6194 return true;
6196 Parser.Lex(); // Eat the last ':'
6198 return false;
6201 /// Given a mnemonic, split out possible predication code and carry
6202 /// setting letters to form a canonical mnemonic and flags.
6204 // FIXME: Would be nice to autogen this.
6205 // FIXME: This is a bit of a maze of special cases.
6206 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
6207 StringRef ExtraToken,
6208 unsigned &PredicationCode,
6209 unsigned &VPTPredicationCode,
6210 bool &CarrySetting,
6211 unsigned &ProcessorIMod,
6212 StringRef &ITMask) {
6213 PredicationCode = ARMCC::AL;
6214 VPTPredicationCode = ARMVCC::None;
6215 CarrySetting = false;
6216 ProcessorIMod = 0;
6218 // Ignore some mnemonics we know aren't predicated forms.
6220 // FIXME: Would be nice to autogen this.
6221 if ((Mnemonic == "movs" && isThumb()) ||
6222 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
6223 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
6224 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
6225 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
6226 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
6227 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
6228 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
6229 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
6230 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
6231 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
6232 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
6233 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
6234 Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
6235 Mnemonic == "bxns" || Mnemonic == "blxns" ||
6236 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6237 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6238 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6239 Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
6240 Mnemonic == "csel" || Mnemonic == "csinc" ||
6241 Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
6242 Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
6243 Mnemonic == "csetm")
6244 return Mnemonic;
6246 // First, split out any predication code. Ignore mnemonics we know aren't
6247 // predicated but do have a carry-set and so weren't caught above.
6248 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
6249 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
6250 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
6251 Mnemonic != "sbcs" && Mnemonic != "rscs" &&
6252 !(hasMVE() &&
6253 (Mnemonic == "vmine" ||
6254 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
6255 Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
6256 Mnemonic == "vmvne" || Mnemonic == "vorne" ||
6257 Mnemonic == "vnege" || Mnemonic == "vnegt" ||
6258 Mnemonic == "vmule" || Mnemonic == "vmult" ||
6259 Mnemonic == "vrintne" ||
6260 Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
6261 Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
6262 Mnemonic.startswith("vq")))) {
6263 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
6264 if (CC != ~0U) {
6265 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
6266 PredicationCode = CC;
6270 // Next, determine if we have a carry setting bit. We explicitly ignore all
6271 // the instructions we know end in 's'.
6272 if (Mnemonic.endswith("s") &&
6273 !(Mnemonic == "cps" || Mnemonic == "mls" ||
6274 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
6275 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
6276 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
6277 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
6278 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
6279 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
6280 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
6281 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
6282 Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
6283 Mnemonic == "vmlas" ||
6284 (Mnemonic == "movs" && isThumb()))) {
6285 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
6286 CarrySetting = true;
6289 // The "cps" instruction can have a interrupt mode operand which is glued into
6290 // the mnemonic. Check if this is the case, split it and parse the imod op
6291 if (Mnemonic.startswith("cps")) {
6292 // Split out any imod code.
6293 unsigned IMod =
6294 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
6295 .Case("ie", ARM_PROC::IE)
6296 .Case("id", ARM_PROC::ID)
6297 .Default(~0U);
6298 if (IMod != ~0U) {
6299 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
6300 ProcessorIMod = IMod;
6304 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
6305 Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
6306 Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6307 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
6308 Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
6309 Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6310 Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
6311 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
6312 if (CC != ~0U) {
6313 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
6314 VPTPredicationCode = CC;
6316 return Mnemonic;
6319 // The "it" instruction has the condition mask on the end of the mnemonic.
6320 if (Mnemonic.startswith("it")) {
6321 ITMask = Mnemonic.slice(2, Mnemonic.size());
6322 Mnemonic = Mnemonic.slice(0, 2);
6325 if (Mnemonic.startswith("vpst")) {
6326 ITMask = Mnemonic.slice(4, Mnemonic.size());
6327 Mnemonic = Mnemonic.slice(0, 4);
6329 else if (Mnemonic.startswith("vpt")) {
6330 ITMask = Mnemonic.slice(3, Mnemonic.size());
6331 Mnemonic = Mnemonic.slice(0, 3);
6334 return Mnemonic;
6337 /// Given a canonical mnemonic, determine if the instruction ever allows
6338 /// inclusion of carry set or predication code operands.
6340 // FIXME: It would be nice to autogen this.
6341 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic,
6342 StringRef ExtraToken,
6343 StringRef FullInst,
6344 bool &CanAcceptCarrySet,
6345 bool &CanAcceptPredicationCode,
6346 bool &CanAcceptVPTPredicationCode) {
6347 CanAcceptVPTPredicationCode = isMnemonicVPTPredicable(Mnemonic, ExtraToken);
6349 CanAcceptCarrySet =
6350 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6351 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
6352 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
6353 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
6354 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
6355 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
6356 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
6357 (!isThumb() &&
6358 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
6359 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
6361 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
6362 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
6363 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
6364 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
6365 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
6366 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
6367 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
6368 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
6369 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
6370 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
6371 (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
6372 Mnemonic == "vmovx" || Mnemonic == "vins" ||
6373 Mnemonic == "vudot" || Mnemonic == "vsdot" ||
6374 Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
6375 Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
6376 Mnemonic == "sb" || Mnemonic == "ssbb" ||
6377 Mnemonic == "pssbb" ||
6378 Mnemonic == "bfcsel" || Mnemonic == "wls" ||
6379 Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
6380 Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
6381 Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
6382 Mnemonic == "cset" || Mnemonic == "csetm" ||
6383 Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
6384 (hasMVE() &&
6385 (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
6386 Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
6387 Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
6388 Mnemonic.startswith("letp")))) {
6389 // These mnemonics are never predicable
6390 CanAcceptPredicationCode = false;
6391 } else if (!isThumb()) {
6392 // Some instructions are only predicable in Thumb mode
6393 CanAcceptPredicationCode =
6394 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
6395 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
6396 Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
6397 Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
6398 Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
6399 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
6400 Mnemonic != "tsb" &&
6401 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
6402 } else if (isThumbOne()) {
6403 if (hasV6MOps())
6404 CanAcceptPredicationCode = Mnemonic != "movs";
6405 else
6406 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
6407 } else
6408 CanAcceptPredicationCode = true;
6411 // Some Thumb instructions have two operand forms that are not
6412 // available as three operand, convert to two operand form if possible.
6414 // FIXME: We would really like to be able to tablegen'erate this.
6415 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
6416 bool CarrySetting,
6417 OperandVector &Operands) {
6418 if (Operands.size() != 6)
6419 return;
6421 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6422 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
6423 if (!Op3.isReg() || !Op4.isReg())
6424 return;
6426 auto Op3Reg = Op3.getReg();
6427 auto Op4Reg = Op4.getReg();
6429 // For most Thumb2 cases we just generate the 3 operand form and reduce
6430 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
6431 // won't accept SP or PC so we do the transformation here taking care
6432 // with immediate range in the 'add sp, sp #imm' case.
6433 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
6434 if (isThumbTwo()) {
6435 if (Mnemonic != "add")
6436 return;
6437 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
6438 (Op5.isReg() && Op5.getReg() == ARM::PC);
6439 if (!TryTransform) {
6440 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
6441 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6442 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
6443 Op5.isImm() && !Op5.isImm0_508s4());
6445 if (!TryTransform)
6446 return;
6447 } else if (!isThumbOne())
6448 return;
6450 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
6451 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
6452 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
6453 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
6454 return;
6456 // If first 2 operands of a 3 operand instruction are the same
6457 // then transform to 2 operand version of the same instruction
6458 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
6459 bool Transform = Op3Reg == Op4Reg;
6461 // For communtative operations, we might be able to transform if we swap
6462 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
6463 // as tADDrsp.
6464 const ARMOperand *LastOp = &Op5;
6465 bool Swap = false;
6466 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
6467 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
6468 Mnemonic == "and" || Mnemonic == "eor" ||
6469 Mnemonic == "adc" || Mnemonic == "orr")) {
6470 Swap = true;
6471 LastOp = &Op4;
6472 Transform = true;
6475 // If both registers are the same then remove one of them from
6476 // the operand list, with certain exceptions.
6477 if (Transform) {
6478 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
6479 // 2 operand forms don't exist.
6480 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
6481 LastOp->isReg())
6482 Transform = false;
6484 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
6485 // 3-bits because the ARMARM says not to.
6486 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
6487 Transform = false;
6490 if (Transform) {
6491 if (Swap)
6492 std::swap(Op4, Op5);
6493 Operands.erase(Operands.begin() + 3);
6497 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
6498 OperandVector &Operands) {
6499 // FIXME: This is all horribly hacky. We really need a better way to deal
6500 // with optional operands like this in the matcher table.
6502 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
6503 // another does not. Specifically, the MOVW instruction does not. So we
6504 // special case it here and remove the defaulted (non-setting) cc_out
6505 // operand if that's the instruction we're trying to match.
6507 // We do this as post-processing of the explicit operands rather than just
6508 // conditionally adding the cc_out in the first place because we need
6509 // to check the type of the parsed immediate operand.
6510 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
6511 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
6512 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
6513 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6514 return true;
6516 // Register-register 'add' for thumb does not have a cc_out operand
6517 // when there are only two register operands.
6518 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
6519 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6520 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6521 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
6522 return true;
6523 // Register-register 'add' for thumb does not have a cc_out operand
6524 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
6525 // have to check the immediate range here since Thumb2 has a variant
6526 // that can handle a different range and has a cc_out operand.
6527 if (((isThumb() && Mnemonic == "add") ||
6528 (isThumbTwo() && Mnemonic == "sub")) &&
6529 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6530 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6531 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
6532 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6533 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
6534 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
6535 return true;
6536 // For Thumb2, add/sub immediate does not have a cc_out operand for the
6537 // imm0_4095 variant. That's the least-preferred variant when
6538 // selecting via the generic "add" mnemonic, so to know that we
6539 // should remove the cc_out operand, we have to explicitly check that
6540 // it's not one of the other variants. Ugh.
6541 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
6542 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6543 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6544 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
6545 // Nest conditions rather than one big 'if' statement for readability.
6547 // If both registers are low, we're in an IT block, and the immediate is
6548 // in range, we should use encoding T1 instead, which has a cc_out.
6549 if (inITBlock() &&
6550 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
6551 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
6552 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
6553 return false;
6554 // Check against T3. If the second register is the PC, this is an
6555 // alternate form of ADR, which uses encoding T4, so check for that too.
6556 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
6557 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
6558 return false;
6560 // Otherwise, we use encoding T4, which does not have a cc_out
6561 // operand.
6562 return true;
6565 // The thumb2 multiply instruction doesn't have a CCOut register, so
6566 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
6567 // use the 16-bit encoding or not.
6568 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
6569 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6570 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6571 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6572 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
6573 // If the registers aren't low regs, the destination reg isn't the
6574 // same as one of the source regs, or the cc_out operand is zero
6575 // outside of an IT block, we have to use the 32-bit encoding, so
6576 // remove the cc_out operand.
6577 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6578 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6579 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
6580 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6581 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
6582 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
6583 static_cast<ARMOperand &>(*Operands[4]).getReg())))
6584 return true;
6586 // Also check the 'mul' syntax variant that doesn't specify an explicit
6587 // destination register.
6588 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
6589 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6590 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6591 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
6592 // If the registers aren't low regs or the cc_out operand is zero
6593 // outside of an IT block, we have to use the 32-bit encoding, so
6594 // remove the cc_out operand.
6595 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
6596 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
6597 !inITBlock()))
6598 return true;
6600 // Register-register 'add/sub' for thumb does not have a cc_out operand
6601 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
6602 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
6603 // right, this will result in better diagnostics (which operand is off)
6604 // anyway.
6605 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
6606 (Operands.size() == 5 || Operands.size() == 6) &&
6607 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
6608 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
6609 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
6610 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
6611 (Operands.size() == 6 &&
6612 static_cast<ARMOperand &>(*Operands[5]).isImm())))
6613 return true;
6615 return false;
6618 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
6619 OperandVector &Operands) {
6620 // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
6621 unsigned RegIdx = 3;
6622 if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
6623 Mnemonic == "vrintr") &&
6624 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
6625 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
6626 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6627 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
6628 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
6629 RegIdx = 4;
6631 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
6632 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6633 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
6634 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6635 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
6636 return true;
6638 return false;
6641 bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
6642 OperandVector &Operands) {
6643 if (!hasMVE() || Operands.size() < 3)
6644 return true;
6646 if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
6647 Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
6648 return true;
6650 if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
6651 return false;
6653 if (Mnemonic.startswith("vmov") &&
6654 !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
6655 Mnemonic.startswith("vmovx"))) {
6656 for (auto &Operand : Operands) {
6657 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6658 ((*Operand).isReg() &&
6659 (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
6660 (*Operand).getReg()) ||
6661 ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
6662 (*Operand).getReg())))) {
6663 return true;
6666 return false;
6667 } else {
6668 for (auto &Operand : Operands) {
6669 // We check the larger class QPR instead of just the legal class
6670 // MQPR, to more accurately report errors when using Q registers
6671 // outside of the allowed range.
6672 if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
6673 (Operand->isReg() &&
6674 (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
6675 Operand->getReg()))))
6676 return false;
6678 return true;
6682 static bool isDataTypeToken(StringRef Tok) {
6683 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
6684 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
6685 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
6686 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
6687 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
6688 Tok == ".f" || Tok == ".d";
6691 // FIXME: This bit should probably be handled via an explicit match class
6692 // in the .td files that matches the suffix instead of having it be
6693 // a literal string token the way it is now.
6694 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
6695 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
6698 static void applyMnemonicAliases(StringRef &Mnemonic,
6699 const FeatureBitset &Features,
6700 unsigned VariantID);
6702 // The GNU assembler has aliases of ldrd and strd with the second register
6703 // omitted. We don't have a way to do that in tablegen, so fix it up here.
6705 // We have to be careful to not emit an invalid Rt2 here, because the rest of
6706 // the assmebly parser could then generate confusing diagnostics refering to
6707 // it. If we do find anything that prevents us from doing the transformation we
6708 // bail out, and let the assembly parser report an error on the instruction as
6709 // it is written.
6710 void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
6711 OperandVector &Operands) {
6712 if (Mnemonic != "ldrd" && Mnemonic != "strd")
6713 return;
6714 if (Operands.size() < 4)
6715 return;
6717 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
6718 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
6720 if (!Op2.isReg())
6721 return;
6722 if (!Op3.isGPRMem())
6723 return;
6725 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
6726 if (!GPR.contains(Op2.getReg()))
6727 return;
6729 unsigned RtEncoding = MRI->getEncodingValue(Op2.getReg());
6730 if (!isThumb() && (RtEncoding & 1)) {
6731 // In ARM mode, the registers must be from an aligned pair, this
6732 // restriction does not apply in Thumb mode.
6733 return;
6735 if (Op2.getReg() == ARM::PC)
6736 return;
6737 unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
6738 if (!PairedReg || PairedReg == ARM::PC ||
6739 (PairedReg == ARM::SP && !hasV8Ops()))
6740 return;
6742 Operands.insert(
6743 Operands.begin() + 3,
6744 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
6747 /// Parse an arm instruction mnemonic followed by its operands.
6748 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
6749 SMLoc NameLoc, OperandVector &Operands) {
6750 MCAsmParser &Parser = getParser();
6752 // Apply mnemonic aliases before doing anything else, as the destination
6753 // mnemonic may include suffices and we want to handle them normally.
6754 // The generic tblgen'erated code does this later, at the start of
6755 // MatchInstructionImpl(), but that's too late for aliases that include
6756 // any sort of suffix.
6757 const FeatureBitset &AvailableFeatures = getAvailableFeatures();
6758 unsigned AssemblerDialect = getParser().getAssemblerDialect();
6759 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
6761 // First check for the ARM-specific .req directive.
6762 if (Parser.getTok().is(AsmToken::Identifier) &&
6763 Parser.getTok().getIdentifier() == ".req") {
6764 parseDirectiveReq(Name, NameLoc);
6765 // We always return 'error' for this, as we're done with this
6766 // statement and don't need to match the 'instruction."
6767 return true;
6770 // Create the leading tokens for the mnemonic, split by '.' characters.
6771 size_t Start = 0, Next = Name.find('.');
6772 StringRef Mnemonic = Name.slice(Start, Next);
6773 StringRef ExtraToken = Name.slice(Next, Name.find(' ', Next + 1));
6775 // Split out the predication code and carry setting flag from the mnemonic.
6776 unsigned PredicationCode;
6777 unsigned VPTPredicationCode;
6778 unsigned ProcessorIMod;
6779 bool CarrySetting;
6780 StringRef ITMask;
6781 Mnemonic = splitMnemonic(Mnemonic, ExtraToken, PredicationCode, VPTPredicationCode,
6782 CarrySetting, ProcessorIMod, ITMask);
6784 // In Thumb1, only the branch (B) instruction can be predicated.
6785 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
6786 return Error(NameLoc, "conditional execution not supported in Thumb1");
6789 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
6791 // Handle the mask for IT and VPT instructions. In ARMOperand and
6792 // MCOperand, this is stored in a format independent of the
6793 // condition code: the lowest set bit indicates the end of the
6794 // encoding, and above that, a 1 bit indicates 'else', and an 0
6795 // indicates 'then'. E.g.
6796 // IT -> 1000
6797 // ITx -> x100 (ITT -> 0100, ITE -> 1100)
6798 // ITxy -> xy10 (e.g. ITET -> 1010)
6799 // ITxyz -> xyz1 (e.g. ITEET -> 1101)
6800 if (Mnemonic == "it" || Mnemonic.startswith("vpt") ||
6801 Mnemonic.startswith("vpst")) {
6802 SMLoc Loc = Mnemonic == "it" ? SMLoc::getFromPointer(NameLoc.getPointer() + 2) :
6803 Mnemonic == "vpt" ? SMLoc::getFromPointer(NameLoc.getPointer() + 3) :
6804 SMLoc::getFromPointer(NameLoc.getPointer() + 4);
6805 if (ITMask.size() > 3) {
6806 if (Mnemonic == "it")
6807 return Error(Loc, "too many conditions on IT instruction");
6808 return Error(Loc, "too many conditions on VPT instruction");
6810 unsigned Mask = 8;
6811 for (unsigned i = ITMask.size(); i != 0; --i) {
6812 char pos = ITMask[i - 1];
6813 if (pos != 't' && pos != 'e') {
6814 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
6816 Mask >>= 1;
6817 if (ITMask[i - 1] == 'e')
6818 Mask |= 8;
6820 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
6823 // FIXME: This is all a pretty gross hack. We should automatically handle
6824 // optional operands like this via tblgen.
6826 // Next, add the CCOut and ConditionCode operands, if needed.
6828 // For mnemonics which can ever incorporate a carry setting bit or predication
6829 // code, our matching model involves us always generating CCOut and
6830 // ConditionCode operands to match the mnemonic "as written" and then we let
6831 // the matcher deal with finding the right instruction or generating an
6832 // appropriate error.
6833 bool CanAcceptCarrySet, CanAcceptPredicationCode, CanAcceptVPTPredicationCode;
6834 getMnemonicAcceptInfo(Mnemonic, ExtraToken, Name, CanAcceptCarrySet,
6835 CanAcceptPredicationCode, CanAcceptVPTPredicationCode);
6837 // If we had a carry-set on an instruction that can't do that, issue an
6838 // error.
6839 if (!CanAcceptCarrySet && CarrySetting) {
6840 return Error(NameLoc, "instruction '" + Mnemonic +
6841 "' can not set flags, but 's' suffix specified");
6843 // If we had a predication code on an instruction that can't do that, issue an
6844 // error.
6845 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
6846 return Error(NameLoc, "instruction '" + Mnemonic +
6847 "' is not predicable, but condition code specified");
6850 // If we had a VPT predication code on an instruction that can't do that, issue an
6851 // error.
6852 if (!CanAcceptVPTPredicationCode && VPTPredicationCode != ARMVCC::None) {
6853 return Error(NameLoc, "instruction '" + Mnemonic +
6854 "' is not VPT predicable, but VPT code T/E is specified");
6857 // Add the carry setting operand, if necessary.
6858 if (CanAcceptCarrySet) {
6859 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
6860 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6861 Loc));
6864 // Add the predication code operand, if necessary.
6865 if (CanAcceptPredicationCode) {
6866 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6867 CarrySetting);
6868 Operands.push_back(ARMOperand::CreateCondCode(
6869 ARMCC::CondCodes(PredicationCode), Loc));
6872 // Add the VPT predication code operand, if necessary.
6873 // FIXME: We don't add them for the instructions filtered below as these can
6874 // have custom operands which need special parsing. This parsing requires
6875 // the operand to be in the same place in the OperandVector as their
6876 // definition in tblgen. Since these instructions may also have the
6877 // scalar predication operand we do not add the vector one and leave until
6878 // now to fix it up.
6879 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
6880 !Mnemonic.startswith("vcmp") &&
6881 !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
6882 Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
6883 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
6884 CarrySetting);
6885 Operands.push_back(ARMOperand::CreateVPTPred(
6886 ARMVCC::VPTCodes(VPTPredicationCode), Loc));
6889 // Add the processor imod operand, if necessary.
6890 if (ProcessorIMod) {
6891 Operands.push_back(ARMOperand::CreateImm(
6892 MCConstantExpr::create(ProcessorIMod, getContext()),
6893 NameLoc, NameLoc));
6894 } else if (Mnemonic == "cps" && isMClass()) {
6895 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
6898 // Add the remaining tokens in the mnemonic.
6899 while (Next != StringRef::npos) {
6900 Start = Next;
6901 Next = Name.find('.', Start + 1);
6902 ExtraToken = Name.slice(Start, Next);
6904 // Some NEON instructions have an optional datatype suffix that is
6905 // completely ignored. Check for that.
6906 if (isDataTypeToken(ExtraToken) &&
6907 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
6908 continue;
6910 // For for ARM mode generate an error if the .n qualifier is used.
6911 if (ExtraToken == ".n" && !isThumb()) {
6912 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6913 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
6914 "arm mode");
6917 // The .n qualifier is always discarded as that is what the tables
6918 // and matcher expect. In ARM mode the .w qualifier has no effect,
6919 // so discard it to avoid errors that can be caused by the matcher.
6920 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
6921 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
6922 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
6926 // Read the remaining operands.
6927 if (getLexer().isNot(AsmToken::EndOfStatement)) {
6928 // Read the first operand.
6929 if (parseOperand(Operands, Mnemonic)) {
6930 return true;
6933 while (parseOptionalToken(AsmToken::Comma)) {
6934 // Parse and remember the operand.
6935 if (parseOperand(Operands, Mnemonic)) {
6936 return true;
6941 if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
6942 return true;
6944 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
6946 // Some instructions, mostly Thumb, have forms for the same mnemonic that
6947 // do and don't have a cc_out optional-def operand. With some spot-checks
6948 // of the operand list, we can figure out which variant we're trying to
6949 // parse and adjust accordingly before actually matching. We shouldn't ever
6950 // try to remove a cc_out operand that was explicitly set on the
6951 // mnemonic, of course (CarrySetting == true). Reason number #317 the
6952 // table driven matcher doesn't fit well with the ARM instruction set.
6953 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
6954 Operands.erase(Operands.begin() + 1);
6956 // Some instructions have the same mnemonic, but don't always
6957 // have a predicate. Distinguish them here and delete the
6958 // appropriate predicate if needed. This could be either the scalar
6959 // predication code or the vector predication code.
6960 if (PredicationCode == ARMCC::AL &&
6961 shouldOmitPredicateOperand(Mnemonic, Operands))
6962 Operands.erase(Operands.begin() + 1);
6965 if (hasMVE()) {
6966 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
6967 Mnemonic == "vmov" && PredicationCode == ARMCC::LT) {
6968 // Very nasty hack to deal with the vector predicated variant of vmovlt
6969 // the scalar predicated vmov with condition 'lt'. We can not tell them
6970 // apart until we have parsed their operands.
6971 Operands.erase(Operands.begin() + 1);
6972 Operands.erase(Operands.begin());
6973 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6974 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
6975 Mnemonic.size() - 1 + CarrySetting);
6976 Operands.insert(Operands.begin(),
6977 ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
6978 Operands.insert(Operands.begin(),
6979 ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
6980 } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE &&
6981 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6982 // Another nasty hack to deal with the ambiguity between vcvt with scalar
6983 // predication 'ne' and vcvtn with vector predication 'e'. As above we
6984 // can only distinguish between the two after we have parsed their
6985 // operands.
6986 Operands.erase(Operands.begin() + 1);
6987 Operands.erase(Operands.begin());
6988 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6989 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
6990 Mnemonic.size() - 1 + CarrySetting);
6991 Operands.insert(Operands.begin(),
6992 ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
6993 Operands.insert(Operands.begin(),
6994 ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
6995 } else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
6996 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6997 // Another hack, this time to distinguish between scalar predicated vmul
6998 // with 'lt' predication code and the vector instruction vmullt with
6999 // vector predication code "none"
7000 Operands.erase(Operands.begin() + 1);
7001 Operands.erase(Operands.begin());
7002 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7003 Operands.insert(Operands.begin(),
7004 ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
7006 // For vmov and vcmp, as mentioned earlier, we did not add the vector
7007 // predication code, since these may contain operands that require
7008 // special parsing. So now we have to see if they require vector
7009 // predication and replace the scalar one with the vector predication
7010 // operand if that is the case.
7011 else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp") ||
7012 (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
7013 !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
7014 !Mnemonic.startswith("vcvtm"))) {
7015 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7016 // We could not split the vector predicate off vcvt because it might
7017 // have been the scalar vcvtt instruction. Now we know its a vector
7018 // instruction, we still need to check whether its the vector
7019 // predicated vcvt with 'Then' predication or the vector vcvtt. We can
7020 // distinguish the two based on the suffixes, if it is any of
7021 // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
7022 if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
7023 auto Sz1 = static_cast<ARMOperand &>(*Operands[2]);
7024 auto Sz2 = static_cast<ARMOperand &>(*Operands[3]);
7025 if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
7026 Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
7027 Operands.erase(Operands.begin());
7028 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
7029 VPTPredicationCode = ARMVCC::Then;
7031 Mnemonic = Mnemonic.substr(0, 4);
7032 Operands.insert(Operands.begin(),
7033 ARMOperand::CreateToken(Mnemonic, MLoc));
7036 Operands.erase(Operands.begin() + 1);
7037 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
7038 Mnemonic.size() + CarrySetting);
7039 Operands.insert(Operands.begin() + 1,
7040 ARMOperand::CreateVPTPred(
7041 ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
7043 } else if (CanAcceptVPTPredicationCode) {
7044 // For all other instructions, make sure only one of the two
7045 // predication operands is left behind, depending on whether we should
7046 // use the vector predication.
7047 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
7048 if (CanAcceptPredicationCode)
7049 Operands.erase(Operands.begin() + 2);
7050 else
7051 Operands.erase(Operands.begin() + 1);
7052 } else if (CanAcceptPredicationCode && PredicationCode == ARMCC::AL) {
7053 Operands.erase(Operands.begin() + 1);
7058 if (VPTPredicationCode != ARMVCC::None) {
7059 bool usedVPTPredicationCode = false;
7060 for (unsigned I = 1; I < Operands.size(); ++I)
7061 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7062 usedVPTPredicationCode = true;
7063 if (!usedVPTPredicationCode) {
7064 // If we have a VPT predication code and we haven't just turned it
7065 // into an operand, then it was a mistake for splitMnemonic to
7066 // separate it from the rest of the mnemonic in the first place,
7067 // and this may lead to wrong disassembly (e.g. scalar floating
7068 // point VCMPE is actually a different instruction from VCMP, so
7069 // we mustn't treat them the same). In that situation, glue it
7070 // back on.
7071 Mnemonic = Name.slice(0, Mnemonic.size() + 1);
7072 Operands.erase(Operands.begin());
7073 Operands.insert(Operands.begin(),
7074 ARMOperand::CreateToken(Mnemonic, NameLoc));
7078 // ARM mode 'blx' need special handling, as the register operand version
7079 // is predicable, but the label operand version is not. So, we can't rely
7080 // on the Mnemonic based checking to correctly figure out when to put
7081 // a k_CondCode operand in the list. If we're trying to match the label
7082 // version, remove the k_CondCode operand here.
7083 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
7084 static_cast<ARMOperand &>(*Operands[2]).isImm())
7085 Operands.erase(Operands.begin() + 1);
7087 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
7088 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
7089 // a single GPRPair reg operand is used in the .td file to replace the two
7090 // GPRs. However, when parsing from asm, the two GRPs cannot be
7091 // automatically
7092 // expressed as a GPRPair, so we have to manually merge them.
7093 // FIXME: We would really like to be able to tablegen'erate this.
7094 if (!isThumb() && Operands.size() > 4 &&
7095 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
7096 Mnemonic == "stlexd")) {
7097 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
7098 unsigned Idx = isLoad ? 2 : 3;
7099 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
7100 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
7102 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
7103 // Adjust only if Op1 and Op2 are GPRs.
7104 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
7105 MRC.contains(Op2.getReg())) {
7106 unsigned Reg1 = Op1.getReg();
7107 unsigned Reg2 = Op2.getReg();
7108 unsigned Rt = MRI->getEncodingValue(Reg1);
7109 unsigned Rt2 = MRI->getEncodingValue(Reg2);
7111 // Rt2 must be Rt + 1 and Rt must be even.
7112 if (Rt + 1 != Rt2 || (Rt & 1)) {
7113 return Error(Op2.getStartLoc(),
7114 isLoad ? "destination operands must be sequential"
7115 : "source operands must be sequential");
7117 unsigned NewReg = MRI->getMatchingSuperReg(
7118 Reg1, ARM::gsub_0, &(MRI->getRegClass(ARM::GPRPairRegClassID)));
7119 Operands[Idx] =
7120 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
7121 Operands.erase(Operands.begin() + Idx + 1);
7125 // GNU Assembler extension (compatibility).
7126 fixupGNULDRDAlias(Mnemonic, Operands);
7128 // FIXME: As said above, this is all a pretty gross hack. This instruction
7129 // does not fit with other "subs" and tblgen.
7130 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
7131 // so the Mnemonic is the original name "subs" and delete the predicate
7132 // operand so it will match the table entry.
7133 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
7134 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
7135 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
7136 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
7137 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
7138 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
7139 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
7140 Operands.erase(Operands.begin() + 1);
7142 return false;
7145 // Validate context-sensitive operand constraints.
7147 // return 'true' if register list contains non-low GPR registers,
7148 // 'false' otherwise. If Reg is in the register list or is HiReg, set
7149 // 'containsReg' to true.
7150 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
7151 unsigned Reg, unsigned HiReg,
7152 bool &containsReg) {
7153 containsReg = false;
7154 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
7155 unsigned OpReg = Inst.getOperand(i).getReg();
7156 if (OpReg == Reg)
7157 containsReg = true;
7158 // Anything other than a low register isn't legal here.
7159 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
7160 return true;
7162 return false;
7165 // Check if the specified regisgter is in the register list of the inst,
7166 // starting at the indicated operand number.
7167 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
7168 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
7169 unsigned OpReg = Inst.getOperand(i).getReg();
7170 if (OpReg == Reg)
7171 return true;
7173 return false;
7176 // Return true if instruction has the interesting property of being
7177 // allowed in IT blocks, but not being predicable.
7178 static bool instIsBreakpoint(const MCInst &Inst) {
7179 return Inst.getOpcode() == ARM::tBKPT ||
7180 Inst.getOpcode() == ARM::BKPT ||
7181 Inst.getOpcode() == ARM::tHLT ||
7182 Inst.getOpcode() == ARM::HLT;
7185 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
7186 const OperandVector &Operands,
7187 unsigned ListNo, bool IsARPop) {
7188 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7189 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7191 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7192 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
7193 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7195 if (!IsARPop && ListContainsSP)
7196 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7197 "SP may not be in the register list");
7198 else if (ListContainsPC && ListContainsLR)
7199 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7200 "PC and LR may not be in the register list simultaneously");
7201 return false;
7204 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
7205 const OperandVector &Operands,
7206 unsigned ListNo) {
7207 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
7208 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
7210 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7211 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
7213 if (ListContainsSP && ListContainsPC)
7214 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7215 "SP and PC may not be in the register list");
7216 else if (ListContainsSP)
7217 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7218 "SP may not be in the register list");
7219 else if (ListContainsPC)
7220 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
7221 "PC may not be in the register list");
7222 return false;
7225 bool ARMAsmParser::validateLDRDSTRD(MCInst &Inst,
7226 const OperandVector &Operands,
7227 bool Load, bool ARMMode, bool Writeback) {
7228 unsigned RtIndex = Load || !Writeback ? 0 : 1;
7229 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg());
7230 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg());
7232 if (ARMMode) {
7233 // Rt can't be R14.
7234 if (Rt == 14)
7235 return Error(Operands[3]->getStartLoc(),
7236 "Rt can't be R14");
7238 // Rt must be even-numbered.
7239 if ((Rt & 1) == 1)
7240 return Error(Operands[3]->getStartLoc(),
7241 "Rt must be even-numbered");
7243 // Rt2 must be Rt + 1.
7244 if (Rt2 != Rt + 1) {
7245 if (Load)
7246 return Error(Operands[3]->getStartLoc(),
7247 "destination operands must be sequential");
7248 else
7249 return Error(Operands[3]->getStartLoc(),
7250 "source operands must be sequential");
7253 // FIXME: Diagnose m == 15
7254 // FIXME: Diagnose ldrd with m == t || m == t2.
7257 if (!ARMMode && Load) {
7258 if (Rt2 == Rt)
7259 return Error(Operands[3]->getStartLoc(),
7260 "destination operands can't be identical");
7263 if (Writeback) {
7264 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7266 if (Rn == Rt || Rn == Rt2) {
7267 if (Load)
7268 return Error(Operands[3]->getStartLoc(),
7269 "base register needs to be different from destination "
7270 "registers");
7271 else
7272 return Error(Operands[3]->getStartLoc(),
7273 "source register and base register can't be identical");
7276 // FIXME: Diagnose ldrd/strd with writeback and n == 15.
7277 // (Except the immediate form of ldrd?)
7280 return false;
7283 static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
7284 for (unsigned i = 0; i < MCID.NumOperands; ++i) {
7285 if (ARM::isVpred(MCID.OpInfo[i].OperandType))
7286 return i;
7288 return -1;
7291 static bool isVectorPredicable(const MCInstrDesc &MCID) {
7292 return findFirstVectorPredOperandIdx(MCID) != -1;
7295 // FIXME: We would really like to be able to tablegen'erate this.
7296 bool ARMAsmParser::validateInstruction(MCInst &Inst,
7297 const OperandVector &Operands) {
7298 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
7299 SMLoc Loc = Operands[0]->getStartLoc();
7301 // Check the IT block state first.
7302 // NOTE: BKPT and HLT instructions have the interesting property of being
7303 // allowed in IT blocks, but not being predicable. They just always execute.
7304 if (inITBlock() && !instIsBreakpoint(Inst)) {
7305 // The instruction must be predicable.
7306 if (!MCID.isPredicable())
7307 return Error(Loc, "instructions in IT block must be predicable");
7308 ARMCC::CondCodes Cond = ARMCC::CondCodes(
7309 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm());
7310 if (Cond != currentITCond()) {
7311 // Find the condition code Operand to get its SMLoc information.
7312 SMLoc CondLoc;
7313 for (unsigned I = 1; I < Operands.size(); ++I)
7314 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
7315 CondLoc = Operands[I]->getStartLoc();
7316 return Error(CondLoc, "incorrect condition in IT block; got '" +
7317 StringRef(ARMCondCodeToString(Cond)) +
7318 "', but expected '" +
7319 ARMCondCodeToString(currentITCond()) + "'");
7321 // Check for non-'al' condition codes outside of the IT block.
7322 } else if (isThumbTwo() && MCID.isPredicable() &&
7323 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7324 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
7325 Inst.getOpcode() != ARM::t2Bcc &&
7326 Inst.getOpcode() != ARM::t2BFic) {
7327 return Error(Loc, "predicated instructions must be in IT block");
7328 } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
7329 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
7330 ARMCC::AL) {
7331 return Warning(Loc, "predicated instructions should be in IT block");
7332 } else if (!MCID.isPredicable()) {
7333 // Check the instruction doesn't have a predicate operand anyway
7334 // that it's not allowed to use. Sometimes this happens in order
7335 // to keep instructions the same shape even though one cannot
7336 // legally be predicated, e.g. vmul.f16 vs vmul.f32.
7337 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
7338 if (MCID.OpInfo[i].isPredicate()) {
7339 if (Inst.getOperand(i).getImm() != ARMCC::AL)
7340 return Error(Loc, "instruction is not predicable");
7341 break;
7346 // PC-setting instructions in an IT block, but not the last instruction of
7347 // the block, are UNPREDICTABLE.
7348 if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
7349 return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
7352 if (inVPTBlock() && !instIsBreakpoint(Inst)) {
7353 unsigned Bit = extractITMaskBit(VPTState.Mask, VPTState.CurPosition);
7354 if (!isVectorPredicable(MCID))
7355 return Error(Loc, "instruction in VPT block must be predicable");
7356 unsigned Pred = Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm();
7357 unsigned VPTPred = Bit ? ARMVCC::Else : ARMVCC::Then;
7358 if (Pred != VPTPred) {
7359 SMLoc PredLoc;
7360 for (unsigned I = 1; I < Operands.size(); ++I)
7361 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred())
7362 PredLoc = Operands[I]->getStartLoc();
7363 return Error(PredLoc, "incorrect predication in VPT block; got '" +
7364 StringRef(ARMVPTPredToString(ARMVCC::VPTCodes(Pred))) +
7365 "', but expected '" +
7366 ARMVPTPredToString(ARMVCC::VPTCodes(VPTPred)) + "'");
7369 else if (isVectorPredicable(MCID) &&
7370 Inst.getOperand(findFirstVectorPredOperandIdx(MCID)).getImm() !=
7371 ARMVCC::None)
7372 return Error(Loc, "VPT predicated instructions must be in VPT block");
7374 const unsigned Opcode = Inst.getOpcode();
7375 switch (Opcode) {
7376 case ARM::t2IT: {
7377 // Encoding is unpredictable if it ever results in a notional 'NV'
7378 // predicate. Since we don't parse 'NV' directly this means an 'AL'
7379 // predicate with an "else" mask bit.
7380 unsigned Cond = Inst.getOperand(0).getImm();
7381 unsigned Mask = Inst.getOperand(1).getImm();
7383 // Conditions only allowing a 't' are those with no set bit except
7384 // the lowest-order one that indicates the end of the sequence. In
7385 // other words, powers of 2.
7386 if (Cond == ARMCC::AL && countPopulation(Mask) != 1)
7387 return Error(Loc, "unpredictable IT predicate sequence");
7388 break;
7390 case ARM::LDRD:
7391 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7392 /*Writeback*/false))
7393 return true;
7394 break;
7395 case ARM::LDRD_PRE:
7396 case ARM::LDRD_POST:
7397 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true,
7398 /*Writeback*/true))
7399 return true;
7400 break;
7401 case ARM::t2LDRDi8:
7402 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7403 /*Writeback*/false))
7404 return true;
7405 break;
7406 case ARM::t2LDRD_PRE:
7407 case ARM::t2LDRD_POST:
7408 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false,
7409 /*Writeback*/true))
7410 return true;
7411 break;
7412 case ARM::t2BXJ: {
7413 const unsigned RmReg = Inst.getOperand(0).getReg();
7414 // Rm = SP is no longer unpredictable in v8-A
7415 if (RmReg == ARM::SP && !hasV8Ops())
7416 return Error(Operands[2]->getStartLoc(),
7417 "r13 (SP) is an unpredictable operand to BXJ");
7418 return false;
7420 case ARM::STRD:
7421 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7422 /*Writeback*/false))
7423 return true;
7424 break;
7425 case ARM::STRD_PRE:
7426 case ARM::STRD_POST:
7427 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true,
7428 /*Writeback*/true))
7429 return true;
7430 break;
7431 case ARM::t2STRD_PRE:
7432 case ARM::t2STRD_POST:
7433 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false,
7434 /*Writeback*/true))
7435 return true;
7436 break;
7437 case ARM::STR_PRE_IMM:
7438 case ARM::STR_PRE_REG:
7439 case ARM::t2STR_PRE:
7440 case ARM::STR_POST_IMM:
7441 case ARM::STR_POST_REG:
7442 case ARM::t2STR_POST:
7443 case ARM::STRH_PRE:
7444 case ARM::t2STRH_PRE:
7445 case ARM::STRH_POST:
7446 case ARM::t2STRH_POST:
7447 case ARM::STRB_PRE_IMM:
7448 case ARM::STRB_PRE_REG:
7449 case ARM::t2STRB_PRE:
7450 case ARM::STRB_POST_IMM:
7451 case ARM::STRB_POST_REG:
7452 case ARM::t2STRB_POST: {
7453 // Rt must be different from Rn.
7454 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7455 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7457 if (Rt == Rn)
7458 return Error(Operands[3]->getStartLoc(),
7459 "source register and base register can't be identical");
7460 return false;
7462 case ARM::LDR_PRE_IMM:
7463 case ARM::LDR_PRE_REG:
7464 case ARM::t2LDR_PRE:
7465 case ARM::LDR_POST_IMM:
7466 case ARM::LDR_POST_REG:
7467 case ARM::t2LDR_POST:
7468 case ARM::LDRH_PRE:
7469 case ARM::t2LDRH_PRE:
7470 case ARM::LDRH_POST:
7471 case ARM::t2LDRH_POST:
7472 case ARM::LDRSH_PRE:
7473 case ARM::t2LDRSH_PRE:
7474 case ARM::LDRSH_POST:
7475 case ARM::t2LDRSH_POST:
7476 case ARM::LDRB_PRE_IMM:
7477 case ARM::LDRB_PRE_REG:
7478 case ARM::t2LDRB_PRE:
7479 case ARM::LDRB_POST_IMM:
7480 case ARM::LDRB_POST_REG:
7481 case ARM::t2LDRB_POST:
7482 case ARM::LDRSB_PRE:
7483 case ARM::t2LDRSB_PRE:
7484 case ARM::LDRSB_POST:
7485 case ARM::t2LDRSB_POST: {
7486 // Rt must be different from Rn.
7487 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7488 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7490 if (Rt == Rn)
7491 return Error(Operands[3]->getStartLoc(),
7492 "destination register and base register can't be identical");
7493 return false;
7496 case ARM::MVE_VLDRBU8_rq:
7497 case ARM::MVE_VLDRBU16_rq:
7498 case ARM::MVE_VLDRBS16_rq:
7499 case ARM::MVE_VLDRBU32_rq:
7500 case ARM::MVE_VLDRBS32_rq:
7501 case ARM::MVE_VLDRHU16_rq:
7502 case ARM::MVE_VLDRHU16_rq_u:
7503 case ARM::MVE_VLDRHU32_rq:
7504 case ARM::MVE_VLDRHU32_rq_u:
7505 case ARM::MVE_VLDRHS32_rq:
7506 case ARM::MVE_VLDRHS32_rq_u:
7507 case ARM::MVE_VLDRWU32_rq:
7508 case ARM::MVE_VLDRWU32_rq_u:
7509 case ARM::MVE_VLDRDU64_rq:
7510 case ARM::MVE_VLDRDU64_rq_u:
7511 case ARM::MVE_VLDRWU32_qi:
7512 case ARM::MVE_VLDRWU32_qi_pre:
7513 case ARM::MVE_VLDRDU64_qi:
7514 case ARM::MVE_VLDRDU64_qi_pre: {
7515 // Qd must be different from Qm.
7516 unsigned QdIdx = 0, QmIdx = 2;
7517 bool QmIsPointer = false;
7518 switch (Opcode) {
7519 case ARM::MVE_VLDRWU32_qi:
7520 case ARM::MVE_VLDRDU64_qi:
7521 QmIdx = 1;
7522 QmIsPointer = true;
7523 break;
7524 case ARM::MVE_VLDRWU32_qi_pre:
7525 case ARM::MVE_VLDRDU64_qi_pre:
7526 QdIdx = 1;
7527 QmIsPointer = true;
7528 break;
7531 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());
7532 const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());
7534 if (Qd == Qm) {
7535 return Error(Operands[3]->getStartLoc(),
7536 Twine("destination vector register and vector ") +
7537 (QmIsPointer ? "pointer" : "offset") +
7538 " register can't be identical");
7540 return false;
7543 case ARM::SBFX:
7544 case ARM::t2SBFX:
7545 case ARM::UBFX:
7546 case ARM::t2UBFX: {
7547 // Width must be in range [1, 32-lsb].
7548 unsigned LSB = Inst.getOperand(2).getImm();
7549 unsigned Widthm1 = Inst.getOperand(3).getImm();
7550 if (Widthm1 >= 32 - LSB)
7551 return Error(Operands[5]->getStartLoc(),
7552 "bitfield width must be in range [1,32-lsb]");
7553 return false;
7555 // Notionally handles ARM::tLDMIA_UPD too.
7556 case ARM::tLDMIA: {
7557 // If we're parsing Thumb2, the .w variant is available and handles
7558 // most cases that are normally illegal for a Thumb1 LDM instruction.
7559 // We'll make the transformation in processInstruction() if necessary.
7561 // Thumb LDM instructions are writeback iff the base register is not
7562 // in the register list.
7563 unsigned Rn = Inst.getOperand(0).getReg();
7564 bool HasWritebackToken =
7565 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7566 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7567 bool ListContainsBase;
7568 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
7569 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
7570 "registers must be in range r0-r7");
7571 // If we should have writeback, then there should be a '!' token.
7572 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
7573 return Error(Operands[2]->getStartLoc(),
7574 "writeback operator '!' expected");
7575 // If we should not have writeback, there must not be a '!'. This is
7576 // true even for the 32-bit wide encodings.
7577 if (ListContainsBase && HasWritebackToken)
7578 return Error(Operands[3]->getStartLoc(),
7579 "writeback operator '!' not allowed when base register "
7580 "in register list");
7582 if (validatetLDMRegList(Inst, Operands, 3))
7583 return true;
7584 break;
7586 case ARM::LDMIA_UPD:
7587 case ARM::LDMDB_UPD:
7588 case ARM::LDMIB_UPD:
7589 case ARM::LDMDA_UPD:
7590 // ARM variants loading and updating the same register are only officially
7591 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
7592 if (!hasV7Ops())
7593 break;
7594 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7595 return Error(Operands.back()->getStartLoc(),
7596 "writeback register not allowed in register list");
7597 break;
7598 case ARM::t2LDMIA:
7599 case ARM::t2LDMDB:
7600 if (validatetLDMRegList(Inst, Operands, 3))
7601 return true;
7602 break;
7603 case ARM::t2STMIA:
7604 case ARM::t2STMDB:
7605 if (validatetSTMRegList(Inst, Operands, 3))
7606 return true;
7607 break;
7608 case ARM::t2LDMIA_UPD:
7609 case ARM::t2LDMDB_UPD:
7610 case ARM::t2STMIA_UPD:
7611 case ARM::t2STMDB_UPD:
7612 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
7613 return Error(Operands.back()->getStartLoc(),
7614 "writeback register not allowed in register list");
7616 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
7617 if (validatetLDMRegList(Inst, Operands, 3))
7618 return true;
7619 } else {
7620 if (validatetSTMRegList(Inst, Operands, 3))
7621 return true;
7623 break;
7625 case ARM::sysLDMIA_UPD:
7626 case ARM::sysLDMDA_UPD:
7627 case ARM::sysLDMDB_UPD:
7628 case ARM::sysLDMIB_UPD:
7629 if (!listContainsReg(Inst, 3, ARM::PC))
7630 return Error(Operands[4]->getStartLoc(),
7631 "writeback register only allowed on system LDM "
7632 "if PC in register-list");
7633 break;
7634 case ARM::sysSTMIA_UPD:
7635 case ARM::sysSTMDA_UPD:
7636 case ARM::sysSTMDB_UPD:
7637 case ARM::sysSTMIB_UPD:
7638 return Error(Operands[2]->getStartLoc(),
7639 "system STM cannot have writeback register");
7640 case ARM::tMUL:
7641 // The second source operand must be the same register as the destination
7642 // operand.
7644 // In this case, we must directly check the parsed operands because the
7645 // cvtThumbMultiply() function is written in such a way that it guarantees
7646 // this first statement is always true for the new Inst. Essentially, the
7647 // destination is unconditionally copied into the second source operand
7648 // without checking to see if it matches what we actually parsed.
7649 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
7650 ((ARMOperand &)*Operands[5]).getReg()) &&
7651 (((ARMOperand &)*Operands[3]).getReg() !=
7652 ((ARMOperand &)*Operands[4]).getReg())) {
7653 return Error(Operands[3]->getStartLoc(),
7654 "destination register must match source register");
7656 break;
7658 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
7659 // so only issue a diagnostic for thumb1. The instructions will be
7660 // switched to the t2 encodings in processInstruction() if necessary.
7661 case ARM::tPOP: {
7662 bool ListContainsBase;
7663 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
7664 !isThumbTwo())
7665 return Error(Operands[2]->getStartLoc(),
7666 "registers must be in range r0-r7 or pc");
7667 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
7668 return true;
7669 break;
7671 case ARM::tPUSH: {
7672 bool ListContainsBase;
7673 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
7674 !isThumbTwo())
7675 return Error(Operands[2]->getStartLoc(),
7676 "registers must be in range r0-r7 or lr");
7677 if (validatetSTMRegList(Inst, Operands, 2))
7678 return true;
7679 break;
7681 case ARM::tSTMIA_UPD: {
7682 bool ListContainsBase, InvalidLowList;
7683 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
7684 0, ListContainsBase);
7685 if (InvalidLowList && !isThumbTwo())
7686 return Error(Operands[4]->getStartLoc(),
7687 "registers must be in range r0-r7");
7689 // This would be converted to a 32-bit stm, but that's not valid if the
7690 // writeback register is in the list.
7691 if (InvalidLowList && ListContainsBase)
7692 return Error(Operands[4]->getStartLoc(),
7693 "writeback operator '!' not allowed when base register "
7694 "in register list");
7696 if (validatetSTMRegList(Inst, Operands, 4))
7697 return true;
7698 break;
7700 case ARM::tADDrSP:
7701 // If the non-SP source operand and the destination operand are not the
7702 // same, we need thumb2 (for the wide encoding), or we have an error.
7703 if (!isThumbTwo() &&
7704 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7705 return Error(Operands[4]->getStartLoc(),
7706 "source register must be the same as destination");
7708 break;
7710 case ARM::t2ADDri:
7711 case ARM::t2ADDri12:
7712 case ARM::t2ADDrr:
7713 case ARM::t2ADDrs:
7714 case ARM::t2SUBri:
7715 case ARM::t2SUBri12:
7716 case ARM::t2SUBrr:
7717 case ARM::t2SUBrs:
7718 if (Inst.getOperand(0).getReg() == ARM::SP &&
7719 Inst.getOperand(1).getReg() != ARM::SP)
7720 return Error(Operands[4]->getStartLoc(),
7721 "source register must be sp if destination is sp");
7722 break;
7724 // Final range checking for Thumb unconditional branch instructions.
7725 case ARM::tB:
7726 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
7727 return Error(Operands[2]->getStartLoc(), "branch target out of range");
7728 break;
7729 case ARM::t2B: {
7730 int op = (Operands[2]->isImm()) ? 2 : 3;
7731 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
7732 return Error(Operands[op]->getStartLoc(), "branch target out of range");
7733 break;
7735 // Final range checking for Thumb conditional branch instructions.
7736 case ARM::tBcc:
7737 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
7738 return Error(Operands[2]->getStartLoc(), "branch target out of range");
7739 break;
7740 case ARM::t2Bcc: {
7741 int Op = (Operands[2]->isImm()) ? 2 : 3;
7742 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
7743 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
7744 break;
7746 case ARM::tCBZ:
7747 case ARM::tCBNZ: {
7748 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
7749 return Error(Operands[2]->getStartLoc(), "branch target out of range");
7750 break;
7752 case ARM::MOVi16:
7753 case ARM::MOVTi16:
7754 case ARM::t2MOVi16:
7755 case ARM::t2MOVTi16:
7757 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
7758 // especially when we turn it into a movw and the expression <symbol> does
7759 // not have a :lower16: or :upper16 as part of the expression. We don't
7760 // want the behavior of silently truncating, which can be unexpected and
7761 // lead to bugs that are difficult to find since this is an easy mistake
7762 // to make.
7763 int i = (Operands[3]->isImm()) ? 3 : 4;
7764 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
7765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
7766 if (CE) break;
7767 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
7768 if (!E) break;
7769 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
7770 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
7771 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
7772 return Error(
7773 Op.getStartLoc(),
7774 "immediate expression for mov requires :lower16: or :upper16");
7775 break;
7777 case ARM::HINT:
7778 case ARM::t2HINT: {
7779 unsigned Imm8 = Inst.getOperand(0).getImm();
7780 unsigned Pred = Inst.getOperand(1).getImm();
7781 // ESB is not predicable (pred must be AL). Without the RAS extension, this
7782 // behaves as any other unallocated hint.
7783 if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
7784 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
7785 "predicable, but condition "
7786 "code specified");
7787 if (Imm8 == 0x14 && Pred != ARMCC::AL)
7788 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
7789 "predicable, but condition "
7790 "code specified");
7791 break;
7793 case ARM::t2BFi:
7794 case ARM::t2BFr:
7795 case ARM::t2BFLi:
7796 case ARM::t2BFLr: {
7797 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() ||
7798 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
7799 return Error(Operands[2]->getStartLoc(),
7800 "branch location out of range or not a multiple of 2");
7802 if (Opcode == ARM::t2BFi) {
7803 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>())
7804 return Error(Operands[3]->getStartLoc(),
7805 "branch target out of range or not a multiple of 2");
7806 } else if (Opcode == ARM::t2BFLi) {
7807 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>())
7808 return Error(Operands[3]->getStartLoc(),
7809 "branch target out of range or not a multiple of 2");
7811 break;
7813 case ARM::t2BFic: {
7814 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() ||
7815 (Inst.getOperand(0).isImm() && Inst.getOperand(0).getImm() == 0))
7816 return Error(Operands[1]->getStartLoc(),
7817 "branch location out of range or not a multiple of 2");
7819 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>())
7820 return Error(Operands[2]->getStartLoc(),
7821 "branch target out of range or not a multiple of 2");
7823 assert(Inst.getOperand(0).isImm() == Inst.getOperand(2).isImm() &&
7824 "branch location and else branch target should either both be "
7825 "immediates or both labels");
7827 if (Inst.getOperand(0).isImm() && Inst.getOperand(2).isImm()) {
7828 int Diff = Inst.getOperand(2).getImm() - Inst.getOperand(0).getImm();
7829 if (Diff != 4 && Diff != 2)
7830 return Error(
7831 Operands[3]->getStartLoc(),
7832 "else branch target must be 2 or 4 greater than the branch location");
7834 break;
7836 case ARM::t2CLRM: {
7837 for (unsigned i = 2; i < Inst.getNumOperands(); i++) {
7838 if (Inst.getOperand(i).isReg() &&
7839 !ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(
7840 Inst.getOperand(i).getReg())) {
7841 return Error(Operands[2]->getStartLoc(),
7842 "invalid register in register list. Valid registers are "
7843 "r0-r12, lr/r14 and APSR.");
7846 break;
7848 case ARM::DSB:
7849 case ARM::t2DSB: {
7851 if (Inst.getNumOperands() < 2)
7852 break;
7854 unsigned Option = Inst.getOperand(0).getImm();
7855 unsigned Pred = Inst.getOperand(1).getImm();
7857 // SSBB and PSSBB (DSB #0|#4) are not predicable (pred must be AL).
7858 if (Option == 0 && Pred != ARMCC::AL)
7859 return Error(Operands[1]->getStartLoc(),
7860 "instruction 'ssbb' is not predicable, but condition code "
7861 "specified");
7862 if (Option == 4 && Pred != ARMCC::AL)
7863 return Error(Operands[1]->getStartLoc(),
7864 "instruction 'pssbb' is not predicable, but condition code "
7865 "specified");
7866 break;
7868 case ARM::VMOVRRS: {
7869 // Source registers must be sequential.
7870 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7871 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7872 if (Sm1 != Sm + 1)
7873 return Error(Operands[5]->getStartLoc(),
7874 "source operands must be sequential");
7875 break;
7877 case ARM::VMOVSRR: {
7878 // Destination registers must be sequential.
7879 const unsigned Sm = MRI->getEncodingValue(Inst.getOperand(0).getReg());
7880 const unsigned Sm1 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
7881 if (Sm1 != Sm + 1)
7882 return Error(Operands[3]->getStartLoc(),
7883 "destination operands must be sequential");
7884 break;
7886 case ARM::VLDMDIA:
7887 case ARM::VSTMDIA: {
7888 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
7889 auto &RegList = Op.getRegList();
7890 if (RegList.size() < 1 || RegList.size() > 16)
7891 return Error(Operands[3]->getStartLoc(),
7892 "list of registers must be at least 1 and at most 16");
7893 break;
7895 case ARM::MVE_VQDMULLs32bh:
7896 case ARM::MVE_VQDMULLs32th:
7897 case ARM::MVE_VCMULf32:
7898 case ARM::MVE_VMULLs32bh:
7899 case ARM::MVE_VMULLs32th:
7900 case ARM::MVE_VMULLu32bh:
7901 case ARM::MVE_VMULLu32th: {
7902 if (Operands[3]->getReg() == Operands[4]->getReg()) {
7903 return Error (Operands[3]->getStartLoc(),
7904 "Qd register and Qn register can't be identical");
7906 if (Operands[3]->getReg() == Operands[5]->getReg()) {
7907 return Error (Operands[3]->getStartLoc(),
7908 "Qd register and Qm register can't be identical");
7910 break;
7912 case ARM::MVE_VMOV_rr_q: {
7913 if (Operands[4]->getReg() != Operands[6]->getReg())
7914 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same");
7915 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() !=
7916 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2)
7917 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
7918 break;
7920 case ARM::MVE_VMOV_q_rr: {
7921 if (Operands[2]->getReg() != Operands[4]->getReg())
7922 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same");
7923 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() !=
7924 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2)
7925 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
7926 break;
7930 return false;
7933 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
7934 switch(Opc) {
7935 default: llvm_unreachable("unexpected opcode!");
7936 // VST1LN
7937 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
7938 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
7939 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
7940 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
7941 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
7942 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
7943 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
7944 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
7945 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
7947 // VST2LN
7948 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
7949 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
7950 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
7951 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
7952 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
7954 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
7955 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
7956 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
7957 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
7958 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
7960 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
7961 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
7962 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
7963 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
7964 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
7966 // VST3LN
7967 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
7968 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
7969 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
7970 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
7971 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
7972 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
7973 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
7974 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
7975 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
7976 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
7977 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
7978 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
7979 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
7980 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
7981 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
7983 // VST3
7984 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
7985 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
7986 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
7987 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
7988 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
7989 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
7990 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
7991 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
7992 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
7993 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
7994 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
7995 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
7996 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
7997 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
7998 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
7999 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
8000 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
8001 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
8003 // VST4LN
8004 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
8005 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8006 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8007 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
8008 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8009 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
8010 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
8011 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
8012 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
8013 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
8014 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
8015 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
8016 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
8017 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
8018 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
8020 // VST4
8021 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
8022 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8023 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8024 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
8025 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8026 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8027 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
8028 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
8029 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
8030 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
8031 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
8032 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
8033 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
8034 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
8035 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
8036 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
8037 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
8038 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
8042 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
8043 switch(Opc) {
8044 default: llvm_unreachable("unexpected opcode!");
8045 // VLD1LN
8046 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
8047 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8048 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8049 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
8050 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
8051 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
8052 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
8053 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
8054 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
8056 // VLD2LN
8057 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
8058 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8059 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8060 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
8061 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8062 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
8063 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
8064 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
8065 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
8066 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
8067 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
8068 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
8069 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
8070 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
8071 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
8073 // VLD3DUP
8074 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
8075 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8076 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8077 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
8078 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8079 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8080 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
8081 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
8082 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
8083 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
8084 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
8085 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
8086 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
8087 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
8088 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
8089 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
8090 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
8091 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
8093 // VLD3LN
8094 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
8095 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8096 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8097 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
8098 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8099 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
8100 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
8101 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
8102 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
8103 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
8104 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
8105 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
8106 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
8107 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
8108 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
8110 // VLD3
8111 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
8112 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8113 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8114 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
8115 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8116 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8117 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
8118 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
8119 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
8120 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
8121 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
8122 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
8123 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
8124 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
8125 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
8126 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
8127 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
8128 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
8130 // VLD4LN
8131 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
8132 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8133 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8134 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8135 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8136 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
8137 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
8138 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
8139 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
8140 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
8141 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
8142 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
8143 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
8144 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
8145 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
8147 // VLD4DUP
8148 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
8149 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8150 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8151 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
8152 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
8153 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8154 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
8155 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
8156 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
8157 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
8158 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
8159 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
8160 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
8161 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
8162 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
8163 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
8164 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
8165 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
8167 // VLD4
8168 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
8169 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8170 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8171 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
8172 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8173 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8174 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
8175 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
8176 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
8177 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
8178 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
8179 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
8180 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
8181 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
8182 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
8183 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
8184 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
8185 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
8189 bool ARMAsmParser::processInstruction(MCInst &Inst,
8190 const OperandVector &Operands,
8191 MCStreamer &Out) {
8192 // Check if we have the wide qualifier, because if it's present we
8193 // must avoid selecting a 16-bit thumb instruction.
8194 bool HasWideQualifier = false;
8195 for (auto &Op : Operands) {
8196 ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
8197 if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
8198 HasWideQualifier = true;
8199 break;
8203 switch (Inst.getOpcode()) {
8204 case ARM::MVE_VORNIZ0v4i32:
8205 case ARM::MVE_VORNIZ0v8i16:
8206 case ARM::MVE_VORNIZ8v4i32:
8207 case ARM::MVE_VORNIZ8v8i16:
8208 case ARM::MVE_VORNIZ16v4i32:
8209 case ARM::MVE_VORNIZ24v4i32:
8210 case ARM::MVE_VANDIZ0v4i32:
8211 case ARM::MVE_VANDIZ0v8i16:
8212 case ARM::MVE_VANDIZ8v4i32:
8213 case ARM::MVE_VANDIZ8v8i16:
8214 case ARM::MVE_VANDIZ16v4i32:
8215 case ARM::MVE_VANDIZ24v4i32: {
8216 unsigned Opcode;
8217 bool imm16 = false;
8218 switch(Inst.getOpcode()) {
8219 case ARM::MVE_VORNIZ0v4i32: Opcode = ARM::MVE_VORRIZ0v4i32; break;
8220 case ARM::MVE_VORNIZ0v8i16: Opcode = ARM::MVE_VORRIZ0v8i16; imm16 = true; break;
8221 case ARM::MVE_VORNIZ8v4i32: Opcode = ARM::MVE_VORRIZ8v4i32; break;
8222 case ARM::MVE_VORNIZ8v8i16: Opcode = ARM::MVE_VORRIZ8v8i16; imm16 = true; break;
8223 case ARM::MVE_VORNIZ16v4i32: Opcode = ARM::MVE_VORRIZ16v4i32; break;
8224 case ARM::MVE_VORNIZ24v4i32: Opcode = ARM::MVE_VORRIZ24v4i32; break;
8225 case ARM::MVE_VANDIZ0v4i32: Opcode = ARM::MVE_VBICIZ0v4i32; break;
8226 case ARM::MVE_VANDIZ0v8i16: Opcode = ARM::MVE_VBICIZ0v8i16; imm16 = true; break;
8227 case ARM::MVE_VANDIZ8v4i32: Opcode = ARM::MVE_VBICIZ8v4i32; break;
8228 case ARM::MVE_VANDIZ8v8i16: Opcode = ARM::MVE_VBICIZ8v8i16; imm16 = true; break;
8229 case ARM::MVE_VANDIZ16v4i32: Opcode = ARM::MVE_VBICIZ16v4i32; break;
8230 case ARM::MVE_VANDIZ24v4i32: Opcode = ARM::MVE_VBICIZ24v4i32; break;
8231 default: llvm_unreachable("unexpected opcode");
8234 MCInst TmpInst;
8235 TmpInst.setOpcode(Opcode);
8236 TmpInst.addOperand(Inst.getOperand(0));
8237 TmpInst.addOperand(Inst.getOperand(1));
8239 // invert immediate
8240 unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff);
8241 TmpInst.addOperand(MCOperand::createImm(imm));
8243 TmpInst.addOperand(Inst.getOperand(3));
8244 TmpInst.addOperand(Inst.getOperand(4));
8245 Inst = TmpInst;
8246 return true;
8248 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
8249 case ARM::LDRT_POST:
8250 case ARM::LDRBT_POST: {
8251 const unsigned Opcode =
8252 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
8253 : ARM::LDRBT_POST_IMM;
8254 MCInst TmpInst;
8255 TmpInst.setOpcode(Opcode);
8256 TmpInst.addOperand(Inst.getOperand(0));
8257 TmpInst.addOperand(Inst.getOperand(1));
8258 TmpInst.addOperand(Inst.getOperand(1));
8259 TmpInst.addOperand(MCOperand::createReg(0));
8260 TmpInst.addOperand(MCOperand::createImm(0));
8261 TmpInst.addOperand(Inst.getOperand(2));
8262 TmpInst.addOperand(Inst.getOperand(3));
8263 Inst = TmpInst;
8264 return true;
8266 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
8267 case ARM::STRT_POST:
8268 case ARM::STRBT_POST: {
8269 const unsigned Opcode =
8270 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
8271 : ARM::STRBT_POST_IMM;
8272 MCInst TmpInst;
8273 TmpInst.setOpcode(Opcode);
8274 TmpInst.addOperand(Inst.getOperand(1));
8275 TmpInst.addOperand(Inst.getOperand(0));
8276 TmpInst.addOperand(Inst.getOperand(1));
8277 TmpInst.addOperand(MCOperand::createReg(0));
8278 TmpInst.addOperand(MCOperand::createImm(0));
8279 TmpInst.addOperand(Inst.getOperand(2));
8280 TmpInst.addOperand(Inst.getOperand(3));
8281 Inst = TmpInst;
8282 return true;
8284 // Alias for alternate form of 'ADR Rd, #imm' instruction.
8285 case ARM::ADDri: {
8286 if (Inst.getOperand(1).getReg() != ARM::PC ||
8287 Inst.getOperand(5).getReg() != 0 ||
8288 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
8289 return false;
8290 MCInst TmpInst;
8291 TmpInst.setOpcode(ARM::ADR);
8292 TmpInst.addOperand(Inst.getOperand(0));
8293 if (Inst.getOperand(2).isImm()) {
8294 // Immediate (mod_imm) will be in its encoded form, we must unencode it
8295 // before passing it to the ADR instruction.
8296 unsigned Enc = Inst.getOperand(2).getImm();
8297 TmpInst.addOperand(MCOperand::createImm(
8298 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
8299 } else {
8300 // Turn PC-relative expression into absolute expression.
8301 // Reading PC provides the start of the current instruction + 8 and
8302 // the transform to adr is biased by that.
8303 MCSymbol *Dot = getContext().createTempSymbol();
8304 Out.EmitLabel(Dot);
8305 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
8306 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
8307 MCSymbolRefExpr::VK_None,
8308 getContext());
8309 const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
8310 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
8311 getContext());
8312 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
8313 getContext());
8314 TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
8316 TmpInst.addOperand(Inst.getOperand(3));
8317 TmpInst.addOperand(Inst.getOperand(4));
8318 Inst = TmpInst;
8319 return true;
8321 // Aliases for alternate PC+imm syntax of LDR instructions.
8322 case ARM::t2LDRpcrel:
8323 // Select the narrow version if the immediate will fit.
8324 if (Inst.getOperand(1).getImm() > 0 &&
8325 Inst.getOperand(1).getImm() <= 0xff &&
8326 !HasWideQualifier)
8327 Inst.setOpcode(ARM::tLDRpci);
8328 else
8329 Inst.setOpcode(ARM::t2LDRpci);
8330 return true;
8331 case ARM::t2LDRBpcrel:
8332 Inst.setOpcode(ARM::t2LDRBpci);
8333 return true;
8334 case ARM::t2LDRHpcrel:
8335 Inst.setOpcode(ARM::t2LDRHpci);
8336 return true;
8337 case ARM::t2LDRSBpcrel:
8338 Inst.setOpcode(ARM::t2LDRSBpci);
8339 return true;
8340 case ARM::t2LDRSHpcrel:
8341 Inst.setOpcode(ARM::t2LDRSHpci);
8342 return true;
8343 case ARM::LDRConstPool:
8344 case ARM::tLDRConstPool:
8345 case ARM::t2LDRConstPool: {
8346 // Pseudo instruction ldr rt, =immediate is converted to a
8347 // MOV rt, immediate if immediate is known and representable
8348 // otherwise we create a constant pool entry that we load from.
8349 MCInst TmpInst;
8350 if (Inst.getOpcode() == ARM::LDRConstPool)
8351 TmpInst.setOpcode(ARM::LDRi12);
8352 else if (Inst.getOpcode() == ARM::tLDRConstPool)
8353 TmpInst.setOpcode(ARM::tLDRpci);
8354 else if (Inst.getOpcode() == ARM::t2LDRConstPool)
8355 TmpInst.setOpcode(ARM::t2LDRpci);
8356 const ARMOperand &PoolOperand =
8357 (HasWideQualifier ?
8358 static_cast<ARMOperand &>(*Operands[4]) :
8359 static_cast<ARMOperand &>(*Operands[3]));
8360 const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
8361 // If SubExprVal is a constant we may be able to use a MOV
8362 if (isa<MCConstantExpr>(SubExprVal) &&
8363 Inst.getOperand(0).getReg() != ARM::PC &&
8364 Inst.getOperand(0).getReg() != ARM::SP) {
8365 int64_t Value =
8366 (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
8367 bool UseMov = true;
8368 bool MovHasS = true;
8369 if (Inst.getOpcode() == ARM::LDRConstPool) {
8370 // ARM Constant
8371 if (ARM_AM::getSOImmVal(Value) != -1) {
8372 Value = ARM_AM::getSOImmVal(Value);
8373 TmpInst.setOpcode(ARM::MOVi);
8375 else if (ARM_AM::getSOImmVal(~Value) != -1) {
8376 Value = ARM_AM::getSOImmVal(~Value);
8377 TmpInst.setOpcode(ARM::MVNi);
8379 else if (hasV6T2Ops() &&
8380 Value >=0 && Value < 65536) {
8381 TmpInst.setOpcode(ARM::MOVi16);
8382 MovHasS = false;
8384 else
8385 UseMov = false;
8387 else {
8388 // Thumb/Thumb2 Constant
8389 if (hasThumb2() &&
8390 ARM_AM::getT2SOImmVal(Value) != -1)
8391 TmpInst.setOpcode(ARM::t2MOVi);
8392 else if (hasThumb2() &&
8393 ARM_AM::getT2SOImmVal(~Value) != -1) {
8394 TmpInst.setOpcode(ARM::t2MVNi);
8395 Value = ~Value;
8397 else if (hasV8MBaseline() &&
8398 Value >=0 && Value < 65536) {
8399 TmpInst.setOpcode(ARM::t2MOVi16);
8400 MovHasS = false;
8402 else
8403 UseMov = false;
8405 if (UseMov) {
8406 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8407 TmpInst.addOperand(MCOperand::createImm(Value)); // Immediate
8408 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8409 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8410 if (MovHasS)
8411 TmpInst.addOperand(MCOperand::createReg(0)); // S
8412 Inst = TmpInst;
8413 return true;
8416 // No opportunity to use MOV/MVN create constant pool
8417 const MCExpr *CPLoc =
8418 getTargetStreamer().addConstantPoolEntry(SubExprVal,
8419 PoolOperand.getStartLoc());
8420 TmpInst.addOperand(Inst.getOperand(0)); // Rt
8421 TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
8422 if (TmpInst.getOpcode() == ARM::LDRi12)
8423 TmpInst.addOperand(MCOperand::createImm(0)); // unused offset
8424 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8425 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8426 Inst = TmpInst;
8427 return true;
8429 // Handle NEON VST complex aliases.
8430 case ARM::VST1LNdWB_register_Asm_8:
8431 case ARM::VST1LNdWB_register_Asm_16:
8432 case ARM::VST1LNdWB_register_Asm_32: {
8433 MCInst TmpInst;
8434 // Shuffle the operands around so the lane index operand is in the
8435 // right place.
8436 unsigned Spacing;
8437 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8438 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8439 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8440 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8441 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8442 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8443 TmpInst.addOperand(Inst.getOperand(1)); // lane
8444 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8445 TmpInst.addOperand(Inst.getOperand(6));
8446 Inst = TmpInst;
8447 return true;
8450 case ARM::VST2LNdWB_register_Asm_8:
8451 case ARM::VST2LNdWB_register_Asm_16:
8452 case ARM::VST2LNdWB_register_Asm_32:
8453 case ARM::VST2LNqWB_register_Asm_16:
8454 case ARM::VST2LNqWB_register_Asm_32: {
8455 MCInst TmpInst;
8456 // Shuffle the operands around so the lane index operand is in the
8457 // right place.
8458 unsigned Spacing;
8459 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8460 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8461 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8462 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8463 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8464 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8465 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8466 Spacing));
8467 TmpInst.addOperand(Inst.getOperand(1)); // lane
8468 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8469 TmpInst.addOperand(Inst.getOperand(6));
8470 Inst = TmpInst;
8471 return true;
8474 case ARM::VST3LNdWB_register_Asm_8:
8475 case ARM::VST3LNdWB_register_Asm_16:
8476 case ARM::VST3LNdWB_register_Asm_32:
8477 case ARM::VST3LNqWB_register_Asm_16:
8478 case ARM::VST3LNqWB_register_Asm_32: {
8479 MCInst TmpInst;
8480 // Shuffle the operands around so the lane index operand is in the
8481 // right place.
8482 unsigned Spacing;
8483 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8484 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8485 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8486 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8487 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8488 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8489 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8490 Spacing));
8491 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8492 Spacing * 2));
8493 TmpInst.addOperand(Inst.getOperand(1)); // lane
8494 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8495 TmpInst.addOperand(Inst.getOperand(6));
8496 Inst = TmpInst;
8497 return true;
8500 case ARM::VST4LNdWB_register_Asm_8:
8501 case ARM::VST4LNdWB_register_Asm_16:
8502 case ARM::VST4LNdWB_register_Asm_32:
8503 case ARM::VST4LNqWB_register_Asm_16:
8504 case ARM::VST4LNqWB_register_Asm_32: {
8505 MCInst TmpInst;
8506 // Shuffle the operands around so the lane index operand is in the
8507 // right place.
8508 unsigned Spacing;
8509 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8510 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8511 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8512 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8513 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8514 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8515 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8516 Spacing));
8517 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8518 Spacing * 2));
8519 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8520 Spacing * 3));
8521 TmpInst.addOperand(Inst.getOperand(1)); // lane
8522 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8523 TmpInst.addOperand(Inst.getOperand(6));
8524 Inst = TmpInst;
8525 return true;
8528 case ARM::VST1LNdWB_fixed_Asm_8:
8529 case ARM::VST1LNdWB_fixed_Asm_16:
8530 case ARM::VST1LNdWB_fixed_Asm_32: {
8531 MCInst TmpInst;
8532 // Shuffle the operands around so the lane index operand is in the
8533 // right place.
8534 unsigned Spacing;
8535 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8536 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8537 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8538 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8539 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8540 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8541 TmpInst.addOperand(Inst.getOperand(1)); // lane
8542 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8543 TmpInst.addOperand(Inst.getOperand(5));
8544 Inst = TmpInst;
8545 return true;
8548 case ARM::VST2LNdWB_fixed_Asm_8:
8549 case ARM::VST2LNdWB_fixed_Asm_16:
8550 case ARM::VST2LNdWB_fixed_Asm_32:
8551 case ARM::VST2LNqWB_fixed_Asm_16:
8552 case ARM::VST2LNqWB_fixed_Asm_32: {
8553 MCInst TmpInst;
8554 // Shuffle the operands around so the lane index operand is in the
8555 // right place.
8556 unsigned Spacing;
8557 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8558 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8559 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8560 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8561 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8562 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8563 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8564 Spacing));
8565 TmpInst.addOperand(Inst.getOperand(1)); // lane
8566 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8567 TmpInst.addOperand(Inst.getOperand(5));
8568 Inst = TmpInst;
8569 return true;
8572 case ARM::VST3LNdWB_fixed_Asm_8:
8573 case ARM::VST3LNdWB_fixed_Asm_16:
8574 case ARM::VST3LNdWB_fixed_Asm_32:
8575 case ARM::VST3LNqWB_fixed_Asm_16:
8576 case ARM::VST3LNqWB_fixed_Asm_32: {
8577 MCInst TmpInst;
8578 // Shuffle the operands around so the lane index operand is in the
8579 // right place.
8580 unsigned Spacing;
8581 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8582 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8583 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8584 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8585 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8586 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8587 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8588 Spacing));
8589 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8590 Spacing * 2));
8591 TmpInst.addOperand(Inst.getOperand(1)); // lane
8592 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8593 TmpInst.addOperand(Inst.getOperand(5));
8594 Inst = TmpInst;
8595 return true;
8598 case ARM::VST4LNdWB_fixed_Asm_8:
8599 case ARM::VST4LNdWB_fixed_Asm_16:
8600 case ARM::VST4LNdWB_fixed_Asm_32:
8601 case ARM::VST4LNqWB_fixed_Asm_16:
8602 case ARM::VST4LNqWB_fixed_Asm_32: {
8603 MCInst TmpInst;
8604 // Shuffle the operands around so the lane index operand is in the
8605 // right place.
8606 unsigned Spacing;
8607 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8608 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8609 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8610 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8611 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8612 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8613 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8614 Spacing));
8615 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8616 Spacing * 2));
8617 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8618 Spacing * 3));
8619 TmpInst.addOperand(Inst.getOperand(1)); // lane
8620 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8621 TmpInst.addOperand(Inst.getOperand(5));
8622 Inst = TmpInst;
8623 return true;
8626 case ARM::VST1LNdAsm_8:
8627 case ARM::VST1LNdAsm_16:
8628 case ARM::VST1LNdAsm_32: {
8629 MCInst TmpInst;
8630 // Shuffle the operands around so the lane index operand is in the
8631 // right place.
8632 unsigned Spacing;
8633 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8634 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8635 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8636 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8637 TmpInst.addOperand(Inst.getOperand(1)); // lane
8638 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8639 TmpInst.addOperand(Inst.getOperand(5));
8640 Inst = TmpInst;
8641 return true;
8644 case ARM::VST2LNdAsm_8:
8645 case ARM::VST2LNdAsm_16:
8646 case ARM::VST2LNdAsm_32:
8647 case ARM::VST2LNqAsm_16:
8648 case ARM::VST2LNqAsm_32: {
8649 MCInst TmpInst;
8650 // Shuffle the operands around so the lane index operand is in the
8651 // right place.
8652 unsigned Spacing;
8653 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8654 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8655 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8656 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8657 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8658 Spacing));
8659 TmpInst.addOperand(Inst.getOperand(1)); // lane
8660 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8661 TmpInst.addOperand(Inst.getOperand(5));
8662 Inst = TmpInst;
8663 return true;
8666 case ARM::VST3LNdAsm_8:
8667 case ARM::VST3LNdAsm_16:
8668 case ARM::VST3LNdAsm_32:
8669 case ARM::VST3LNqAsm_16:
8670 case ARM::VST3LNqAsm_32: {
8671 MCInst TmpInst;
8672 // Shuffle the operands around so the lane index operand is in the
8673 // right place.
8674 unsigned Spacing;
8675 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8676 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8677 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8678 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8679 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8680 Spacing));
8681 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8682 Spacing * 2));
8683 TmpInst.addOperand(Inst.getOperand(1)); // lane
8684 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8685 TmpInst.addOperand(Inst.getOperand(5));
8686 Inst = TmpInst;
8687 return true;
8690 case ARM::VST4LNdAsm_8:
8691 case ARM::VST4LNdAsm_16:
8692 case ARM::VST4LNdAsm_32:
8693 case ARM::VST4LNqAsm_16:
8694 case ARM::VST4LNqAsm_32: {
8695 MCInst TmpInst;
8696 // Shuffle the operands around so the lane index operand is in the
8697 // right place.
8698 unsigned Spacing;
8699 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8700 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8701 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8702 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8703 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8704 Spacing));
8705 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8706 Spacing * 2));
8707 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8708 Spacing * 3));
8709 TmpInst.addOperand(Inst.getOperand(1)); // lane
8710 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8711 TmpInst.addOperand(Inst.getOperand(5));
8712 Inst = TmpInst;
8713 return true;
8716 // Handle NEON VLD complex aliases.
8717 case ARM::VLD1LNdWB_register_Asm_8:
8718 case ARM::VLD1LNdWB_register_Asm_16:
8719 case ARM::VLD1LNdWB_register_Asm_32: {
8720 MCInst TmpInst;
8721 // Shuffle the operands around so the lane index operand is in the
8722 // right place.
8723 unsigned Spacing;
8724 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8725 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8726 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8727 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8728 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8729 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8730 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8731 TmpInst.addOperand(Inst.getOperand(1)); // lane
8732 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8733 TmpInst.addOperand(Inst.getOperand(6));
8734 Inst = TmpInst;
8735 return true;
8738 case ARM::VLD2LNdWB_register_Asm_8:
8739 case ARM::VLD2LNdWB_register_Asm_16:
8740 case ARM::VLD2LNdWB_register_Asm_32:
8741 case ARM::VLD2LNqWB_register_Asm_16:
8742 case ARM::VLD2LNqWB_register_Asm_32: {
8743 MCInst TmpInst;
8744 // Shuffle the operands around so the lane index operand is in the
8745 // right place.
8746 unsigned Spacing;
8747 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8748 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8749 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8750 Spacing));
8751 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8752 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8753 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8754 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8755 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8756 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8757 Spacing));
8758 TmpInst.addOperand(Inst.getOperand(1)); // lane
8759 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8760 TmpInst.addOperand(Inst.getOperand(6));
8761 Inst = TmpInst;
8762 return true;
8765 case ARM::VLD3LNdWB_register_Asm_8:
8766 case ARM::VLD3LNdWB_register_Asm_16:
8767 case ARM::VLD3LNdWB_register_Asm_32:
8768 case ARM::VLD3LNqWB_register_Asm_16:
8769 case ARM::VLD3LNqWB_register_Asm_32: {
8770 MCInst TmpInst;
8771 // Shuffle the operands around so the lane index operand is in the
8772 // right place.
8773 unsigned Spacing;
8774 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8775 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8776 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8777 Spacing));
8778 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8779 Spacing * 2));
8780 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8781 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8782 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8783 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8784 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8785 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8786 Spacing));
8787 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8788 Spacing * 2));
8789 TmpInst.addOperand(Inst.getOperand(1)); // lane
8790 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8791 TmpInst.addOperand(Inst.getOperand(6));
8792 Inst = TmpInst;
8793 return true;
8796 case ARM::VLD4LNdWB_register_Asm_8:
8797 case ARM::VLD4LNdWB_register_Asm_16:
8798 case ARM::VLD4LNdWB_register_Asm_32:
8799 case ARM::VLD4LNqWB_register_Asm_16:
8800 case ARM::VLD4LNqWB_register_Asm_32: {
8801 MCInst TmpInst;
8802 // Shuffle the operands around so the lane index operand is in the
8803 // right place.
8804 unsigned Spacing;
8805 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8806 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8807 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8808 Spacing));
8809 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8810 Spacing * 2));
8811 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8812 Spacing * 3));
8813 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8814 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8815 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8816 TmpInst.addOperand(Inst.getOperand(4)); // Rm
8817 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8818 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8819 Spacing));
8820 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8821 Spacing * 2));
8822 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8823 Spacing * 3));
8824 TmpInst.addOperand(Inst.getOperand(1)); // lane
8825 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
8826 TmpInst.addOperand(Inst.getOperand(6));
8827 Inst = TmpInst;
8828 return true;
8831 case ARM::VLD1LNdWB_fixed_Asm_8:
8832 case ARM::VLD1LNdWB_fixed_Asm_16:
8833 case ARM::VLD1LNdWB_fixed_Asm_32: {
8834 MCInst TmpInst;
8835 // Shuffle the operands around so the lane index operand is in the
8836 // right place.
8837 unsigned Spacing;
8838 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8839 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8840 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8841 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8842 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8843 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8844 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8845 TmpInst.addOperand(Inst.getOperand(1)); // lane
8846 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8847 TmpInst.addOperand(Inst.getOperand(5));
8848 Inst = TmpInst;
8849 return true;
8852 case ARM::VLD2LNdWB_fixed_Asm_8:
8853 case ARM::VLD2LNdWB_fixed_Asm_16:
8854 case ARM::VLD2LNdWB_fixed_Asm_32:
8855 case ARM::VLD2LNqWB_fixed_Asm_16:
8856 case ARM::VLD2LNqWB_fixed_Asm_32: {
8857 MCInst TmpInst;
8858 // Shuffle the operands around so the lane index operand is in the
8859 // right place.
8860 unsigned Spacing;
8861 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8862 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8863 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8864 Spacing));
8865 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8866 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8867 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8868 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8869 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8870 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8871 Spacing));
8872 TmpInst.addOperand(Inst.getOperand(1)); // lane
8873 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8874 TmpInst.addOperand(Inst.getOperand(5));
8875 Inst = TmpInst;
8876 return true;
8879 case ARM::VLD3LNdWB_fixed_Asm_8:
8880 case ARM::VLD3LNdWB_fixed_Asm_16:
8881 case ARM::VLD3LNdWB_fixed_Asm_32:
8882 case ARM::VLD3LNqWB_fixed_Asm_16:
8883 case ARM::VLD3LNqWB_fixed_Asm_32: {
8884 MCInst TmpInst;
8885 // Shuffle the operands around so the lane index operand is in the
8886 // right place.
8887 unsigned Spacing;
8888 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8889 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8890 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8891 Spacing));
8892 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8893 Spacing * 2));
8894 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8895 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8896 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8897 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8898 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8899 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8900 Spacing));
8901 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8902 Spacing * 2));
8903 TmpInst.addOperand(Inst.getOperand(1)); // lane
8904 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8905 TmpInst.addOperand(Inst.getOperand(5));
8906 Inst = TmpInst;
8907 return true;
8910 case ARM::VLD4LNdWB_fixed_Asm_8:
8911 case ARM::VLD4LNdWB_fixed_Asm_16:
8912 case ARM::VLD4LNdWB_fixed_Asm_32:
8913 case ARM::VLD4LNqWB_fixed_Asm_16:
8914 case ARM::VLD4LNqWB_fixed_Asm_32: {
8915 MCInst TmpInst;
8916 // Shuffle the operands around so the lane index operand is in the
8917 // right place.
8918 unsigned Spacing;
8919 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8920 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8921 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8922 Spacing));
8923 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8924 Spacing * 2));
8925 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8926 Spacing * 3));
8927 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
8928 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8929 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8930 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
8931 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8932 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8933 Spacing));
8934 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8935 Spacing * 2));
8936 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8937 Spacing * 3));
8938 TmpInst.addOperand(Inst.getOperand(1)); // lane
8939 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8940 TmpInst.addOperand(Inst.getOperand(5));
8941 Inst = TmpInst;
8942 return true;
8945 case ARM::VLD1LNdAsm_8:
8946 case ARM::VLD1LNdAsm_16:
8947 case ARM::VLD1LNdAsm_32: {
8948 MCInst TmpInst;
8949 // Shuffle the operands around so the lane index operand is in the
8950 // right place.
8951 unsigned Spacing;
8952 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8953 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8954 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8955 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8956 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8957 TmpInst.addOperand(Inst.getOperand(1)); // lane
8958 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8959 TmpInst.addOperand(Inst.getOperand(5));
8960 Inst = TmpInst;
8961 return true;
8964 case ARM::VLD2LNdAsm_8:
8965 case ARM::VLD2LNdAsm_16:
8966 case ARM::VLD2LNdAsm_32:
8967 case ARM::VLD2LNqAsm_16:
8968 case ARM::VLD2LNqAsm_32: {
8969 MCInst TmpInst;
8970 // Shuffle the operands around so the lane index operand is in the
8971 // right place.
8972 unsigned Spacing;
8973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8974 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8975 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8976 Spacing));
8977 TmpInst.addOperand(Inst.getOperand(2)); // Rn
8978 TmpInst.addOperand(Inst.getOperand(3)); // alignment
8979 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
8980 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8981 Spacing));
8982 TmpInst.addOperand(Inst.getOperand(1)); // lane
8983 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8984 TmpInst.addOperand(Inst.getOperand(5));
8985 Inst = TmpInst;
8986 return true;
8989 case ARM::VLD3LNdAsm_8:
8990 case ARM::VLD3LNdAsm_16:
8991 case ARM::VLD3LNdAsm_32:
8992 case ARM::VLD3LNqAsm_16:
8993 case ARM::VLD3LNqAsm_32: {
8994 MCInst TmpInst;
8995 // Shuffle the operands around so the lane index operand is in the
8996 // right place.
8997 unsigned Spacing;
8998 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8999 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9000 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9001 Spacing));
9002 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9003 Spacing * 2));
9004 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9005 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9006 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9007 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9008 Spacing));
9009 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9010 Spacing * 2));
9011 TmpInst.addOperand(Inst.getOperand(1)); // lane
9012 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9013 TmpInst.addOperand(Inst.getOperand(5));
9014 Inst = TmpInst;
9015 return true;
9018 case ARM::VLD4LNdAsm_8:
9019 case ARM::VLD4LNdAsm_16:
9020 case ARM::VLD4LNdAsm_32:
9021 case ARM::VLD4LNqAsm_16:
9022 case ARM::VLD4LNqAsm_32: {
9023 MCInst TmpInst;
9024 // Shuffle the operands around so the lane index operand is in the
9025 // right place.
9026 unsigned Spacing;
9027 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9028 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9029 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9030 Spacing));
9031 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9032 Spacing * 2));
9033 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9034 Spacing * 3));
9035 TmpInst.addOperand(Inst.getOperand(2)); // Rn
9036 TmpInst.addOperand(Inst.getOperand(3)); // alignment
9037 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
9038 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9039 Spacing));
9040 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9041 Spacing * 2));
9042 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9043 Spacing * 3));
9044 TmpInst.addOperand(Inst.getOperand(1)); // lane
9045 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9046 TmpInst.addOperand(Inst.getOperand(5));
9047 Inst = TmpInst;
9048 return true;
9051 // VLD3DUP single 3-element structure to all lanes instructions.
9052 case ARM::VLD3DUPdAsm_8:
9053 case ARM::VLD3DUPdAsm_16:
9054 case ARM::VLD3DUPdAsm_32:
9055 case ARM::VLD3DUPqAsm_8:
9056 case ARM::VLD3DUPqAsm_16:
9057 case ARM::VLD3DUPqAsm_32: {
9058 MCInst TmpInst;
9059 unsigned Spacing;
9060 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9061 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9062 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9063 Spacing));
9064 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9065 Spacing * 2));
9066 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9067 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9068 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9069 TmpInst.addOperand(Inst.getOperand(4));
9070 Inst = TmpInst;
9071 return true;
9074 case ARM::VLD3DUPdWB_fixed_Asm_8:
9075 case ARM::VLD3DUPdWB_fixed_Asm_16:
9076 case ARM::VLD3DUPdWB_fixed_Asm_32:
9077 case ARM::VLD3DUPqWB_fixed_Asm_8:
9078 case ARM::VLD3DUPqWB_fixed_Asm_16:
9079 case ARM::VLD3DUPqWB_fixed_Asm_32: {
9080 MCInst TmpInst;
9081 unsigned Spacing;
9082 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9083 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9084 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9085 Spacing));
9086 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9087 Spacing * 2));
9088 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9089 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9090 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9091 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9092 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9093 TmpInst.addOperand(Inst.getOperand(4));
9094 Inst = TmpInst;
9095 return true;
9098 case ARM::VLD3DUPdWB_register_Asm_8:
9099 case ARM::VLD3DUPdWB_register_Asm_16:
9100 case ARM::VLD3DUPdWB_register_Asm_32:
9101 case ARM::VLD3DUPqWB_register_Asm_8:
9102 case ARM::VLD3DUPqWB_register_Asm_16:
9103 case ARM::VLD3DUPqWB_register_Asm_32: {
9104 MCInst TmpInst;
9105 unsigned Spacing;
9106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9107 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9108 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9109 Spacing));
9110 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9111 Spacing * 2));
9112 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9113 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9114 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9115 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9116 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9117 TmpInst.addOperand(Inst.getOperand(5));
9118 Inst = TmpInst;
9119 return true;
9122 // VLD3 multiple 3-element structure instructions.
9123 case ARM::VLD3dAsm_8:
9124 case ARM::VLD3dAsm_16:
9125 case ARM::VLD3dAsm_32:
9126 case ARM::VLD3qAsm_8:
9127 case ARM::VLD3qAsm_16:
9128 case ARM::VLD3qAsm_32: {
9129 MCInst TmpInst;
9130 unsigned Spacing;
9131 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9132 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9133 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9134 Spacing));
9135 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9136 Spacing * 2));
9137 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9138 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9139 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9140 TmpInst.addOperand(Inst.getOperand(4));
9141 Inst = TmpInst;
9142 return true;
9145 case ARM::VLD3dWB_fixed_Asm_8:
9146 case ARM::VLD3dWB_fixed_Asm_16:
9147 case ARM::VLD3dWB_fixed_Asm_32:
9148 case ARM::VLD3qWB_fixed_Asm_8:
9149 case ARM::VLD3qWB_fixed_Asm_16:
9150 case ARM::VLD3qWB_fixed_Asm_32: {
9151 MCInst TmpInst;
9152 unsigned Spacing;
9153 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9154 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9155 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9156 Spacing));
9157 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9158 Spacing * 2));
9159 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9160 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9161 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9162 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9163 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9164 TmpInst.addOperand(Inst.getOperand(4));
9165 Inst = TmpInst;
9166 return true;
9169 case ARM::VLD3dWB_register_Asm_8:
9170 case ARM::VLD3dWB_register_Asm_16:
9171 case ARM::VLD3dWB_register_Asm_32:
9172 case ARM::VLD3qWB_register_Asm_8:
9173 case ARM::VLD3qWB_register_Asm_16:
9174 case ARM::VLD3qWB_register_Asm_32: {
9175 MCInst TmpInst;
9176 unsigned Spacing;
9177 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9178 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9179 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9180 Spacing));
9181 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9182 Spacing * 2));
9183 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9184 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9185 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9186 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9187 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9188 TmpInst.addOperand(Inst.getOperand(5));
9189 Inst = TmpInst;
9190 return true;
9193 // VLD4DUP single 3-element structure to all lanes instructions.
9194 case ARM::VLD4DUPdAsm_8:
9195 case ARM::VLD4DUPdAsm_16:
9196 case ARM::VLD4DUPdAsm_32:
9197 case ARM::VLD4DUPqAsm_8:
9198 case ARM::VLD4DUPqAsm_16:
9199 case ARM::VLD4DUPqAsm_32: {
9200 MCInst TmpInst;
9201 unsigned Spacing;
9202 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9203 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9204 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9205 Spacing));
9206 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9207 Spacing * 2));
9208 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9209 Spacing * 3));
9210 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9211 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9212 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9213 TmpInst.addOperand(Inst.getOperand(4));
9214 Inst = TmpInst;
9215 return true;
9218 case ARM::VLD4DUPdWB_fixed_Asm_8:
9219 case ARM::VLD4DUPdWB_fixed_Asm_16:
9220 case ARM::VLD4DUPdWB_fixed_Asm_32:
9221 case ARM::VLD4DUPqWB_fixed_Asm_8:
9222 case ARM::VLD4DUPqWB_fixed_Asm_16:
9223 case ARM::VLD4DUPqWB_fixed_Asm_32: {
9224 MCInst TmpInst;
9225 unsigned Spacing;
9226 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9227 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9228 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9229 Spacing));
9230 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9231 Spacing * 2));
9232 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9233 Spacing * 3));
9234 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9235 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9236 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9237 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9238 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9239 TmpInst.addOperand(Inst.getOperand(4));
9240 Inst = TmpInst;
9241 return true;
9244 case ARM::VLD4DUPdWB_register_Asm_8:
9245 case ARM::VLD4DUPdWB_register_Asm_16:
9246 case ARM::VLD4DUPdWB_register_Asm_32:
9247 case ARM::VLD4DUPqWB_register_Asm_8:
9248 case ARM::VLD4DUPqWB_register_Asm_16:
9249 case ARM::VLD4DUPqWB_register_Asm_32: {
9250 MCInst TmpInst;
9251 unsigned Spacing;
9252 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9253 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9254 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9255 Spacing));
9256 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9257 Spacing * 2));
9258 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9259 Spacing * 3));
9260 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9261 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9262 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9263 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9264 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9265 TmpInst.addOperand(Inst.getOperand(5));
9266 Inst = TmpInst;
9267 return true;
9270 // VLD4 multiple 4-element structure instructions.
9271 case ARM::VLD4dAsm_8:
9272 case ARM::VLD4dAsm_16:
9273 case ARM::VLD4dAsm_32:
9274 case ARM::VLD4qAsm_8:
9275 case ARM::VLD4qAsm_16:
9276 case ARM::VLD4qAsm_32: {
9277 MCInst TmpInst;
9278 unsigned Spacing;
9279 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9280 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9281 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9282 Spacing));
9283 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9284 Spacing * 2));
9285 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9286 Spacing * 3));
9287 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9288 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9289 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9290 TmpInst.addOperand(Inst.getOperand(4));
9291 Inst = TmpInst;
9292 return true;
9295 case ARM::VLD4dWB_fixed_Asm_8:
9296 case ARM::VLD4dWB_fixed_Asm_16:
9297 case ARM::VLD4dWB_fixed_Asm_32:
9298 case ARM::VLD4qWB_fixed_Asm_8:
9299 case ARM::VLD4qWB_fixed_Asm_16:
9300 case ARM::VLD4qWB_fixed_Asm_32: {
9301 MCInst TmpInst;
9302 unsigned Spacing;
9303 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9304 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9305 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9306 Spacing));
9307 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9308 Spacing * 2));
9309 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9310 Spacing * 3));
9311 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9312 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9313 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9314 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9315 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9316 TmpInst.addOperand(Inst.getOperand(4));
9317 Inst = TmpInst;
9318 return true;
9321 case ARM::VLD4dWB_register_Asm_8:
9322 case ARM::VLD4dWB_register_Asm_16:
9323 case ARM::VLD4dWB_register_Asm_32:
9324 case ARM::VLD4qWB_register_Asm_8:
9325 case ARM::VLD4qWB_register_Asm_16:
9326 case ARM::VLD4qWB_register_Asm_32: {
9327 MCInst TmpInst;
9328 unsigned Spacing;
9329 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9330 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9331 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9332 Spacing));
9333 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9334 Spacing * 2));
9335 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9336 Spacing * 3));
9337 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9338 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9339 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9340 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9341 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9342 TmpInst.addOperand(Inst.getOperand(5));
9343 Inst = TmpInst;
9344 return true;
9347 // VST3 multiple 3-element structure instructions.
9348 case ARM::VST3dAsm_8:
9349 case ARM::VST3dAsm_16:
9350 case ARM::VST3dAsm_32:
9351 case ARM::VST3qAsm_8:
9352 case ARM::VST3qAsm_16:
9353 case ARM::VST3qAsm_32: {
9354 MCInst TmpInst;
9355 unsigned Spacing;
9356 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9357 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9358 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9359 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9360 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9361 Spacing));
9362 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9363 Spacing * 2));
9364 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9365 TmpInst.addOperand(Inst.getOperand(4));
9366 Inst = TmpInst;
9367 return true;
9370 case ARM::VST3dWB_fixed_Asm_8:
9371 case ARM::VST3dWB_fixed_Asm_16:
9372 case ARM::VST3dWB_fixed_Asm_32:
9373 case ARM::VST3qWB_fixed_Asm_8:
9374 case ARM::VST3qWB_fixed_Asm_16:
9375 case ARM::VST3qWB_fixed_Asm_32: {
9376 MCInst TmpInst;
9377 unsigned Spacing;
9378 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9379 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9380 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9381 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9382 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9383 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9384 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9385 Spacing));
9386 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9387 Spacing * 2));
9388 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9389 TmpInst.addOperand(Inst.getOperand(4));
9390 Inst = TmpInst;
9391 return true;
9394 case ARM::VST3dWB_register_Asm_8:
9395 case ARM::VST3dWB_register_Asm_16:
9396 case ARM::VST3dWB_register_Asm_32:
9397 case ARM::VST3qWB_register_Asm_8:
9398 case ARM::VST3qWB_register_Asm_16:
9399 case ARM::VST3qWB_register_Asm_32: {
9400 MCInst TmpInst;
9401 unsigned Spacing;
9402 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9403 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9404 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9405 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9406 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9407 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9408 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9409 Spacing));
9410 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9411 Spacing * 2));
9412 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9413 TmpInst.addOperand(Inst.getOperand(5));
9414 Inst = TmpInst;
9415 return true;
9418 // VST4 multiple 3-element structure instructions.
9419 case ARM::VST4dAsm_8:
9420 case ARM::VST4dAsm_16:
9421 case ARM::VST4dAsm_32:
9422 case ARM::VST4qAsm_8:
9423 case ARM::VST4qAsm_16:
9424 case ARM::VST4qAsm_32: {
9425 MCInst TmpInst;
9426 unsigned Spacing;
9427 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9428 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9429 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9430 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9431 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9432 Spacing));
9433 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9434 Spacing * 2));
9435 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9436 Spacing * 3));
9437 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9438 TmpInst.addOperand(Inst.getOperand(4));
9439 Inst = TmpInst;
9440 return true;
9443 case ARM::VST4dWB_fixed_Asm_8:
9444 case ARM::VST4dWB_fixed_Asm_16:
9445 case ARM::VST4dWB_fixed_Asm_32:
9446 case ARM::VST4qWB_fixed_Asm_8:
9447 case ARM::VST4qWB_fixed_Asm_16:
9448 case ARM::VST4qWB_fixed_Asm_32: {
9449 MCInst TmpInst;
9450 unsigned Spacing;
9451 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9452 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9453 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9454 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9455 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
9456 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9457 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9458 Spacing));
9459 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9460 Spacing * 2));
9461 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9462 Spacing * 3));
9463 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9464 TmpInst.addOperand(Inst.getOperand(4));
9465 Inst = TmpInst;
9466 return true;
9469 case ARM::VST4dWB_register_Asm_8:
9470 case ARM::VST4dWB_register_Asm_16:
9471 case ARM::VST4dWB_register_Asm_32:
9472 case ARM::VST4qWB_register_Asm_8:
9473 case ARM::VST4qWB_register_Asm_16:
9474 case ARM::VST4qWB_register_Asm_32: {
9475 MCInst TmpInst;
9476 unsigned Spacing;
9477 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9478 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9479 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
9480 TmpInst.addOperand(Inst.getOperand(2)); // alignment
9481 TmpInst.addOperand(Inst.getOperand(3)); // Rm
9482 TmpInst.addOperand(Inst.getOperand(0)); // Vd
9483 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9484 Spacing));
9485 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9486 Spacing * 2));
9487 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
9488 Spacing * 3));
9489 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9490 TmpInst.addOperand(Inst.getOperand(5));
9491 Inst = TmpInst;
9492 return true;
9495 // Handle encoding choice for the shift-immediate instructions.
9496 case ARM::t2LSLri:
9497 case ARM::t2LSRri:
9498 case ARM::t2ASRri:
9499 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9500 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9501 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9502 !HasWideQualifier) {
9503 unsigned NewOpc;
9504 switch (Inst.getOpcode()) {
9505 default: llvm_unreachable("unexpected opcode");
9506 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
9507 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
9508 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
9510 // The Thumb1 operands aren't in the same order. Awesome, eh?
9511 MCInst TmpInst;
9512 TmpInst.setOpcode(NewOpc);
9513 TmpInst.addOperand(Inst.getOperand(0));
9514 TmpInst.addOperand(Inst.getOperand(5));
9515 TmpInst.addOperand(Inst.getOperand(1));
9516 TmpInst.addOperand(Inst.getOperand(2));
9517 TmpInst.addOperand(Inst.getOperand(3));
9518 TmpInst.addOperand(Inst.getOperand(4));
9519 Inst = TmpInst;
9520 return true;
9522 return false;
9524 // Handle the Thumb2 mode MOV complex aliases.
9525 case ARM::t2MOVsr:
9526 case ARM::t2MOVSsr: {
9527 // Which instruction to expand to depends on the CCOut operand and
9528 // whether we're in an IT block if the register operands are low
9529 // registers.
9530 bool isNarrow = false;
9531 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9532 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9533 isARMLowRegister(Inst.getOperand(2).getReg()) &&
9534 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
9535 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
9536 !HasWideQualifier)
9537 isNarrow = true;
9538 MCInst TmpInst;
9539 unsigned newOpc;
9540 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
9541 default: llvm_unreachable("unexpected opcode!");
9542 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
9543 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
9544 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
9545 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
9547 TmpInst.setOpcode(newOpc);
9548 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9549 if (isNarrow)
9550 TmpInst.addOperand(MCOperand::createReg(
9551 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9552 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9553 TmpInst.addOperand(Inst.getOperand(2)); // Rm
9554 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
9555 TmpInst.addOperand(Inst.getOperand(5));
9556 if (!isNarrow)
9557 TmpInst.addOperand(MCOperand::createReg(
9558 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9559 Inst = TmpInst;
9560 return true;
9562 case ARM::t2MOVsi:
9563 case ARM::t2MOVSsi: {
9564 // Which instruction to expand to depends on the CCOut operand and
9565 // whether we're in an IT block if the register operands are low
9566 // registers.
9567 bool isNarrow = false;
9568 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9569 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9570 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
9571 !HasWideQualifier)
9572 isNarrow = true;
9573 MCInst TmpInst;
9574 unsigned newOpc;
9575 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
9576 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
9577 bool isMov = false;
9578 // MOV rd, rm, LSL #0 is actually a MOV instruction
9579 if (Shift == ARM_AM::lsl && Amount == 0) {
9580 isMov = true;
9581 // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
9582 // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
9583 // unpredictable in an IT block so the 32-bit encoding T3 has to be used
9584 // instead.
9585 if (inITBlock()) {
9586 isNarrow = false;
9588 newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
9589 } else {
9590 switch(Shift) {
9591 default: llvm_unreachable("unexpected opcode!");
9592 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
9593 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
9594 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
9595 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
9596 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
9599 if (Amount == 32) Amount = 0;
9600 TmpInst.setOpcode(newOpc);
9601 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9602 if (isNarrow && !isMov)
9603 TmpInst.addOperand(MCOperand::createReg(
9604 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9605 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9606 if (newOpc != ARM::t2RRX && !isMov)
9607 TmpInst.addOperand(MCOperand::createImm(Amount));
9608 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9609 TmpInst.addOperand(Inst.getOperand(4));
9610 if (!isNarrow)
9611 TmpInst.addOperand(MCOperand::createReg(
9612 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9613 Inst = TmpInst;
9614 return true;
9616 // Handle the ARM mode MOV complex aliases.
9617 case ARM::ASRr:
9618 case ARM::LSRr:
9619 case ARM::LSLr:
9620 case ARM::RORr: {
9621 ARM_AM::ShiftOpc ShiftTy;
9622 switch(Inst.getOpcode()) {
9623 default: llvm_unreachable("unexpected opcode!");
9624 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
9625 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
9626 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
9627 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
9629 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
9630 MCInst TmpInst;
9631 TmpInst.setOpcode(ARM::MOVsr);
9632 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9633 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9634 TmpInst.addOperand(Inst.getOperand(2)); // Rm
9635 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9636 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9637 TmpInst.addOperand(Inst.getOperand(4));
9638 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
9639 Inst = TmpInst;
9640 return true;
9642 case ARM::ASRi:
9643 case ARM::LSRi:
9644 case ARM::LSLi:
9645 case ARM::RORi: {
9646 ARM_AM::ShiftOpc ShiftTy;
9647 switch(Inst.getOpcode()) {
9648 default: llvm_unreachable("unexpected opcode!");
9649 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
9650 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
9651 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
9652 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
9654 // A shift by zero is a plain MOVr, not a MOVsi.
9655 unsigned Amt = Inst.getOperand(2).getImm();
9656 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
9657 // A shift by 32 should be encoded as 0 when permitted
9658 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
9659 Amt = 0;
9660 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
9661 MCInst TmpInst;
9662 TmpInst.setOpcode(Opc);
9663 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9664 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9665 if (Opc == ARM::MOVsi)
9666 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9667 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
9668 TmpInst.addOperand(Inst.getOperand(4));
9669 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
9670 Inst = TmpInst;
9671 return true;
9673 case ARM::RRXi: {
9674 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
9675 MCInst TmpInst;
9676 TmpInst.setOpcode(ARM::MOVsi);
9677 TmpInst.addOperand(Inst.getOperand(0)); // Rd
9678 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9679 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
9680 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9681 TmpInst.addOperand(Inst.getOperand(3));
9682 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
9683 Inst = TmpInst;
9684 return true;
9686 case ARM::t2LDMIA_UPD: {
9687 // If this is a load of a single register, then we should use
9688 // a post-indexed LDR instruction instead, per the ARM ARM.
9689 if (Inst.getNumOperands() != 5)
9690 return false;
9691 MCInst TmpInst;
9692 TmpInst.setOpcode(ARM::t2LDR_POST);
9693 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9694 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9695 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9696 TmpInst.addOperand(MCOperand::createImm(4));
9697 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9698 TmpInst.addOperand(Inst.getOperand(3));
9699 Inst = TmpInst;
9700 return true;
9702 case ARM::t2STMDB_UPD: {
9703 // If this is a store of a single register, then we should use
9704 // a pre-indexed STR instruction instead, per the ARM ARM.
9705 if (Inst.getNumOperands() != 5)
9706 return false;
9707 MCInst TmpInst;
9708 TmpInst.setOpcode(ARM::t2STR_PRE);
9709 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9710 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9711 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9712 TmpInst.addOperand(MCOperand::createImm(-4));
9713 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9714 TmpInst.addOperand(Inst.getOperand(3));
9715 Inst = TmpInst;
9716 return true;
9718 case ARM::LDMIA_UPD:
9719 // If this is a load of a single register via a 'pop', then we should use
9720 // a post-indexed LDR instruction instead, per the ARM ARM.
9721 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
9722 Inst.getNumOperands() == 5) {
9723 MCInst TmpInst;
9724 TmpInst.setOpcode(ARM::LDR_POST_IMM);
9725 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9726 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9727 TmpInst.addOperand(Inst.getOperand(1)); // Rn
9728 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
9729 TmpInst.addOperand(MCOperand::createImm(4));
9730 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9731 TmpInst.addOperand(Inst.getOperand(3));
9732 Inst = TmpInst;
9733 return true;
9735 break;
9736 case ARM::STMDB_UPD:
9737 // If this is a store of a single register via a 'push', then we should use
9738 // a pre-indexed STR instruction instead, per the ARM ARM.
9739 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
9740 Inst.getNumOperands() == 5) {
9741 MCInst TmpInst;
9742 TmpInst.setOpcode(ARM::STR_PRE_IMM);
9743 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
9744 TmpInst.addOperand(Inst.getOperand(4)); // Rt
9745 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
9746 TmpInst.addOperand(MCOperand::createImm(-4));
9747 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
9748 TmpInst.addOperand(Inst.getOperand(3));
9749 Inst = TmpInst;
9751 break;
9752 case ARM::t2ADDri12:
9753 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
9754 // mnemonic was used (not "addw"), encoding T3 is preferred.
9755 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
9756 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
9757 break;
9758 Inst.setOpcode(ARM::t2ADDri);
9759 Inst.addOperand(MCOperand::createReg(0)); // cc_out
9760 break;
9761 case ARM::t2SUBri12:
9762 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
9763 // mnemonic was used (not "subw"), encoding T3 is preferred.
9764 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
9765 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
9766 break;
9767 Inst.setOpcode(ARM::t2SUBri);
9768 Inst.addOperand(MCOperand::createReg(0)); // cc_out
9769 break;
9770 case ARM::tADDi8:
9771 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
9772 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
9773 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
9774 // to encoding T1 if <Rd> is omitted."
9775 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
9776 Inst.setOpcode(ARM::tADDi3);
9777 return true;
9779 break;
9780 case ARM::tSUBi8:
9781 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
9782 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
9783 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
9784 // to encoding T1 if <Rd> is omitted."
9785 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
9786 Inst.setOpcode(ARM::tSUBi3);
9787 return true;
9789 break;
9790 case ARM::t2ADDri:
9791 case ARM::t2SUBri: {
9792 // If the destination and first source operand are the same, and
9793 // the flags are compatible with the current IT status, use encoding T2
9794 // instead of T3. For compatibility with the system 'as'. Make sure the
9795 // wide encoding wasn't explicit.
9796 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
9797 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
9798 (Inst.getOperand(2).isImm() &&
9799 (unsigned)Inst.getOperand(2).getImm() > 255) ||
9800 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
9801 HasWideQualifier)
9802 break;
9803 MCInst TmpInst;
9804 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
9805 ARM::tADDi8 : ARM::tSUBi8);
9806 TmpInst.addOperand(Inst.getOperand(0));
9807 TmpInst.addOperand(Inst.getOperand(5));
9808 TmpInst.addOperand(Inst.getOperand(0));
9809 TmpInst.addOperand(Inst.getOperand(2));
9810 TmpInst.addOperand(Inst.getOperand(3));
9811 TmpInst.addOperand(Inst.getOperand(4));
9812 Inst = TmpInst;
9813 return true;
9815 case ARM::t2ADDrr: {
9816 // If the destination and first source operand are the same, and
9817 // there's no setting of the flags, use encoding T2 instead of T3.
9818 // Note that this is only for ADD, not SUB. This mirrors the system
9819 // 'as' behaviour. Also take advantage of ADD being commutative.
9820 // Make sure the wide encoding wasn't explicit.
9821 bool Swap = false;
9822 auto DestReg = Inst.getOperand(0).getReg();
9823 bool Transform = DestReg == Inst.getOperand(1).getReg();
9824 if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
9825 Transform = true;
9826 Swap = true;
9828 if (!Transform ||
9829 Inst.getOperand(5).getReg() != 0 ||
9830 HasWideQualifier)
9831 break;
9832 MCInst TmpInst;
9833 TmpInst.setOpcode(ARM::tADDhirr);
9834 TmpInst.addOperand(Inst.getOperand(0));
9835 TmpInst.addOperand(Inst.getOperand(0));
9836 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
9837 TmpInst.addOperand(Inst.getOperand(3));
9838 TmpInst.addOperand(Inst.getOperand(4));
9839 Inst = TmpInst;
9840 return true;
9842 case ARM::tADDrSP:
9843 // If the non-SP source operand and the destination operand are not the
9844 // same, we need to use the 32-bit encoding if it's available.
9845 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
9846 Inst.setOpcode(ARM::t2ADDrr);
9847 Inst.addOperand(MCOperand::createReg(0)); // cc_out
9848 return true;
9850 break;
9851 case ARM::tB:
9852 // A Thumb conditional branch outside of an IT block is a tBcc.
9853 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
9854 Inst.setOpcode(ARM::tBcc);
9855 return true;
9857 break;
9858 case ARM::t2B:
9859 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
9860 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
9861 Inst.setOpcode(ARM::t2Bcc);
9862 return true;
9864 break;
9865 case ARM::t2Bcc:
9866 // If the conditional is AL or we're in an IT block, we really want t2B.
9867 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
9868 Inst.setOpcode(ARM::t2B);
9869 return true;
9871 break;
9872 case ARM::tBcc:
9873 // If the conditional is AL, we really want tB.
9874 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
9875 Inst.setOpcode(ARM::tB);
9876 return true;
9878 break;
9879 case ARM::tLDMIA: {
9880 // If the register list contains any high registers, or if the writeback
9881 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
9882 // instead if we're in Thumb2. Otherwise, this should have generated
9883 // an error in validateInstruction().
9884 unsigned Rn = Inst.getOperand(0).getReg();
9885 bool hasWritebackToken =
9886 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
9887 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
9888 bool listContainsBase;
9889 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
9890 (!listContainsBase && !hasWritebackToken) ||
9891 (listContainsBase && hasWritebackToken)) {
9892 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
9893 assert(isThumbTwo());
9894 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
9895 // If we're switching to the updating version, we need to insert
9896 // the writeback tied operand.
9897 if (hasWritebackToken)
9898 Inst.insert(Inst.begin(),
9899 MCOperand::createReg(Inst.getOperand(0).getReg()));
9900 return true;
9902 break;
9904 case ARM::tSTMIA_UPD: {
9905 // If the register list contains any high registers, we need to use
9906 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
9907 // should have generated an error in validateInstruction().
9908 unsigned Rn = Inst.getOperand(0).getReg();
9909 bool listContainsBase;
9910 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
9911 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
9912 assert(isThumbTwo());
9913 Inst.setOpcode(ARM::t2STMIA_UPD);
9914 return true;
9916 break;
9918 case ARM::tPOP: {
9919 bool listContainsBase;
9920 // If the register list contains any high registers, we need to use
9921 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
9922 // should have generated an error in validateInstruction().
9923 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
9924 return false;
9925 assert(isThumbTwo());
9926 Inst.setOpcode(ARM::t2LDMIA_UPD);
9927 // Add the base register and writeback operands.
9928 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9929 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9930 return true;
9932 case ARM::tPUSH: {
9933 bool listContainsBase;
9934 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
9935 return false;
9936 assert(isThumbTwo());
9937 Inst.setOpcode(ARM::t2STMDB_UPD);
9938 // Add the base register and writeback operands.
9939 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9940 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9941 return true;
9943 case ARM::t2MOVi:
9944 // If we can use the 16-bit encoding and the user didn't explicitly
9945 // request the 32-bit variant, transform it here.
9946 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9947 (Inst.getOperand(1).isImm() &&
9948 (unsigned)Inst.getOperand(1).getImm() <= 255) &&
9949 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
9950 !HasWideQualifier) {
9951 // The operands aren't in the same order for tMOVi8...
9952 MCInst TmpInst;
9953 TmpInst.setOpcode(ARM::tMOVi8);
9954 TmpInst.addOperand(Inst.getOperand(0));
9955 TmpInst.addOperand(Inst.getOperand(4));
9956 TmpInst.addOperand(Inst.getOperand(1));
9957 TmpInst.addOperand(Inst.getOperand(2));
9958 TmpInst.addOperand(Inst.getOperand(3));
9959 Inst = TmpInst;
9960 return true;
9962 break;
9964 case ARM::t2MOVr:
9965 // If we can use the 16-bit encoding and the user didn't explicitly
9966 // request the 32-bit variant, transform it here.
9967 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9968 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9969 Inst.getOperand(2).getImm() == ARMCC::AL &&
9970 Inst.getOperand(4).getReg() == ARM::CPSR &&
9971 !HasWideQualifier) {
9972 // The operands aren't the same for tMOV[S]r... (no cc_out)
9973 MCInst TmpInst;
9974 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
9975 TmpInst.addOperand(Inst.getOperand(0));
9976 TmpInst.addOperand(Inst.getOperand(1));
9977 TmpInst.addOperand(Inst.getOperand(2));
9978 TmpInst.addOperand(Inst.getOperand(3));
9979 Inst = TmpInst;
9980 return true;
9982 break;
9984 case ARM::t2SXTH:
9985 case ARM::t2SXTB:
9986 case ARM::t2UXTH:
9987 case ARM::t2UXTB:
9988 // If we can use the 16-bit encoding and the user didn't explicitly
9989 // request the 32-bit variant, transform it here.
9990 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
9991 isARMLowRegister(Inst.getOperand(1).getReg()) &&
9992 Inst.getOperand(2).getImm() == 0 &&
9993 !HasWideQualifier) {
9994 unsigned NewOpc;
9995 switch (Inst.getOpcode()) {
9996 default: llvm_unreachable("Illegal opcode!");
9997 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
9998 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
9999 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
10000 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
10002 // The operands aren't the same for thumb1 (no rotate operand).
10003 MCInst TmpInst;
10004 TmpInst.setOpcode(NewOpc);
10005 TmpInst.addOperand(Inst.getOperand(0));
10006 TmpInst.addOperand(Inst.getOperand(1));
10007 TmpInst.addOperand(Inst.getOperand(3));
10008 TmpInst.addOperand(Inst.getOperand(4));
10009 Inst = TmpInst;
10010 return true;
10012 break;
10014 case ARM::MOVsi: {
10015 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10016 // rrx shifts and asr/lsr of #32 is encoded as 0
10017 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
10018 return false;
10019 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10020 // Shifting by zero is accepted as a vanilla 'MOVr'
10021 MCInst TmpInst;
10022 TmpInst.setOpcode(ARM::MOVr);
10023 TmpInst.addOperand(Inst.getOperand(0));
10024 TmpInst.addOperand(Inst.getOperand(1));
10025 TmpInst.addOperand(Inst.getOperand(3));
10026 TmpInst.addOperand(Inst.getOperand(4));
10027 TmpInst.addOperand(Inst.getOperand(5));
10028 Inst = TmpInst;
10029 return true;
10031 return false;
10033 case ARM::ANDrsi:
10034 case ARM::ORRrsi:
10035 case ARM::EORrsi:
10036 case ARM::BICrsi:
10037 case ARM::SUBrsi:
10038 case ARM::ADDrsi: {
10039 unsigned newOpc;
10040 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
10041 if (SOpc == ARM_AM::rrx) return false;
10042 switch (Inst.getOpcode()) {
10043 default: llvm_unreachable("unexpected opcode!");
10044 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
10045 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
10046 case ARM::EORrsi: newOpc = ARM::EORrr; break;
10047 case ARM::BICrsi: newOpc = ARM::BICrr; break;
10048 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
10049 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
10051 // If the shift is by zero, use the non-shifted instruction definition.
10052 // The exception is for right shifts, where 0 == 32
10053 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
10054 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
10055 MCInst TmpInst;
10056 TmpInst.setOpcode(newOpc);
10057 TmpInst.addOperand(Inst.getOperand(0));
10058 TmpInst.addOperand(Inst.getOperand(1));
10059 TmpInst.addOperand(Inst.getOperand(2));
10060 TmpInst.addOperand(Inst.getOperand(4));
10061 TmpInst.addOperand(Inst.getOperand(5));
10062 TmpInst.addOperand(Inst.getOperand(6));
10063 Inst = TmpInst;
10064 return true;
10066 return false;
10068 case ARM::ITasm:
10069 case ARM::t2IT: {
10070 // Set up the IT block state according to the IT instruction we just
10071 // matched.
10072 assert(!inITBlock() && "nested IT blocks?!");
10073 startExplicitITBlock(ARMCC::CondCodes(Inst.getOperand(0).getImm()),
10074 Inst.getOperand(1).getImm());
10075 break;
10077 case ARM::t2LSLrr:
10078 case ARM::t2LSRrr:
10079 case ARM::t2ASRrr:
10080 case ARM::t2SBCrr:
10081 case ARM::t2RORrr:
10082 case ARM::t2BICrr:
10083 // Assemblers should use the narrow encodings of these instructions when permissible.
10084 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10085 isARMLowRegister(Inst.getOperand(2).getReg())) &&
10086 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
10087 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10088 !HasWideQualifier) {
10089 unsigned NewOpc;
10090 switch (Inst.getOpcode()) {
10091 default: llvm_unreachable("unexpected opcode");
10092 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
10093 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
10094 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
10095 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
10096 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
10097 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
10099 MCInst TmpInst;
10100 TmpInst.setOpcode(NewOpc);
10101 TmpInst.addOperand(Inst.getOperand(0));
10102 TmpInst.addOperand(Inst.getOperand(5));
10103 TmpInst.addOperand(Inst.getOperand(1));
10104 TmpInst.addOperand(Inst.getOperand(2));
10105 TmpInst.addOperand(Inst.getOperand(3));
10106 TmpInst.addOperand(Inst.getOperand(4));
10107 Inst = TmpInst;
10108 return true;
10110 return false;
10112 case ARM::t2ANDrr:
10113 case ARM::t2EORrr:
10114 case ARM::t2ADCrr:
10115 case ARM::t2ORRrr:
10116 // Assemblers should use the narrow encodings of these instructions when permissible.
10117 // These instructions are special in that they are commutable, so shorter encodings
10118 // are available more often.
10119 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
10120 isARMLowRegister(Inst.getOperand(2).getReg())) &&
10121 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
10122 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
10123 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
10124 !HasWideQualifier) {
10125 unsigned NewOpc;
10126 switch (Inst.getOpcode()) {
10127 default: llvm_unreachable("unexpected opcode");
10128 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
10129 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
10130 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
10131 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
10133 MCInst TmpInst;
10134 TmpInst.setOpcode(NewOpc);
10135 TmpInst.addOperand(Inst.getOperand(0));
10136 TmpInst.addOperand(Inst.getOperand(5));
10137 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
10138 TmpInst.addOperand(Inst.getOperand(1));
10139 TmpInst.addOperand(Inst.getOperand(2));
10140 } else {
10141 TmpInst.addOperand(Inst.getOperand(2));
10142 TmpInst.addOperand(Inst.getOperand(1));
10144 TmpInst.addOperand(Inst.getOperand(3));
10145 TmpInst.addOperand(Inst.getOperand(4));
10146 Inst = TmpInst;
10147 return true;
10149 return false;
10150 case ARM::MVE_VPST:
10151 case ARM::MVE_VPTv16i8:
10152 case ARM::MVE_VPTv8i16:
10153 case ARM::MVE_VPTv4i32:
10154 case ARM::MVE_VPTv16u8:
10155 case ARM::MVE_VPTv8u16:
10156 case ARM::MVE_VPTv4u32:
10157 case ARM::MVE_VPTv16s8:
10158 case ARM::MVE_VPTv8s16:
10159 case ARM::MVE_VPTv4s32:
10160 case ARM::MVE_VPTv4f32:
10161 case ARM::MVE_VPTv8f16:
10162 case ARM::MVE_VPTv16i8r:
10163 case ARM::MVE_VPTv8i16r:
10164 case ARM::MVE_VPTv4i32r:
10165 case ARM::MVE_VPTv16u8r:
10166 case ARM::MVE_VPTv8u16r:
10167 case ARM::MVE_VPTv4u32r:
10168 case ARM::MVE_VPTv16s8r:
10169 case ARM::MVE_VPTv8s16r:
10170 case ARM::MVE_VPTv4s32r:
10171 case ARM::MVE_VPTv4f32r:
10172 case ARM::MVE_VPTv8f16r: {
10173 assert(!inVPTBlock() && "Nested VPT blocks are not allowed");
10174 MCOperand &MO = Inst.getOperand(0);
10175 VPTState.Mask = MO.getImm();
10176 VPTState.CurPosition = 0;
10177 break;
10180 return false;
10183 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
10184 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
10185 // suffix depending on whether they're in an IT block or not.
10186 unsigned Opc = Inst.getOpcode();
10187 const MCInstrDesc &MCID = MII.get(Opc);
10188 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
10189 assert(MCID.hasOptionalDef() &&
10190 "optionally flag setting instruction missing optional def operand");
10191 assert(MCID.NumOperands == Inst.getNumOperands() &&
10192 "operand count mismatch!");
10193 // Find the optional-def operand (cc_out).
10194 unsigned OpNo;
10195 for (OpNo = 0;
10196 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
10197 ++OpNo)
10199 // If we're parsing Thumb1, reject it completely.
10200 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
10201 return Match_RequiresFlagSetting;
10202 // If we're parsing Thumb2, which form is legal depends on whether we're
10203 // in an IT block.
10204 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
10205 !inITBlock())
10206 return Match_RequiresITBlock;
10207 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
10208 inITBlock())
10209 return Match_RequiresNotITBlock;
10210 // LSL with zero immediate is not allowed in an IT block
10211 if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
10212 return Match_RequiresNotITBlock;
10213 } else if (isThumbOne()) {
10214 // Some high-register supporting Thumb1 encodings only allow both registers
10215 // to be from r0-r7 when in Thumb2.
10216 if (Opc == ARM::tADDhirr && !hasV6MOps() &&
10217 isARMLowRegister(Inst.getOperand(1).getReg()) &&
10218 isARMLowRegister(Inst.getOperand(2).getReg()))
10219 return Match_RequiresThumb2;
10220 // Others only require ARMv6 or later.
10221 else if (Opc == ARM::tMOVr && !hasV6Ops() &&
10222 isARMLowRegister(Inst.getOperand(0).getReg()) &&
10223 isARMLowRegister(Inst.getOperand(1).getReg()))
10224 return Match_RequiresV6;
10227 // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
10228 // than the loop below can handle, so it uses the GPRnopc register class and
10229 // we do SP handling here.
10230 if (Opc == ARM::t2MOVr && !hasV8Ops())
10232 // SP as both source and destination is not allowed
10233 if (Inst.getOperand(0).getReg() == ARM::SP &&
10234 Inst.getOperand(1).getReg() == ARM::SP)
10235 return Match_RequiresV8;
10236 // When flags-setting SP as either source or destination is not allowed
10237 if (Inst.getOperand(4).getReg() == ARM::CPSR &&
10238 (Inst.getOperand(0).getReg() == ARM::SP ||
10239 Inst.getOperand(1).getReg() == ARM::SP))
10240 return Match_RequiresV8;
10243 switch (Inst.getOpcode()) {
10244 case ARM::VMRS:
10245 case ARM::VMSR:
10246 case ARM::VMRS_FPCXTS:
10247 case ARM::VMRS_FPCXTNS:
10248 case ARM::VMSR_FPCXTS:
10249 case ARM::VMSR_FPCXTNS:
10250 case ARM::VMRS_FPSCR_NZCVQC:
10251 case ARM::VMSR_FPSCR_NZCVQC:
10252 case ARM::FMSTAT:
10253 case ARM::VMRS_VPR:
10254 case ARM::VMRS_P0:
10255 case ARM::VMSR_VPR:
10256 case ARM::VMSR_P0:
10257 // Use of SP for VMRS/VMSR is only allowed in ARM mode with the exception of
10258 // ARMv8-A.
10259 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
10260 (isThumb() && !hasV8Ops()))
10261 return Match_InvalidOperand;
10262 break;
10263 default:
10264 break;
10267 for (unsigned I = 0; I < MCID.NumOperands; ++I)
10268 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
10269 // rGPRRegClass excludes PC, and also excluded SP before ARMv8
10270 const auto &Op = Inst.getOperand(I);
10271 if (!Op.isReg()) {
10272 // This can happen in awkward cases with tied operands, e.g. a
10273 // writeback load/store with a complex addressing mode in
10274 // which there's an output operand corresponding to the
10275 // updated written-back base register: the Tablegen-generated
10276 // AsmMatcher will have written a placeholder operand to that
10277 // slot in the form of an immediate 0, because it can't
10278 // generate the register part of the complex addressing-mode
10279 // operand ahead of time.
10280 continue;
10283 unsigned Reg = Op.getReg();
10284 if ((Reg == ARM::SP) && !hasV8Ops())
10285 return Match_RequiresV8;
10286 else if (Reg == ARM::PC)
10287 return Match_InvalidOperand;
10290 return Match_Success;
10293 namespace llvm {
10295 template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
10296 return true; // In an assembly source, no need to second-guess
10299 } // end namespace llvm
10301 // Returns true if Inst is unpredictable if it is in and IT block, but is not
10302 // the last instruction in the block.
10303 bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
10304 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10306 // All branch & call instructions terminate IT blocks with the exception of
10307 // SVC.
10308 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
10309 MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
10310 return true;
10312 // Any arithmetic instruction which writes to the PC also terminates the IT
10313 // block.
10314 if (MCID.hasDefOfPhysReg(Inst, ARM::PC, *MRI))
10315 return true;
10317 return false;
10320 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
10321 SmallVectorImpl<NearMissInfo> &NearMisses,
10322 bool MatchingInlineAsm,
10323 bool &EmitInITBlock,
10324 MCStreamer &Out) {
10325 // If we can't use an implicit IT block here, just match as normal.
10326 if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
10327 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10329 // Try to match the instruction in an extension of the current IT block (if
10330 // there is one).
10331 if (inImplicitITBlock()) {
10332 extendImplicitITBlock(ITState.Cond);
10333 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10334 Match_Success) {
10335 // The match succeded, but we still have to check that the instruction is
10336 // valid in this implicit IT block.
10337 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10338 if (MCID.isPredicable()) {
10339 ARMCC::CondCodes InstCond =
10340 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10341 .getImm();
10342 ARMCC::CondCodes ITCond = currentITCond();
10343 if (InstCond == ITCond) {
10344 EmitInITBlock = true;
10345 return Match_Success;
10346 } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
10347 invertCurrentITCondition();
10348 EmitInITBlock = true;
10349 return Match_Success;
10353 rewindImplicitITPosition();
10356 // Finish the current IT block, and try to match outside any IT block.
10357 flushPendingInstructions(Out);
10358 unsigned PlainMatchResult =
10359 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm);
10360 if (PlainMatchResult == Match_Success) {
10361 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10362 if (MCID.isPredicable()) {
10363 ARMCC::CondCodes InstCond =
10364 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10365 .getImm();
10366 // Some forms of the branch instruction have their own condition code
10367 // fields, so can be conditionally executed without an IT block.
10368 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
10369 EmitInITBlock = false;
10370 return Match_Success;
10372 if (InstCond == ARMCC::AL) {
10373 EmitInITBlock = false;
10374 return Match_Success;
10376 } else {
10377 EmitInITBlock = false;
10378 return Match_Success;
10382 // Try to match in a new IT block. The matcher doesn't check the actual
10383 // condition, so we create an IT block with a dummy condition, and fix it up
10384 // once we know the actual condition.
10385 startImplicitITBlock();
10386 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) ==
10387 Match_Success) {
10388 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10389 if (MCID.isPredicable()) {
10390 ITState.Cond =
10391 (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
10392 .getImm();
10393 EmitInITBlock = true;
10394 return Match_Success;
10397 discardImplicitITBlock();
10399 // If none of these succeed, return the error we got when trying to match
10400 // outside any IT blocks.
10401 EmitInITBlock = false;
10402 return PlainMatchResult;
10405 static std::string ARMMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
10406 unsigned VariantID = 0);
10408 static const char *getSubtargetFeatureName(uint64_t Val);
10409 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
10410 OperandVector &Operands,
10411 MCStreamer &Out, uint64_t &ErrorInfo,
10412 bool MatchingInlineAsm) {
10413 MCInst Inst;
10414 unsigned MatchResult;
10415 bool PendConditionalInstruction = false;
10417 SmallVector<NearMissInfo, 4> NearMisses;
10418 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm,
10419 PendConditionalInstruction, Out);
10421 switch (MatchResult) {
10422 case Match_Success:
10423 LLVM_DEBUG(dbgs() << "Parsed as: ";
10424 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
10425 dbgs() << "\n");
10427 // Context sensitive operand constraints aren't handled by the matcher,
10428 // so check them here.
10429 if (validateInstruction(Inst, Operands)) {
10430 // Still progress the IT block, otherwise one wrong condition causes
10431 // nasty cascading errors.
10432 forwardITPosition();
10433 forwardVPTPosition();
10434 return true;
10437 { // processInstruction() updates inITBlock state, we need to save it away
10438 bool wasInITBlock = inITBlock();
10440 // Some instructions need post-processing to, for example, tweak which
10441 // encoding is selected. Loop on it while changes happen so the
10442 // individual transformations can chain off each other. E.g.,
10443 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
10444 while (processInstruction(Inst, Operands, Out))
10445 LLVM_DEBUG(dbgs() << "Changed to: ";
10446 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
10447 dbgs() << "\n");
10449 // Only after the instruction is fully processed, we can validate it
10450 if (wasInITBlock && hasV8Ops() && isThumb() &&
10451 !isV8EligibleForIT(&Inst)) {
10452 Warning(IDLoc, "deprecated instruction in IT block");
10456 // Only move forward at the very end so that everything in validate
10457 // and process gets a consistent answer about whether we're in an IT
10458 // block.
10459 forwardITPosition();
10460 forwardVPTPosition();
10462 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
10463 // doesn't actually encode.
10464 if (Inst.getOpcode() == ARM::ITasm)
10465 return false;
10467 Inst.setLoc(IDLoc);
10468 if (PendConditionalInstruction) {
10469 PendingConditionalInsts.push_back(Inst);
10470 if (isITBlockFull() || isITBlockTerminator(Inst))
10471 flushPendingInstructions(Out);
10472 } else {
10473 Out.EmitInstruction(Inst, getSTI());
10475 return false;
10476 case Match_NearMisses:
10477 ReportNearMisses(NearMisses, IDLoc, Operands);
10478 return true;
10479 case Match_MnemonicFail: {
10480 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
10481 std::string Suggestion = ARMMnemonicSpellCheck(
10482 ((ARMOperand &)*Operands[0]).getToken(), FBS);
10483 return Error(IDLoc, "invalid instruction" + Suggestion,
10484 ((ARMOperand &)*Operands[0]).getLocRange());
10488 llvm_unreachable("Implement any new match types added!");
10491 /// parseDirective parses the arm specific directives
10492 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
10493 const MCObjectFileInfo::Environment Format =
10494 getContext().getObjectFileInfo()->getObjectFileType();
10495 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
10496 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
10498 StringRef IDVal = DirectiveID.getIdentifier();
10499 if (IDVal == ".word")
10500 parseLiteralValues(4, DirectiveID.getLoc());
10501 else if (IDVal == ".short" || IDVal == ".hword")
10502 parseLiteralValues(2, DirectiveID.getLoc());
10503 else if (IDVal == ".thumb")
10504 parseDirectiveThumb(DirectiveID.getLoc());
10505 else if (IDVal == ".arm")
10506 parseDirectiveARM(DirectiveID.getLoc());
10507 else if (IDVal == ".thumb_func")
10508 parseDirectiveThumbFunc(DirectiveID.getLoc());
10509 else if (IDVal == ".code")
10510 parseDirectiveCode(DirectiveID.getLoc());
10511 else if (IDVal == ".syntax")
10512 parseDirectiveSyntax(DirectiveID.getLoc());
10513 else if (IDVal == ".unreq")
10514 parseDirectiveUnreq(DirectiveID.getLoc());
10515 else if (IDVal == ".fnend")
10516 parseDirectiveFnEnd(DirectiveID.getLoc());
10517 else if (IDVal == ".cantunwind")
10518 parseDirectiveCantUnwind(DirectiveID.getLoc());
10519 else if (IDVal == ".personality")
10520 parseDirectivePersonality(DirectiveID.getLoc());
10521 else if (IDVal == ".handlerdata")
10522 parseDirectiveHandlerData(DirectiveID.getLoc());
10523 else if (IDVal == ".setfp")
10524 parseDirectiveSetFP(DirectiveID.getLoc());
10525 else if (IDVal == ".pad")
10526 parseDirectivePad(DirectiveID.getLoc());
10527 else if (IDVal == ".save")
10528 parseDirectiveRegSave(DirectiveID.getLoc(), false);
10529 else if (IDVal == ".vsave")
10530 parseDirectiveRegSave(DirectiveID.getLoc(), true);
10531 else if (IDVal == ".ltorg" || IDVal == ".pool")
10532 parseDirectiveLtorg(DirectiveID.getLoc());
10533 else if (IDVal == ".even")
10534 parseDirectiveEven(DirectiveID.getLoc());
10535 else if (IDVal == ".personalityindex")
10536 parseDirectivePersonalityIndex(DirectiveID.getLoc());
10537 else if (IDVal == ".unwind_raw")
10538 parseDirectiveUnwindRaw(DirectiveID.getLoc());
10539 else if (IDVal == ".movsp")
10540 parseDirectiveMovSP(DirectiveID.getLoc());
10541 else if (IDVal == ".arch_extension")
10542 parseDirectiveArchExtension(DirectiveID.getLoc());
10543 else if (IDVal == ".align")
10544 return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
10545 else if (IDVal == ".thumb_set")
10546 parseDirectiveThumbSet(DirectiveID.getLoc());
10547 else if (IDVal == ".inst")
10548 parseDirectiveInst(DirectiveID.getLoc());
10549 else if (IDVal == ".inst.n")
10550 parseDirectiveInst(DirectiveID.getLoc(), 'n');
10551 else if (IDVal == ".inst.w")
10552 parseDirectiveInst(DirectiveID.getLoc(), 'w');
10553 else if (!IsMachO && !IsCOFF) {
10554 if (IDVal == ".arch")
10555 parseDirectiveArch(DirectiveID.getLoc());
10556 else if (IDVal == ".cpu")
10557 parseDirectiveCPU(DirectiveID.getLoc());
10558 else if (IDVal == ".eabi_attribute")
10559 parseDirectiveEabiAttr(DirectiveID.getLoc());
10560 else if (IDVal == ".fpu")
10561 parseDirectiveFPU(DirectiveID.getLoc());
10562 else if (IDVal == ".fnstart")
10563 parseDirectiveFnStart(DirectiveID.getLoc());
10564 else if (IDVal == ".object_arch")
10565 parseDirectiveObjectArch(DirectiveID.getLoc());
10566 else if (IDVal == ".tlsdescseq")
10567 parseDirectiveTLSDescSeq(DirectiveID.getLoc());
10568 else
10569 return true;
10570 } else
10571 return true;
10572 return false;
10575 /// parseLiteralValues
10576 /// ::= .hword expression [, expression]*
10577 /// ::= .short expression [, expression]*
10578 /// ::= .word expression [, expression]*
10579 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
10580 auto parseOne = [&]() -> bool {
10581 const MCExpr *Value;
10582 if (getParser().parseExpression(Value))
10583 return true;
10584 getParser().getStreamer().EmitValue(Value, Size, L);
10585 return false;
10587 return (parseMany(parseOne));
10590 /// parseDirectiveThumb
10591 /// ::= .thumb
10592 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
10593 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
10594 check(!hasThumb(), L, "target does not support Thumb mode"))
10595 return true;
10597 if (!isThumb())
10598 SwitchMode();
10600 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
10601 return false;
10604 /// parseDirectiveARM
10605 /// ::= .arm
10606 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
10607 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
10608 check(!hasARM(), L, "target does not support ARM mode"))
10609 return true;
10611 if (isThumb())
10612 SwitchMode();
10613 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
10614 return false;
10617 void ARMAsmParser::doBeforeLabelEmit(MCSymbol *Symbol) {
10618 // We need to flush the current implicit IT block on a label, because it is
10619 // not legal to branch into an IT block.
10620 flushPendingInstructions(getStreamer());
10623 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
10624 if (NextSymbolIsThumb) {
10625 getParser().getStreamer().EmitThumbFunc(Symbol);
10626 NextSymbolIsThumb = false;
10630 /// parseDirectiveThumbFunc
10631 /// ::= .thumbfunc symbol_name
10632 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
10633 MCAsmParser &Parser = getParser();
10634 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
10635 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
10637 // Darwin asm has (optionally) function name after .thumb_func direction
10638 // ELF doesn't
10640 if (IsMachO) {
10641 if (Parser.getTok().is(AsmToken::Identifier) ||
10642 Parser.getTok().is(AsmToken::String)) {
10643 MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
10644 Parser.getTok().getIdentifier());
10645 getParser().getStreamer().EmitThumbFunc(Func);
10646 Parser.Lex();
10647 if (parseToken(AsmToken::EndOfStatement,
10648 "unexpected token in '.thumb_func' directive"))
10649 return true;
10650 return false;
10654 if (parseToken(AsmToken::EndOfStatement,
10655 "unexpected token in '.thumb_func' directive"))
10656 return true;
10658 NextSymbolIsThumb = true;
10659 return false;
10662 /// parseDirectiveSyntax
10663 /// ::= .syntax unified | divided
10664 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
10665 MCAsmParser &Parser = getParser();
10666 const AsmToken &Tok = Parser.getTok();
10667 if (Tok.isNot(AsmToken::Identifier)) {
10668 Error(L, "unexpected token in .syntax directive");
10669 return false;
10672 StringRef Mode = Tok.getString();
10673 Parser.Lex();
10674 if (check(Mode == "divided" || Mode == "DIVIDED", L,
10675 "'.syntax divided' arm assembly not supported") ||
10676 check(Mode != "unified" && Mode != "UNIFIED", L,
10677 "unrecognized syntax mode in .syntax directive") ||
10678 parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10679 return true;
10681 // TODO tell the MC streamer the mode
10682 // getParser().getStreamer().Emit???();
10683 return false;
10686 /// parseDirectiveCode
10687 /// ::= .code 16 | 32
10688 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
10689 MCAsmParser &Parser = getParser();
10690 const AsmToken &Tok = Parser.getTok();
10691 if (Tok.isNot(AsmToken::Integer))
10692 return Error(L, "unexpected token in .code directive");
10693 int64_t Val = Parser.getTok().getIntVal();
10694 if (Val != 16 && Val != 32) {
10695 Error(L, "invalid operand to .code directive");
10696 return false;
10698 Parser.Lex();
10700 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
10701 return true;
10703 if (Val == 16) {
10704 if (!hasThumb())
10705 return Error(L, "target does not support Thumb mode");
10707 if (!isThumb())
10708 SwitchMode();
10709 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
10710 } else {
10711 if (!hasARM())
10712 return Error(L, "target does not support ARM mode");
10714 if (isThumb())
10715 SwitchMode();
10716 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
10719 return false;
10722 /// parseDirectiveReq
10723 /// ::= name .req registername
10724 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
10725 MCAsmParser &Parser = getParser();
10726 Parser.Lex(); // Eat the '.req' token.
10727 unsigned Reg;
10728 SMLoc SRegLoc, ERegLoc;
10729 if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
10730 "register name expected") ||
10731 parseToken(AsmToken::EndOfStatement,
10732 "unexpected input in .req directive."))
10733 return true;
10735 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
10736 return Error(SRegLoc,
10737 "redefinition of '" + Name + "' does not match original.");
10739 return false;
10742 /// parseDirectiveUneq
10743 /// ::= .unreq registername
10744 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
10745 MCAsmParser &Parser = getParser();
10746 if (Parser.getTok().isNot(AsmToken::Identifier))
10747 return Error(L, "unexpected input in .unreq directive.");
10748 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
10749 Parser.Lex(); // Eat the identifier.
10750 if (parseToken(AsmToken::EndOfStatement,
10751 "unexpected input in '.unreq' directive"))
10752 return true;
10753 return false;
10756 // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
10757 // before, if supported by the new target, or emit mapping symbols for the mode
10758 // switch.
10759 void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
10760 if (WasThumb != isThumb()) {
10761 if (WasThumb && hasThumb()) {
10762 // Stay in Thumb mode
10763 SwitchMode();
10764 } else if (!WasThumb && hasARM()) {
10765 // Stay in ARM mode
10766 SwitchMode();
10767 } else {
10768 // Mode switch forced, because the new arch doesn't support the old mode.
10769 getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16
10770 : MCAF_Code32);
10771 // Warn about the implcit mode switch. GAS does not switch modes here,
10772 // but instead stays in the old mode, reporting an error on any following
10773 // instructions as the mode does not exist on the target.
10774 Warning(Loc, Twine("new target does not support ") +
10775 (WasThumb ? "thumb" : "arm") + " mode, switching to " +
10776 (!WasThumb ? "thumb" : "arm") + " mode");
10781 /// parseDirectiveArch
10782 /// ::= .arch token
10783 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
10784 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
10785 ARM::ArchKind ID = ARM::parseArch(Arch);
10787 if (ID == ARM::ArchKind::INVALID)
10788 return Error(L, "Unknown arch name");
10790 bool WasThumb = isThumb();
10791 Triple T;
10792 MCSubtargetInfo &STI = copySTI();
10793 STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
10794 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
10795 FixModeAfterArchChange(WasThumb, L);
10797 getTargetStreamer().emitArch(ID);
10798 return false;
10801 /// parseDirectiveEabiAttr
10802 /// ::= .eabi_attribute int, int [, "str"]
10803 /// ::= .eabi_attribute Tag_name, int [, "str"]
10804 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
10805 MCAsmParser &Parser = getParser();
10806 int64_t Tag;
10807 SMLoc TagLoc;
10808 TagLoc = Parser.getTok().getLoc();
10809 if (Parser.getTok().is(AsmToken::Identifier)) {
10810 StringRef Name = Parser.getTok().getIdentifier();
10811 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
10812 if (Tag == -1) {
10813 Error(TagLoc, "attribute name not recognised: " + Name);
10814 return false;
10816 Parser.Lex();
10817 } else {
10818 const MCExpr *AttrExpr;
10820 TagLoc = Parser.getTok().getLoc();
10821 if (Parser.parseExpression(AttrExpr))
10822 return true;
10824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
10825 if (check(!CE, TagLoc, "expected numeric constant"))
10826 return true;
10828 Tag = CE->getValue();
10831 if (Parser.parseToken(AsmToken::Comma, "comma expected"))
10832 return true;
10834 StringRef StringValue = "";
10835 bool IsStringValue = false;
10837 int64_t IntegerValue = 0;
10838 bool IsIntegerValue = false;
10840 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
10841 IsStringValue = true;
10842 else if (Tag == ARMBuildAttrs::compatibility) {
10843 IsStringValue = true;
10844 IsIntegerValue = true;
10845 } else if (Tag < 32 || Tag % 2 == 0)
10846 IsIntegerValue = true;
10847 else if (Tag % 2 == 1)
10848 IsStringValue = true;
10849 else
10850 llvm_unreachable("invalid tag type");
10852 if (IsIntegerValue) {
10853 const MCExpr *ValueExpr;
10854 SMLoc ValueExprLoc = Parser.getTok().getLoc();
10855 if (Parser.parseExpression(ValueExpr))
10856 return true;
10858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
10859 if (!CE)
10860 return Error(ValueExprLoc, "expected numeric constant");
10861 IntegerValue = CE->getValue();
10864 if (Tag == ARMBuildAttrs::compatibility) {
10865 if (Parser.parseToken(AsmToken::Comma, "comma expected"))
10866 return true;
10869 if (IsStringValue) {
10870 if (Parser.getTok().isNot(AsmToken::String))
10871 return Error(Parser.getTok().getLoc(), "bad string constant");
10873 StringValue = Parser.getTok().getStringContents();
10874 Parser.Lex();
10877 if (Parser.parseToken(AsmToken::EndOfStatement,
10878 "unexpected token in '.eabi_attribute' directive"))
10879 return true;
10881 if (IsIntegerValue && IsStringValue) {
10882 assert(Tag == ARMBuildAttrs::compatibility);
10883 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
10884 } else if (IsIntegerValue)
10885 getTargetStreamer().emitAttribute(Tag, IntegerValue);
10886 else if (IsStringValue)
10887 getTargetStreamer().emitTextAttribute(Tag, StringValue);
10888 return false;
10891 /// parseDirectiveCPU
10892 /// ::= .cpu str
10893 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
10894 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
10895 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
10897 // FIXME: This is using table-gen data, but should be moved to
10898 // ARMTargetParser once that is table-gen'd.
10899 if (!getSTI().isCPUStringValid(CPU))
10900 return Error(L, "Unknown CPU name");
10902 bool WasThumb = isThumb();
10903 MCSubtargetInfo &STI = copySTI();
10904 STI.setDefaultFeatures(CPU, "");
10905 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
10906 FixModeAfterArchChange(WasThumb, L);
10908 return false;
10911 /// parseDirectiveFPU
10912 /// ::= .fpu str
10913 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
10914 SMLoc FPUNameLoc = getTok().getLoc();
10915 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
10917 unsigned ID = ARM::parseFPU(FPU);
10918 std::vector<StringRef> Features;
10919 if (!ARM::getFPUFeatures(ID, Features))
10920 return Error(FPUNameLoc, "Unknown FPU name");
10922 MCSubtargetInfo &STI = copySTI();
10923 for (auto Feature : Features)
10924 STI.ApplyFeatureFlag(Feature);
10925 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
10927 getTargetStreamer().emitFPU(ID);
10928 return false;
10931 /// parseDirectiveFnStart
10932 /// ::= .fnstart
10933 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
10934 if (parseToken(AsmToken::EndOfStatement,
10935 "unexpected token in '.fnstart' directive"))
10936 return true;
10938 if (UC.hasFnStart()) {
10939 Error(L, ".fnstart starts before the end of previous one");
10940 UC.emitFnStartLocNotes();
10941 return true;
10944 // Reset the unwind directives parser state
10945 UC.reset();
10947 getTargetStreamer().emitFnStart();
10949 UC.recordFnStart(L);
10950 return false;
10953 /// parseDirectiveFnEnd
10954 /// ::= .fnend
10955 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
10956 if (parseToken(AsmToken::EndOfStatement,
10957 "unexpected token in '.fnend' directive"))
10958 return true;
10959 // Check the ordering of unwind directives
10960 if (!UC.hasFnStart())
10961 return Error(L, ".fnstart must precede .fnend directive");
10963 // Reset the unwind directives parser state
10964 getTargetStreamer().emitFnEnd();
10966 UC.reset();
10967 return false;
10970 /// parseDirectiveCantUnwind
10971 /// ::= .cantunwind
10972 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
10973 if (parseToken(AsmToken::EndOfStatement,
10974 "unexpected token in '.cantunwind' directive"))
10975 return true;
10977 UC.recordCantUnwind(L);
10978 // Check the ordering of unwind directives
10979 if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
10980 return true;
10982 if (UC.hasHandlerData()) {
10983 Error(L, ".cantunwind can't be used with .handlerdata directive");
10984 UC.emitHandlerDataLocNotes();
10985 return true;
10987 if (UC.hasPersonality()) {
10988 Error(L, ".cantunwind can't be used with .personality directive");
10989 UC.emitPersonalityLocNotes();
10990 return true;
10993 getTargetStreamer().emitCantUnwind();
10994 return false;
10997 /// parseDirectivePersonality
10998 /// ::= .personality name
10999 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
11000 MCAsmParser &Parser = getParser();
11001 bool HasExistingPersonality = UC.hasPersonality();
11003 // Parse the name of the personality routine
11004 if (Parser.getTok().isNot(AsmToken::Identifier))
11005 return Error(L, "unexpected input in .personality directive.");
11006 StringRef Name(Parser.getTok().getIdentifier());
11007 Parser.Lex();
11009 if (parseToken(AsmToken::EndOfStatement,
11010 "unexpected token in '.personality' directive"))
11011 return true;
11013 UC.recordPersonality(L);
11015 // Check the ordering of unwind directives
11016 if (!UC.hasFnStart())
11017 return Error(L, ".fnstart must precede .personality directive");
11018 if (UC.cantUnwind()) {
11019 Error(L, ".personality can't be used with .cantunwind directive");
11020 UC.emitCantUnwindLocNotes();
11021 return true;
11023 if (UC.hasHandlerData()) {
11024 Error(L, ".personality must precede .handlerdata directive");
11025 UC.emitHandlerDataLocNotes();
11026 return true;
11028 if (HasExistingPersonality) {
11029 Error(L, "multiple personality directives");
11030 UC.emitPersonalityLocNotes();
11031 return true;
11034 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
11035 getTargetStreamer().emitPersonality(PR);
11036 return false;
11039 /// parseDirectiveHandlerData
11040 /// ::= .handlerdata
11041 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
11042 if (parseToken(AsmToken::EndOfStatement,
11043 "unexpected token in '.handlerdata' directive"))
11044 return true;
11046 UC.recordHandlerData(L);
11047 // Check the ordering of unwind directives
11048 if (!UC.hasFnStart())
11049 return Error(L, ".fnstart must precede .personality directive");
11050 if (UC.cantUnwind()) {
11051 Error(L, ".handlerdata can't be used with .cantunwind directive");
11052 UC.emitCantUnwindLocNotes();
11053 return true;
11056 getTargetStreamer().emitHandlerData();
11057 return false;
11060 /// parseDirectiveSetFP
11061 /// ::= .setfp fpreg, spreg [, offset]
11062 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
11063 MCAsmParser &Parser = getParser();
11064 // Check the ordering of unwind directives
11065 if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
11066 check(UC.hasHandlerData(), L,
11067 ".setfp must precede .handlerdata directive"))
11068 return true;
11070 // Parse fpreg
11071 SMLoc FPRegLoc = Parser.getTok().getLoc();
11072 int FPReg = tryParseRegister();
11074 if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
11075 Parser.parseToken(AsmToken::Comma, "comma expected"))
11076 return true;
11078 // Parse spreg
11079 SMLoc SPRegLoc = Parser.getTok().getLoc();
11080 int SPReg = tryParseRegister();
11081 if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
11082 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
11083 "register should be either $sp or the latest fp register"))
11084 return true;
11086 // Update the frame pointer register
11087 UC.saveFPReg(FPReg);
11089 // Parse offset
11090 int64_t Offset = 0;
11091 if (Parser.parseOptionalToken(AsmToken::Comma)) {
11092 if (Parser.getTok().isNot(AsmToken::Hash) &&
11093 Parser.getTok().isNot(AsmToken::Dollar))
11094 return Error(Parser.getTok().getLoc(), "'#' expected");
11095 Parser.Lex(); // skip hash token.
11097 const MCExpr *OffsetExpr;
11098 SMLoc ExLoc = Parser.getTok().getLoc();
11099 SMLoc EndLoc;
11100 if (getParser().parseExpression(OffsetExpr, EndLoc))
11101 return Error(ExLoc, "malformed setfp offset");
11102 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11103 if (check(!CE, ExLoc, "setfp offset must be an immediate"))
11104 return true;
11105 Offset = CE->getValue();
11108 if (Parser.parseToken(AsmToken::EndOfStatement))
11109 return true;
11111 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
11112 static_cast<unsigned>(SPReg), Offset);
11113 return false;
11116 /// parseDirective
11117 /// ::= .pad offset
11118 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
11119 MCAsmParser &Parser = getParser();
11120 // Check the ordering of unwind directives
11121 if (!UC.hasFnStart())
11122 return Error(L, ".fnstart must precede .pad directive");
11123 if (UC.hasHandlerData())
11124 return Error(L, ".pad must precede .handlerdata directive");
11126 // Parse the offset
11127 if (Parser.getTok().isNot(AsmToken::Hash) &&
11128 Parser.getTok().isNot(AsmToken::Dollar))
11129 return Error(Parser.getTok().getLoc(), "'#' expected");
11130 Parser.Lex(); // skip hash token.
11132 const MCExpr *OffsetExpr;
11133 SMLoc ExLoc = Parser.getTok().getLoc();
11134 SMLoc EndLoc;
11135 if (getParser().parseExpression(OffsetExpr, EndLoc))
11136 return Error(ExLoc, "malformed pad offset");
11137 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11138 if (!CE)
11139 return Error(ExLoc, "pad offset must be an immediate");
11141 if (parseToken(AsmToken::EndOfStatement,
11142 "unexpected token in '.pad' directive"))
11143 return true;
11145 getTargetStreamer().emitPad(CE->getValue());
11146 return false;
11149 /// parseDirectiveRegSave
11150 /// ::= .save { registers }
11151 /// ::= .vsave { registers }
11152 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
11153 // Check the ordering of unwind directives
11154 if (!UC.hasFnStart())
11155 return Error(L, ".fnstart must precede .save or .vsave directives");
11156 if (UC.hasHandlerData())
11157 return Error(L, ".save or .vsave must precede .handlerdata directive");
11159 // RAII object to make sure parsed operands are deleted.
11160 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
11162 // Parse the register list
11163 if (parseRegisterList(Operands) ||
11164 parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11165 return true;
11166 ARMOperand &Op = (ARMOperand &)*Operands[0];
11167 if (!IsVector && !Op.isRegList())
11168 return Error(L, ".save expects GPR registers");
11169 if (IsVector && !Op.isDPRRegList())
11170 return Error(L, ".vsave expects DPR registers");
11172 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
11173 return false;
11176 /// parseDirectiveInst
11177 /// ::= .inst opcode [, ...]
11178 /// ::= .inst.n opcode [, ...]
11179 /// ::= .inst.w opcode [, ...]
11180 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
11181 int Width = 4;
11183 if (isThumb()) {
11184 switch (Suffix) {
11185 case 'n':
11186 Width = 2;
11187 break;
11188 case 'w':
11189 break;
11190 default:
11191 Width = 0;
11192 break;
11194 } else {
11195 if (Suffix)
11196 return Error(Loc, "width suffixes are invalid in ARM mode");
11199 auto parseOne = [&]() -> bool {
11200 const MCExpr *Expr;
11201 if (getParser().parseExpression(Expr))
11202 return true;
11203 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
11204 if (!Value) {
11205 return Error(Loc, "expected constant expression");
11208 char CurSuffix = Suffix;
11209 switch (Width) {
11210 case 2:
11211 if (Value->getValue() > 0xffff)
11212 return Error(Loc, "inst.n operand is too big, use inst.w instead");
11213 break;
11214 case 4:
11215 if (Value->getValue() > 0xffffffff)
11216 return Error(Loc, StringRef(Suffix ? "inst.w" : "inst") +
11217 " operand is too big");
11218 break;
11219 case 0:
11220 // Thumb mode, no width indicated. Guess from the opcode, if possible.
11221 if (Value->getValue() < 0xe800)
11222 CurSuffix = 'n';
11223 else if (Value->getValue() >= 0xe8000000)
11224 CurSuffix = 'w';
11225 else
11226 return Error(Loc, "cannot determine Thumb instruction size, "
11227 "use inst.n/inst.w instead");
11228 break;
11229 default:
11230 llvm_unreachable("only supported widths are 2 and 4");
11233 getTargetStreamer().emitInst(Value->getValue(), CurSuffix);
11234 return false;
11237 if (parseOptionalToken(AsmToken::EndOfStatement))
11238 return Error(Loc, "expected expression following directive");
11239 if (parseMany(parseOne))
11240 return true;
11241 return false;
11244 /// parseDirectiveLtorg
11245 /// ::= .ltorg | .pool
11246 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
11247 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11248 return true;
11249 getTargetStreamer().emitCurrentConstantPool();
11250 return false;
11253 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
11254 const MCSection *Section = getStreamer().getCurrentSectionOnly();
11256 if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
11257 return true;
11259 if (!Section) {
11260 getStreamer().InitSections(false);
11261 Section = getStreamer().getCurrentSectionOnly();
11264 assert(Section && "must have section to emit alignment");
11265 if (Section->UseCodeAlign())
11266 getStreamer().EmitCodeAlignment(2);
11267 else
11268 getStreamer().EmitValueToAlignment(2);
11270 return false;
11273 /// parseDirectivePersonalityIndex
11274 /// ::= .personalityindex index
11275 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
11276 MCAsmParser &Parser = getParser();
11277 bool HasExistingPersonality = UC.hasPersonality();
11279 const MCExpr *IndexExpression;
11280 SMLoc IndexLoc = Parser.getTok().getLoc();
11281 if (Parser.parseExpression(IndexExpression) ||
11282 parseToken(AsmToken::EndOfStatement,
11283 "unexpected token in '.personalityindex' directive")) {
11284 return true;
11287 UC.recordPersonalityIndex(L);
11289 if (!UC.hasFnStart()) {
11290 return Error(L, ".fnstart must precede .personalityindex directive");
11292 if (UC.cantUnwind()) {
11293 Error(L, ".personalityindex cannot be used with .cantunwind");
11294 UC.emitCantUnwindLocNotes();
11295 return true;
11297 if (UC.hasHandlerData()) {
11298 Error(L, ".personalityindex must precede .handlerdata directive");
11299 UC.emitHandlerDataLocNotes();
11300 return true;
11302 if (HasExistingPersonality) {
11303 Error(L, "multiple personality directives");
11304 UC.emitPersonalityLocNotes();
11305 return true;
11308 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
11309 if (!CE)
11310 return Error(IndexLoc, "index must be a constant number");
11311 if (CE->getValue() < 0 || CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX)
11312 return Error(IndexLoc,
11313 "personality routine index should be in range [0-3]");
11315 getTargetStreamer().emitPersonalityIndex(CE->getValue());
11316 return false;
11319 /// parseDirectiveUnwindRaw
11320 /// ::= .unwind_raw offset, opcode [, opcode...]
11321 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
11322 MCAsmParser &Parser = getParser();
11323 int64_t StackOffset;
11324 const MCExpr *OffsetExpr;
11325 SMLoc OffsetLoc = getLexer().getLoc();
11327 if (!UC.hasFnStart())
11328 return Error(L, ".fnstart must precede .unwind_raw directives");
11329 if (getParser().parseExpression(OffsetExpr))
11330 return Error(OffsetLoc, "expected expression");
11332 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11333 if (!CE)
11334 return Error(OffsetLoc, "offset must be a constant");
11336 StackOffset = CE->getValue();
11338 if (Parser.parseToken(AsmToken::Comma, "expected comma"))
11339 return true;
11341 SmallVector<uint8_t, 16> Opcodes;
11343 auto parseOne = [&]() -> bool {
11344 const MCExpr *OE = nullptr;
11345 SMLoc OpcodeLoc = getLexer().getLoc();
11346 if (check(getLexer().is(AsmToken::EndOfStatement) ||
11347 Parser.parseExpression(OE),
11348 OpcodeLoc, "expected opcode expression"))
11349 return true;
11350 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
11351 if (!OC)
11352 return Error(OpcodeLoc, "opcode value must be a constant");
11353 const int64_t Opcode = OC->getValue();
11354 if (Opcode & ~0xff)
11355 return Error(OpcodeLoc, "invalid opcode");
11356 Opcodes.push_back(uint8_t(Opcode));
11357 return false;
11360 // Must have at least 1 element
11361 SMLoc OpcodeLoc = getLexer().getLoc();
11362 if (parseOptionalToken(AsmToken::EndOfStatement))
11363 return Error(OpcodeLoc, "expected opcode expression");
11364 if (parseMany(parseOne))
11365 return true;
11367 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
11368 return false;
11371 /// parseDirectiveTLSDescSeq
11372 /// ::= .tlsdescseq tls-variable
11373 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
11374 MCAsmParser &Parser = getParser();
11376 if (getLexer().isNot(AsmToken::Identifier))
11377 return TokError("expected variable after '.tlsdescseq' directive");
11379 const MCSymbolRefExpr *SRE =
11380 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
11381 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
11382 Lex();
11384 if (parseToken(AsmToken::EndOfStatement,
11385 "unexpected token in '.tlsdescseq' directive"))
11386 return true;
11388 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
11389 return false;
11392 /// parseDirectiveMovSP
11393 /// ::= .movsp reg [, #offset]
11394 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
11395 MCAsmParser &Parser = getParser();
11396 if (!UC.hasFnStart())
11397 return Error(L, ".fnstart must precede .movsp directives");
11398 if (UC.getFPReg() != ARM::SP)
11399 return Error(L, "unexpected .movsp directive");
11401 SMLoc SPRegLoc = Parser.getTok().getLoc();
11402 int SPReg = tryParseRegister();
11403 if (SPReg == -1)
11404 return Error(SPRegLoc, "register expected");
11405 if (SPReg == ARM::SP || SPReg == ARM::PC)
11406 return Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
11408 int64_t Offset = 0;
11409 if (Parser.parseOptionalToken(AsmToken::Comma)) {
11410 if (Parser.parseToken(AsmToken::Hash, "expected #constant"))
11411 return true;
11413 const MCExpr *OffsetExpr;
11414 SMLoc OffsetLoc = Parser.getTok().getLoc();
11416 if (Parser.parseExpression(OffsetExpr))
11417 return Error(OffsetLoc, "malformed offset expression");
11419 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
11420 if (!CE)
11421 return Error(OffsetLoc, "offset must be an immediate constant");
11423 Offset = CE->getValue();
11426 if (parseToken(AsmToken::EndOfStatement,
11427 "unexpected token in '.movsp' directive"))
11428 return true;
11430 getTargetStreamer().emitMovSP(SPReg, Offset);
11431 UC.saveFPReg(SPReg);
11433 return false;
11436 /// parseDirectiveObjectArch
11437 /// ::= .object_arch name
11438 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
11439 MCAsmParser &Parser = getParser();
11440 if (getLexer().isNot(AsmToken::Identifier))
11441 return Error(getLexer().getLoc(), "unexpected token");
11443 StringRef Arch = Parser.getTok().getString();
11444 SMLoc ArchLoc = Parser.getTok().getLoc();
11445 Lex();
11447 ARM::ArchKind ID = ARM::parseArch(Arch);
11449 if (ID == ARM::ArchKind::INVALID)
11450 return Error(ArchLoc, "unknown architecture '" + Arch + "'");
11451 if (parseToken(AsmToken::EndOfStatement))
11452 return true;
11454 getTargetStreamer().emitObjectArch(ID);
11455 return false;
11458 /// parseDirectiveAlign
11459 /// ::= .align
11460 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
11461 // NOTE: if this is not the end of the statement, fall back to the target
11462 // agnostic handling for this directive which will correctly handle this.
11463 if (parseOptionalToken(AsmToken::EndOfStatement)) {
11464 // '.align' is target specifically handled to mean 2**2 byte alignment.
11465 const MCSection *Section = getStreamer().getCurrentSectionOnly();
11466 assert(Section && "must have section to emit alignment");
11467 if (Section->UseCodeAlign())
11468 getStreamer().EmitCodeAlignment(4, 0);
11469 else
11470 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
11471 return false;
11473 return true;
11476 /// parseDirectiveThumbSet
11477 /// ::= .thumb_set name, value
11478 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
11479 MCAsmParser &Parser = getParser();
11481 StringRef Name;
11482 if (check(Parser.parseIdentifier(Name),
11483 "expected identifier after '.thumb_set'") ||
11484 parseToken(AsmToken::Comma, "expected comma after name '" + Name + "'"))
11485 return true;
11487 MCSymbol *Sym;
11488 const MCExpr *Value;
11489 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
11490 Parser, Sym, Value))
11491 return true;
11493 getTargetStreamer().emitThumbSet(Sym, Value);
11494 return false;
11497 /// Force static initialization.
11498 extern "C" void LLVMInitializeARMAsmParser() {
11499 RegisterMCAsmParser<ARMAsmParser> X(getTheARMLETarget());
11500 RegisterMCAsmParser<ARMAsmParser> Y(getTheARMBETarget());
11501 RegisterMCAsmParser<ARMAsmParser> A(getTheThumbLETarget());
11502 RegisterMCAsmParser<ARMAsmParser> B(getTheThumbBETarget());
11505 #define GET_REGISTER_MATCHER
11506 #define GET_SUBTARGET_FEATURE_NAME
11507 #define GET_MATCHER_IMPLEMENTATION
11508 #define GET_MNEMONIC_SPELL_CHECKER
11509 #include "ARMGenAsmMatcher.inc"
11511 // Some diagnostics need to vary with subtarget features, so they are handled
11512 // here. For example, the DPR class has either 16 or 32 registers, depending
11513 // on the FPU available.
11514 const char *
11515 ARMAsmParser::getCustomOperandDiag(ARMMatchResultTy MatchError) {
11516 switch (MatchError) {
11517 // rGPR contains sp starting with ARMv8.
11518 case Match_rGPR:
11519 return hasV8Ops() ? "operand must be a register in range [r0, r14]"
11520 : "operand must be a register in range [r0, r12] or r14";
11521 // DPR contains 16 registers for some FPUs, and 32 for others.
11522 case Match_DPR:
11523 return hasD32() ? "operand must be a register in range [d0, d31]"
11524 : "operand must be a register in range [d0, d15]";
11525 case Match_DPR_RegList:
11526 return hasD32() ? "operand must be a list of registers in range [d0, d31]"
11527 : "operand must be a list of registers in range [d0, d15]";
11529 // For all other diags, use the static string from tablegen.
11530 default:
11531 return getMatchKindDiag(MatchError);
11535 // Process the list of near-misses, throwing away ones we don't want to report
11536 // to the user, and converting the rest to a source location and string that
11537 // should be reported.
11538 void
11539 ARMAsmParser::FilterNearMisses(SmallVectorImpl<NearMissInfo> &NearMissesIn,
11540 SmallVectorImpl<NearMissMessage> &NearMissesOut,
11541 SMLoc IDLoc, OperandVector &Operands) {
11542 // TODO: If operand didn't match, sub in a dummy one and run target
11543 // predicate, so that we can avoid reporting near-misses that are invalid?
11544 // TODO: Many operand types dont have SuperClasses set, so we report
11545 // redundant ones.
11546 // TODO: Some operands are superclasses of registers (e.g.
11547 // MCK_RegShiftedImm), we don't have any way to represent that currently.
11548 // TODO: This is not all ARM-specific, can some of it be factored out?
11550 // Record some information about near-misses that we have already seen, so
11551 // that we can avoid reporting redundant ones. For example, if there are
11552 // variants of an instruction that take 8- and 16-bit immediates, we want
11553 // to only report the widest one.
11554 std::multimap<unsigned, unsigned> OperandMissesSeen;
11555 SmallSet<FeatureBitset, 4> FeatureMissesSeen;
11556 bool ReportedTooFewOperands = false;
11558 // Process the near-misses in reverse order, so that we see more general ones
11559 // first, and so can avoid emitting more specific ones.
11560 for (NearMissInfo &I : reverse(NearMissesIn)) {
11561 switch (I.getKind()) {
11562 case NearMissInfo::NearMissOperand: {
11563 SMLoc OperandLoc =
11564 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc();
11565 const char *OperandDiag =
11566 getCustomOperandDiag((ARMMatchResultTy)I.getOperandError());
11568 // If we have already emitted a message for a superclass, don't also report
11569 // the sub-class. We consider all operand classes that we don't have a
11570 // specialised diagnostic for to be equal for the propose of this check,
11571 // so that we don't report the generic error multiple times on the same
11572 // operand.
11573 unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U;
11574 auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex());
11575 if (std::any_of(PrevReports.first, PrevReports.second,
11576 [DupCheckMatchClass](
11577 const std::pair<unsigned, unsigned> Pair) {
11578 if (DupCheckMatchClass == ~0U || Pair.second == ~0U)
11579 return Pair.second == DupCheckMatchClass;
11580 else
11581 return isSubclass((MatchClassKind)DupCheckMatchClass,
11582 (MatchClassKind)Pair.second);
11584 break;
11585 OperandMissesSeen.insert(
11586 std::make_pair(I.getOperandIndex(), DupCheckMatchClass));
11588 NearMissMessage Message;
11589 Message.Loc = OperandLoc;
11590 if (OperandDiag) {
11591 Message.Message = OperandDiag;
11592 } else if (I.getOperandClass() == InvalidMatchClass) {
11593 Message.Message = "too many operands for instruction";
11594 } else {
11595 Message.Message = "invalid operand for instruction";
11596 LLVM_DEBUG(
11597 dbgs() << "Missing diagnostic string for operand class "
11598 << getMatchClassName((MatchClassKind)I.getOperandClass())
11599 << I.getOperandClass() << ", error " << I.getOperandError()
11600 << ", opcode " << MII.getName(I.getOpcode()) << "\n");
11602 NearMissesOut.emplace_back(Message);
11603 break;
11605 case NearMissInfo::NearMissFeature: {
11606 const FeatureBitset &MissingFeatures = I.getFeatures();
11607 // Don't report the same set of features twice.
11608 if (FeatureMissesSeen.count(MissingFeatures))
11609 break;
11610 FeatureMissesSeen.insert(MissingFeatures);
11612 // Special case: don't report a feature set which includes arm-mode for
11613 // targets that don't have ARM mode.
11614 if (MissingFeatures.test(Feature_IsARMBit) && !hasARM())
11615 break;
11616 // Don't report any near-misses that both require switching instruction
11617 // set, and adding other subtarget features.
11618 if (isThumb() && MissingFeatures.test(Feature_IsARMBit) &&
11619 MissingFeatures.count() > 1)
11620 break;
11621 if (!isThumb() && MissingFeatures.test(Feature_IsThumbBit) &&
11622 MissingFeatures.count() > 1)
11623 break;
11624 if (!isThumb() && MissingFeatures.test(Feature_IsThumb2Bit) &&
11625 (MissingFeatures & ~FeatureBitset({Feature_IsThumb2Bit,
11626 Feature_IsThumbBit})).any())
11627 break;
11628 if (isMClass() && MissingFeatures.test(Feature_HasNEONBit))
11629 break;
11631 NearMissMessage Message;
11632 Message.Loc = IDLoc;
11633 raw_svector_ostream OS(Message.Message);
11635 OS << "instruction requires:";
11636 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
11637 if (MissingFeatures.test(i))
11638 OS << ' ' << getSubtargetFeatureName(i);
11640 NearMissesOut.emplace_back(Message);
11642 break;
11644 case NearMissInfo::NearMissPredicate: {
11645 NearMissMessage Message;
11646 Message.Loc = IDLoc;
11647 switch (I.getPredicateError()) {
11648 case Match_RequiresNotITBlock:
11649 Message.Message = "flag setting instruction only valid outside IT block";
11650 break;
11651 case Match_RequiresITBlock:
11652 Message.Message = "instruction only valid inside IT block";
11653 break;
11654 case Match_RequiresV6:
11655 Message.Message = "instruction variant requires ARMv6 or later";
11656 break;
11657 case Match_RequiresThumb2:
11658 Message.Message = "instruction variant requires Thumb2";
11659 break;
11660 case Match_RequiresV8:
11661 Message.Message = "instruction variant requires ARMv8 or later";
11662 break;
11663 case Match_RequiresFlagSetting:
11664 Message.Message = "no flag-preserving variant of this instruction available";
11665 break;
11666 case Match_InvalidOperand:
11667 Message.Message = "invalid operand for instruction";
11668 break;
11669 default:
11670 llvm_unreachable("Unhandled target predicate error");
11671 break;
11673 NearMissesOut.emplace_back(Message);
11674 break;
11676 case NearMissInfo::NearMissTooFewOperands: {
11677 if (!ReportedTooFewOperands) {
11678 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc();
11679 NearMissesOut.emplace_back(NearMissMessage{
11680 EndLoc, StringRef("too few operands for instruction")});
11681 ReportedTooFewOperands = true;
11683 break;
11685 case NearMissInfo::NoNearMiss:
11686 // This should never leave the matcher.
11687 llvm_unreachable("not a near-miss");
11688 break;
11693 void ARMAsmParser::ReportNearMisses(SmallVectorImpl<NearMissInfo> &NearMisses,
11694 SMLoc IDLoc, OperandVector &Operands) {
11695 SmallVector<NearMissMessage, 4> Messages;
11696 FilterNearMisses(NearMisses, Messages, IDLoc, Operands);
11698 if (Messages.size() == 0) {
11699 // No near-misses were found, so the best we can do is "invalid
11700 // instruction".
11701 Error(IDLoc, "invalid instruction");
11702 } else if (Messages.size() == 1) {
11703 // One near miss was found, report it as the sole error.
11704 Error(Messages[0].Loc, Messages[0].Message);
11705 } else {
11706 // More than one near miss, so report a generic "invalid instruction"
11707 // error, followed by notes for each of the near-misses.
11708 Error(IDLoc, "invalid instruction, any one of the following would fix this:");
11709 for (auto &M : Messages) {
11710 Note(M.Loc, M.Message);
11715 /// parseDirectiveArchExtension
11716 /// ::= .arch_extension [no]feature
11717 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
11718 // FIXME: This structure should be moved inside ARMTargetParser
11719 // when we start to table-generate them, and we can use the ARM
11720 // flags below, that were generated by table-gen.
11721 static const struct {
11722 const unsigned Kind;
11723 const FeatureBitset ArchCheck;
11724 const FeatureBitset Features;
11725 } Extensions[] = {
11726 { ARM::AEK_CRC, {Feature_HasV8Bit}, {ARM::FeatureCRC} },
11727 { ARM::AEK_CRYPTO, {Feature_HasV8Bit},
11728 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
11729 { ARM::AEK_FP, {Feature_HasV8Bit},
11730 {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
11731 { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM),
11732 {Feature_HasV7Bit, Feature_IsNotMClassBit},
11733 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
11734 { ARM::AEK_MP, {Feature_HasV7Bit, Feature_IsNotMClassBit},
11735 {ARM::FeatureMP} },
11736 { ARM::AEK_SIMD, {Feature_HasV8Bit},
11737 {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
11738 { ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone} },
11739 // FIXME: Only available in A-class, isel not predicated
11740 { ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization} },
11741 { ARM::AEK_FP16, {Feature_HasV8_2aBit},
11742 {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
11743 { ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS} },
11744 { ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB} },
11745 // FIXME: Unsupported extensions.
11746 { ARM::AEK_OS, {}, {} },
11747 { ARM::AEK_IWMMXT, {}, {} },
11748 { ARM::AEK_IWMMXT2, {}, {} },
11749 { ARM::AEK_MAVERICK, {}, {} },
11750 { ARM::AEK_XSCALE, {}, {} },
11753 MCAsmParser &Parser = getParser();
11755 if (getLexer().isNot(AsmToken::Identifier))
11756 return Error(getLexer().getLoc(), "expected architecture extension name");
11758 StringRef Name = Parser.getTok().getString();
11759 SMLoc ExtLoc = Parser.getTok().getLoc();
11760 Lex();
11762 if (parseToken(AsmToken::EndOfStatement,
11763 "unexpected token in '.arch_extension' directive"))
11764 return true;
11766 bool EnableFeature = true;
11767 if (Name.startswith_lower("no")) {
11768 EnableFeature = false;
11769 Name = Name.substr(2);
11771 unsigned FeatureKind = ARM::parseArchExt(Name);
11772 if (FeatureKind == ARM::AEK_INVALID)
11773 return Error(ExtLoc, "unknown architectural extension: " + Name);
11775 for (const auto &Extension : Extensions) {
11776 if (Extension.Kind != FeatureKind)
11777 continue;
11779 if (Extension.Features.none())
11780 return Error(ExtLoc, "unsupported architectural extension: " + Name);
11782 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck)
11783 return Error(ExtLoc, "architectural extension '" + Name +
11784 "' is not "
11785 "allowed for the current base architecture");
11787 MCSubtargetInfo &STI = copySTI();
11788 if (EnableFeature) {
11789 STI.SetFeatureBitsTransitively(Extension.Features);
11790 } else {
11791 STI.ClearFeatureBitsTransitively(Extension.Features);
11793 FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
11794 setAvailableFeatures(Features);
11795 return false;
11798 return Error(ExtLoc, "unknown architectural extension: " + Name);
11801 // Define this matcher function after the auto-generated include so we
11802 // have the match class enum definitions.
11803 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
11804 unsigned Kind) {
11805 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
11806 // If the kind is a token for a literal immediate, check if our asm
11807 // operand matches. This is for InstAliases which have a fixed-value
11808 // immediate in the syntax.
11809 switch (Kind) {
11810 default: break;
11811 case MCK__HASH_0:
11812 if (Op.isImm())
11813 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
11814 if (CE->getValue() == 0)
11815 return Match_Success;
11816 break;
11817 case MCK__HASH_8:
11818 if (Op.isImm())
11819 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
11820 if (CE->getValue() == 8)
11821 return Match_Success;
11822 break;
11823 case MCK__HASH_16:
11824 if (Op.isImm())
11825 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
11826 if (CE->getValue() == 16)
11827 return Match_Success;
11828 break;
11829 case MCK_ModImm:
11830 if (Op.isImm()) {
11831 const MCExpr *SOExpr = Op.getImm();
11832 int64_t Value;
11833 if (!SOExpr->evaluateAsAbsolute(Value))
11834 return Match_Success;
11835 assert((Value >= std::numeric_limits<int32_t>::min() &&
11836 Value <= std::numeric_limits<uint32_t>::max()) &&
11837 "expression value must be representable in 32 bits");
11839 break;
11840 case MCK_rGPR:
11841 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
11842 return Match_Success;
11843 return Match_rGPR;
11844 case MCK_GPRPair:
11845 if (Op.isReg() &&
11846 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
11847 return Match_Success;
11848 break;
11850 return Match_InvalidOperand;
11853 bool ARMAsmParser::isMnemonicVPTPredicable(StringRef Mnemonic,
11854 StringRef ExtraToken) {
11855 if (!hasMVE())
11856 return false;
11858 return Mnemonic.startswith("vabav") || Mnemonic.startswith("vaddv") ||
11859 Mnemonic.startswith("vaddlv") || Mnemonic.startswith("vminnmv") ||
11860 Mnemonic.startswith("vminnmav") || Mnemonic.startswith("vminv") ||
11861 Mnemonic.startswith("vminav") || Mnemonic.startswith("vmaxnmv") ||
11862 Mnemonic.startswith("vmaxnmav") || Mnemonic.startswith("vmaxv") ||
11863 Mnemonic.startswith("vmaxav") || Mnemonic.startswith("vmladav") ||
11864 Mnemonic.startswith("vrmlaldavh") || Mnemonic.startswith("vrmlalvh") ||
11865 Mnemonic.startswith("vmlsdav") || Mnemonic.startswith("vmlav") ||
11866 Mnemonic.startswith("vmlaldav") || Mnemonic.startswith("vmlalv") ||
11867 Mnemonic.startswith("vmaxnm") || Mnemonic.startswith("vminnm") ||
11868 Mnemonic.startswith("vmax") || Mnemonic.startswith("vmin") ||
11869 Mnemonic.startswith("vshlc") || Mnemonic.startswith("vmovlt") ||
11870 Mnemonic.startswith("vmovlb") || Mnemonic.startswith("vshll") ||
11871 Mnemonic.startswith("vrshrn") || Mnemonic.startswith("vshrn") ||
11872 Mnemonic.startswith("vqrshrun") || Mnemonic.startswith("vqshrun") ||
11873 Mnemonic.startswith("vqrshrn") || Mnemonic.startswith("vqshrn") ||
11874 Mnemonic.startswith("vbic") || Mnemonic.startswith("vrev64") ||
11875 Mnemonic.startswith("vrev32") || Mnemonic.startswith("vrev16") ||
11876 Mnemonic.startswith("vmvn") || Mnemonic.startswith("veor") ||
11877 Mnemonic.startswith("vorn") || Mnemonic.startswith("vorr") ||
11878 Mnemonic.startswith("vand") || Mnemonic.startswith("vmul") ||
11879 Mnemonic.startswith("vqrdmulh") || Mnemonic.startswith("vqdmulh") ||
11880 Mnemonic.startswith("vsub") || Mnemonic.startswith("vadd") ||
11881 Mnemonic.startswith("vqsub") || Mnemonic.startswith("vqadd") ||
11882 Mnemonic.startswith("vabd") || Mnemonic.startswith("vrhadd") ||
11883 Mnemonic.startswith("vhsub") || Mnemonic.startswith("vhadd") ||
11884 Mnemonic.startswith("vdup") || Mnemonic.startswith("vcls") ||
11885 Mnemonic.startswith("vclz") || Mnemonic.startswith("vneg") ||
11886 Mnemonic.startswith("vabs") || Mnemonic.startswith("vqneg") ||
11887 Mnemonic.startswith("vqabs") ||
11888 (Mnemonic.startswith("vrint") && Mnemonic != "vrintr") ||
11889 Mnemonic.startswith("vcmla") || Mnemonic.startswith("vfma") ||
11890 Mnemonic.startswith("vfms") || Mnemonic.startswith("vcadd") ||
11891 Mnemonic.startswith("vadd") || Mnemonic.startswith("vsub") ||
11892 Mnemonic.startswith("vshl") || Mnemonic.startswith("vqshl") ||
11893 Mnemonic.startswith("vqrshl") || Mnemonic.startswith("vrshl") ||
11894 Mnemonic.startswith("vsri") || Mnemonic.startswith("vsli") ||
11895 Mnemonic.startswith("vrshr") || Mnemonic.startswith("vshr") ||
11896 Mnemonic.startswith("vpsel") || Mnemonic.startswith("vcmp") ||
11897 Mnemonic.startswith("vqdmladh") || Mnemonic.startswith("vqrdmladh") ||
11898 Mnemonic.startswith("vqdmlsdh") || Mnemonic.startswith("vqrdmlsdh") ||
11899 Mnemonic.startswith("vcmul") || Mnemonic.startswith("vrmulh") ||
11900 Mnemonic.startswith("vqmovn") || Mnemonic.startswith("vqmovun") ||
11901 Mnemonic.startswith("vmovnt") || Mnemonic.startswith("vmovnb") ||
11902 Mnemonic.startswith("vmaxa") || Mnemonic.startswith("vmaxnma") ||
11903 Mnemonic.startswith("vhcadd") || Mnemonic.startswith("vadc") ||
11904 Mnemonic.startswith("vsbc") || Mnemonic.startswith("vrshr") ||
11905 Mnemonic.startswith("vshr") || Mnemonic.startswith("vstrb") ||
11906 Mnemonic.startswith("vldrb") ||
11907 (Mnemonic.startswith("vstrh") && Mnemonic != "vstrhi") ||
11908 (Mnemonic.startswith("vldrh") && Mnemonic != "vldrhi") ||
11909 Mnemonic.startswith("vstrw") || Mnemonic.startswith("vldrw") ||
11910 Mnemonic.startswith("vldrd") || Mnemonic.startswith("vstrd") ||
11911 Mnemonic.startswith("vqdmull") || Mnemonic.startswith("vbrsr") ||
11912 Mnemonic.startswith("vfmas") || Mnemonic.startswith("vmlas") ||
11913 Mnemonic.startswith("vmla") || Mnemonic.startswith("vqdmlash") ||
11914 Mnemonic.startswith("vqdmlah") || Mnemonic.startswith("vqrdmlash") ||
11915 Mnemonic.startswith("vqrdmlah") || Mnemonic.startswith("viwdup") ||
11916 Mnemonic.startswith("vdwdup") || Mnemonic.startswith("vidup") ||
11917 Mnemonic.startswith("vddup") || Mnemonic.startswith("vctp") ||
11918 Mnemonic.startswith("vpnot") || Mnemonic.startswith("vbic") ||
11919 Mnemonic.startswith("vrmlsldavh") || Mnemonic.startswith("vmlsldav") ||
11920 Mnemonic.startswith("vcvt") ||
11921 (Mnemonic.startswith("vmov") &&
11922 !(ExtraToken == ".f16" || ExtraToken == ".32" ||
11923 ExtraToken == ".16" || ExtraToken == ".8"));