lib/Target/NVPTX/NVPTXFrameLowering.cpp

   1 //=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the NVPTX implementation of TargetFrameLowering class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "NVPTXFrameLowering.h"
  14 #include "NVPTX.h"
  15 #include "NVPTXRegisterInfo.h"
  16 #include "NVPTXSubtarget.h"
  17 #include "NVPTXTargetMachine.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/CodeGen/MachineFunction.h"
  20 #include "llvm/CodeGen/MachineInstrBuilder.h"
  21 #include "llvm/CodeGen/MachineRegisterInfo.h"
  22 #include "llvm/CodeGen/TargetInstrInfo.h"
  23 #include "llvm/MC/MachineLocation.h"
  24
  25 using namespace llvm;
  26
  27 NVPTXFrameLowering::NVPTXFrameLowering()
  28     : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, Align(8), 0) {}
  29
  30 bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
  31
  32 void NVPTXFrameLowering::emitPrologue(MachineFunction &MF,
  33                                       MachineBasicBlock &MBB) const {
  34   if (MF.getFrameInfo().hasStackObjects()) {
  35     assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
  36     MachineInstr *MI = &MBB.front();
  37     MachineRegisterInfo &MR = MF.getRegInfo();
  38
  39     // This instruction really occurs before first instruction
  40     // in the BB, so giving it no debug location.
  41     DebugLoc dl = DebugLoc();
  42
  43     // Emits
  44     //   mov %SPL, %depot;
  45     //   cvta.local %SP, %SPL;
  46     // for local address accesses in MF.
  47     bool Is64Bit =
  48         static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit();
  49     unsigned CvtaLocalOpcode =
  50         (Is64Bit ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes);
  51     unsigned MovDepotOpcode =
  52         (Is64Bit ? NVPTX::MOV_DEPOT_ADDR_64 : NVPTX::MOV_DEPOT_ADDR);
  53     if (!MR.use_empty(NVPTX::VRFrame)) {
  54       // If %SP is not used, do not bother emitting "cvta.local %SP, %SPL".
  55       MI = BuildMI(MBB, MI, dl,
  56                    MF.getSubtarget().getInstrInfo()->get(CvtaLocalOpcode),
  57                    NVPTX::VRFrame)
  58                .addReg(NVPTX::VRFrameLocal);
  59     }
  60     BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
  61             NVPTX::VRFrameLocal)
  62         .addImm(MF.getFunctionNumber());
  63   }
  64 }
  65
  66 int NVPTXFrameLowering::getFrameIndexReference(const MachineFunction &MF,
  67                                                int FI,
  68                                                unsigned &FrameReg) const {
  69   const MachineFrameInfo &MFI = MF.getFrameInfo();
  70   FrameReg = NVPTX::VRDepot;
  71   return MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
  72 }
  73
  74 void NVPTXFrameLowering::emitEpilogue(MachineFunction &MF,
  75                                       MachineBasicBlock &MBB) const {}
  76
  77 // This function eliminates ADJCALLSTACKDOWN,
  78 // ADJCALLSTACKUP pseudo instructions
  79 MachineBasicBlock::iterator NVPTXFrameLowering::eliminateCallFramePseudoInstr(
  80     MachineFunction &MF, MachineBasicBlock &MBB,
  81     MachineBasicBlock::iterator I) const {
  82   // Simply discard ADJCALLSTACKDOWN,
  83   // ADJCALLSTACKUP instructions.
  84   return MBB.erase(I);
  85 }