lib/Target/RISCV/CMakeLists.txt

   1 set(LLVM_TARGET_DEFINITIONS RISCV.td)
   2
   3 tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
   4 tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
   5 tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
   6 tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
   7 tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
   8 tablegen(LLVM RISCVGenGlobalISel.inc -gen-global-isel)
   9 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
  10 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
  11 tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
  12 tablegen(LLVM RISCVGenRegisterBank.inc -gen-register-bank)
  13 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
  14 tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
  15 tablegen(LLVM RISCVGenSystemOperands.inc -gen-searchable-tables)
  16
  17 add_public_tablegen_target(RISCVCommonTableGen)
  18
  19 add_llvm_target(RISCVCodeGen
  20   RISCVAsmPrinter.cpp
  21   RISCVCallLowering.cpp
  22   RISCVExpandPseudoInsts.cpp
  23   RISCVFrameLowering.cpp
  24   RISCVInstrInfo.cpp
  25   RISCVInstructionSelector.cpp
  26   RISCVISelDAGToDAG.cpp
  27   RISCVISelLowering.cpp
  28   RISCVLegalizerInfo.cpp
  29   RISCVMCInstLower.cpp
  30   RISCVMergeBaseOffset.cpp
  31   RISCVRegisterBankInfo.cpp
  32   RISCVRegisterInfo.cpp
  33   RISCVSubtarget.cpp
  34   RISCVTargetMachine.cpp
  35   RISCVTargetObjectFile.cpp
  36   RISCVTargetTransformInfo.cpp
  37   )
  38
  39 add_subdirectory(AsmParser)
  40 add_subdirectory(Disassembler)
  41 add_subdirectory(MCTargetDesc)
  42 add_subdirectory(TargetInfo)
  43 add_subdirectory(Utils)