lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

   1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// This file provides RISCV-specific target descriptions.
  10 ///
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "RISCVMCTargetDesc.h"
  14 #include "RISCVELFStreamer.h"
  15 #include "RISCVInstPrinter.h"
  16 #include "RISCVMCAsmInfo.h"
  17 #include "RISCVTargetStreamer.h"
  18 #include "TargetInfo/RISCVTargetInfo.h"
  19 #include "Utils/RISCVBaseInfo.h"
  20 #include "llvm/ADT/STLExtras.h"
  21 #include "llvm/CodeGen/Register.h"
  22 #include "llvm/MC/MCAsmInfo.h"
  23 #include "llvm/MC/MCInstrInfo.h"
  24 #include "llvm/MC/MCRegisterInfo.h"
  25 #include "llvm/MC/MCStreamer.h"
  26 #include "llvm/MC/MCSubtargetInfo.h"
  27 #include "llvm/Support/ErrorHandling.h"
  28 #include "llvm/Support/TargetRegistry.h"
  29
  30 #define GET_INSTRINFO_MC_DESC
  31 #include "RISCVGenInstrInfo.inc"
  32
  33 #define GET_REGINFO_MC_DESC
  34 #include "RISCVGenRegisterInfo.inc"
  35
  36 #define GET_SUBTARGETINFO_MC_DESC
  37 #include "RISCVGenSubtargetInfo.inc"
  38
  39 using namespace llvm;
  40
  41 static MCInstrInfo *createRISCVMCInstrInfo() {
  42   MCInstrInfo *X = new MCInstrInfo();
  43   InitRISCVMCInstrInfo(X);
  44   return X;
  45 }
  46
  47 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
  48   MCRegisterInfo *X = new MCRegisterInfo();
  49   InitRISCVMCRegisterInfo(X, RISCV::X1);
  50   return X;
  51 }
  52
  53 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
  54                                        const Triple &TT) {
  55   MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
  56
  57   Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
  58   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
  59   MAI->addInitialFrameState(Inst);
  60
  61   return MAI;
  62 }
  63
  64 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
  65                                                    StringRef CPU, StringRef FS) {
  66   std::string CPUName = CPU;
  67   if (CPUName.empty())
  68     CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
  69   return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
  70 }
  71
  72 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
  73                                                unsigned SyntaxVariant,
  74                                                const MCAsmInfo &MAI,
  75                                                const MCInstrInfo &MII,
  76                                                const MCRegisterInfo &MRI) {
  77   return new RISCVInstPrinter(MAI, MII, MRI);
  78 }
  79
  80 static MCTargetStreamer *
  81 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
  82   const Triple &TT = STI.getTargetTriple();
  83   if (TT.isOSBinFormatELF())
  84     return new RISCVTargetELFStreamer(S, STI);
  85   return nullptr;
  86 }
  87
  88 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
  89                                                       formatted_raw_ostream &OS,
  90                                                       MCInstPrinter *InstPrint,
  91                                                       bool isVerboseAsm) {
  92   return new RISCVTargetAsmStreamer(S, OS);
  93 }
  94
  95 extern "C" void LLVMInitializeRISCVTargetMC() {
  96   for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
  97     TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
  98     TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
  99     TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
 100     TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
 101     TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
 102     TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
 103     TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
 104     TargetRegistry::RegisterObjectTargetStreamer(
 105         *T, createRISCVObjectTargetStreamer);
 106
 107     // Register the asm target streamer.
 108     TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
 109   }
 110 }