lib/Target/Sparc/SparcTargetMachine.cpp

   1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "SparcTargetMachine.h"
  13 #include "LeonPasses.h"
  14 #include "Sparc.h"
  15 #include "SparcTargetObjectFile.h"
  16 #include "TargetInfo/SparcTargetInfo.h"
  17 #include "llvm/CodeGen/Passes.h"
  18 #include "llvm/CodeGen/TargetPassConfig.h"
  19 #include "llvm/IR/LegacyPassManager.h"
  20 #include "llvm/Support/TargetRegistry.h"
  21 using namespace llvm;
  22
  23 extern "C" void LLVMInitializeSparcTarget() {
  24   // Register the target.
  25   RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
  26   RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
  27   RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
  28 }
  29
  30 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
  31   // Sparc is typically big endian, but some are little.
  32   std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
  33   Ret += "-m:e";
  34
  35   // Some ABIs have 32bit pointers.
  36   if (!is64Bit)
  37     Ret += "-p:32:32";
  38
  39   // Alignments for 64 bit integers.
  40   Ret += "-i64:64";
  41
  42   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
  43   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
  44   if (is64Bit)
  45     Ret += "-n32:64";
  46   else
  47     Ret += "-f128:64-n32";
  48
  49   if (is64Bit)
  50     Ret += "-S128";
  51   else
  52     Ret += "-S64";
  53
  54   return Ret;
  55 }
  56
  57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
  58   if (!RM.hasValue())
  59     return Reloc::Static;
  60   return *RM;
  61 }
  62
  63 // Code models. Some only make sense for 64-bit code.
  64 //
  65 // SunCC  Reloc   CodeModel  Constraints
  66 // abs32  Static  Small      text+data+bss linked below 2^32 bytes
  67 // abs44  Static  Medium     text+data+bss linked below 2^44 bytes
  68 // abs64  Static  Large      text smaller than 2^31 bytes
  69 // pic13  PIC_    Small      GOT < 2^13 bytes
  70 // pic32  PIC_    Medium     GOT < 2^32 bytes
  71 //
  72 // All code models require that the text segment is smaller than 2GB.
  73 static CodeModel::Model
  74 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM,
  75                            bool Is64Bit, bool JIT) {
  76   if (CM) {
  77     if (*CM == CodeModel::Tiny)
  78       report_fatal_error("Target does not support the tiny CodeModel", false);
  79     if (*CM == CodeModel::Kernel)
  80       report_fatal_error("Target does not support the kernel CodeModel", false);
  81     return *CM;
  82   }
  83   if (Is64Bit) {
  84     if (JIT)
  85       return CodeModel::Large;
  86     return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
  87   }
  88   return CodeModel::Small;
  89 }
  90
  91 /// Create an ILP32 architecture model
  92 SparcTargetMachine::SparcTargetMachine(
  93     const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
  94     const TargetOptions &Options, Optional<Reloc::Model> RM,
  95     Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
  96     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
  97                         getEffectiveRelocModel(RM),
  98                         getEffectiveSparcCodeModel(
  99                             CM, getEffectiveRelocModel(RM), is64bit, JIT),
 100                         OL),
 101       TLOF(std::make_unique<SparcELFTargetObjectFile>()),
 102       Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
 103   initAsmInfo();
 104 }
 105
 106 SparcTargetMachine::~SparcTargetMachine() {}
 107
 108 const SparcSubtarget *
 109 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
 110   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 111   Attribute FSAttr = F.getFnAttribute("target-features");
 112
 113   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
 114                         ? CPUAttr.getValueAsString().str()
 115                         : TargetCPU;
 116   std::string FS = !FSAttr.hasAttribute(Attribute::None)
 117                        ? FSAttr.getValueAsString().str()
 118                        : TargetFS;
 119
 120   // FIXME: This is related to the code below to reset the target options,
 121   // we need to know whether or not the soft float flag is set on the
 122   // function, so we can enable it as a subtarget feature.
 123   bool softFloat =
 124       F.hasFnAttribute("use-soft-float") &&
 125       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
 126
 127   if (softFloat)
 128     FS += FS.empty() ? "+soft-float" : ",+soft-float";
 129
 130   auto &I = SubtargetMap[CPU + FS];
 131   if (!I) {
 132     // This needs to be done before we create a new subtarget since any
 133     // creation will depend on the TM and the code generation flags on the
 134     // function that reside in TargetOptions.
 135     resetTargetOptions(F);
 136     I = std::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
 137                                           this->is64Bit);
 138   }
 139   return I.get();
 140 }
 141
 142 namespace {
 143 /// Sparc Code Generator Pass Configuration Options.
 144 class SparcPassConfig : public TargetPassConfig {
 145 public:
 146   SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
 147     : TargetPassConfig(TM, PM) {}
 148
 149   SparcTargetMachine &getSparcTargetMachine() const {
 150     return getTM<SparcTargetMachine>();
 151   }
 152
 153   void addIRPasses() override;
 154   bool addInstSelector() override;
 155   void addPreEmitPass() override;
 156 };
 157 } // namespace
 158
 159 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
 160   return new SparcPassConfig(*this, PM);
 161 }
 162
 163 void SparcPassConfig::addIRPasses() {
 164   addPass(createAtomicExpandPass());
 165
 166   TargetPassConfig::addIRPasses();
 167 }
 168
 169 bool SparcPassConfig::addInstSelector() {
 170   addPass(createSparcISelDag(getSparcTargetMachine()));
 171   return false;
 172 }
 173
 174 void SparcPassConfig::addPreEmitPass(){
 175   addPass(createSparcDelaySlotFillerPass());
 176
 177   if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
 178   {
 179     addPass(new InsertNOPLoad());
 180   }
 181   if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
 182     addPass(new DetectRoundChange());
 183   }
 184   if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
 185   {
 186     addPass(new FixAllFDIVSQRT());
 187   }
 188 }
 189
 190 void SparcV8TargetMachine::anchor() { }
 191
 192 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
 193                                            StringRef CPU, StringRef FS,
 194                                            const TargetOptions &Options,
 195                                            Optional<Reloc::Model> RM,
 196                                            Optional<CodeModel::Model> CM,
 197                                            CodeGenOpt::Level OL, bool JIT)
 198     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
 199
 200 void SparcV9TargetMachine::anchor() { }
 201
 202 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
 203                                            StringRef CPU, StringRef FS,
 204                                            const TargetOptions &Options,
 205                                            Optional<Reloc::Model> RM,
 206                                            Optional<CodeModel::Model> CM,
 207                                            CodeGenOpt::Level OL, bool JIT)
 208     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
 209
 210 void SparcelTargetMachine::anchor() {}
 211
 212 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
 213                                            StringRef CPU, StringRef FS,
 214                                            const TargetOptions &Options,
 215                                            Optional<Reloc::Model> RM,
 216                                            Optional<CodeModel::Model> CM,
 217                                            CodeGenOpt::Level OL, bool JIT)
 218     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}