test/MC/AArch64/SVE/rdffrs-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
   2
   3
   4 // --------------------------------------------------------------------------//
   5 // No unpredicated form
   6
   7 rdffrs   p0.b
   8 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
   9 // CHECK: rdffrs   p0.b
  10 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  11
  12
  13 // --------------------------------------------------------------------------//
  14 // Invalid element widths
  15
  16 rdffrs   p0.h, p0/z
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  18 // CHECK: rdffrs   p0.h, p0/z
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 rdffrs   p0.s, p0/z
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  23 // CHECK: rdffrs   p0.s, p0/z
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 rdffrs   p0.d, p0/z
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
  28 // CHECK: rdffrs   p0.d, p0/z
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30