[InstCombine] Signed saturation tests. NFC
[llvm-complete.git] / test / MC / Disassembler / AMDGPU / dpp_vi.txt
blob74ce47aaf76d37b29b883145f62e4a8dea9ad73d
1 # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x58,0x00,0xff]
4 0xfa 0x02 0x00 0x7e 0x00 0x58 0x00 0xff
6 # VI: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x01,0xff]
7 0xfa 0x02 0x00 0x7e 0x00 0x01 0x01 0xff
9 # VI: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x1f,0x01,0xff]
10 0xfa 0x02 0x00 0x7e 0x00 0x1f 0x01 0xff
12 # VI: v_mov_b32_dpp v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x2c,0x01,0xff]
13 0xfa 0x02 0x00 0x7e 0x00 0x2c 0x01 0xff
15 # VI: v_mov_b32_dpp v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x30,0x01,0xff]
16 0xfa 0x02 0x00 0x7e 0x00 0x30 0x01 0xff
18 # VI: v_mov_b32_dpp v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x34,0x01,0xff]
19 0xfa 0x02 0x00 0x7e 0x00 0x34 0x01 0xff
21 # VI: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x38,0x01,0xff]
22 0xfa 0x02 0x00 0x7e 0x00 0x38 0x01 0xff
24 # VI: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x3c,0x01,0xff]
25 0xfa 0x02 0x00 0x7e 0x00 0x3c 0x01 0xff
27 # VI: v_mov_b32_dpp v0, v0 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x40,0x01,0xff]
28 0xfa 0x02 0x00 0x7e 0x00 0x40 0x01 0xff
30 # VI: v_mov_b32_dpp v0, v0 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x41,0x01,0xff]
31 0xfa 0x02 0x00 0x7e 0x00 0x41 0x01 0xff
33 # VI: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
34 0xfa 0x02 0x00 0x7e 0x00 0x42 0x01 0xff
36 # VI: v_mov_b32_dpp v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x43,0x01,0xff]
37 0xfa 0x02 0x00 0x7e 0x00 0x43 0x01 0xff
39 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
40 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xa1
42 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xaf]
43 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xaf
45 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xf1]
46 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xf1
48 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
49 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xff
51 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xa1]
52 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xa1
54 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
55 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xaf
57 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
58 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xf1
60 # VI: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
61 0xfa 0x0e 0x00 0x7e 0x00 0x01 0x09 0xa1
63 # VI: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
64 0xfa 0x36 0x00 0x7e 0x00 0x01 0x09 0xa1
66 # VI: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
67 0xfa 0x52 0x00 0x7e 0x00 0x01 0x09 0xa1
69 # VI: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
70 0xfa 0x00 0x00 0x02 0x00 0x01 0x09 0xa1
72 # VI: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
73 0xfa 0x00 0x00 0x14 0x00 0x01 0x09 0xa1
75 # VI: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
76 0xfa 0x00 0x00 0x26 0x00 0x01 0x09 0xa1
78 # VI: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
79 0xfa 0x00 0x00 0x02 0x00 0x01 0x19 0xa1
81 # VI: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
82 0xfa 0x00 0x00 0x02 0x00 0x01 0x89 0xa1
84 # VI: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
85 0xfa 0x00 0x00 0x02 0x00 0x01 0x99 0xa1
87 # VI: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
88 0xfa 0x00 0x00 0x02 0x00 0x01 0x69 0xa1
90 # VI: v_mac_f32_dpp v76, v76, v114  quad_perm:[2,3,0,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xe4,0x98,0x2c,0x4c,0x4e,0x00,0xff]
91 0xfa 0xe4 0x98 0x2c 0x4c 0x4e 0x00 0xff
93 # VI: v_mac_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x46,0x02,0x01,0x09,0xa1]
94 0xfa 0x06 0x02 0x46 0x02 0x01 0x09 0xa1
96 # VI: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
97 0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00
99 # VI: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00]
100 0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00