test/MC/Disassembler/AMDGPU/xdl-insts-gfx1011-gfx1012.txt

   1 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx1011 -disassemble -show-encoding < %s | FileCheck %s
   2 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx1012 -disassemble -show-encoding < %s | FileCheck %s
   3
   4 # CHECK: v_dot2c_f32_f16_e32 v5, v1, v2  ; encoding: [0x01,0x05,0x0a,0x04]
   5 0x01,0x05,0x0a,0x04
   6
   7 # CHECK: v_dot2c_f32_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x05]
   8 0x01,0x05,0xfe,0x05
   9
  10 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00]
  11 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00
  12
  13 # CHECK: v_dot2c_f32_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00]
  14 0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00
  15
  16 # CHECK: v_dot2c_f32_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00]
  17 0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00
  18
  19 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00]
  20 0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00
  21
  22 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00]
  23 0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00
  24
  25 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00]
  26 0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00
  27
  28 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00]
  29 0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00
  30
  31 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00]
  32 0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00
  33
  34 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00]
  35 0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00
  36
  37 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00]
  38 0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00
  39
  40 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00]
  41 0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00
  42
  43 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00]
  44 0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00
  45
  46 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00]
  47 0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00
  48
  49 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10]
  50 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10
  51
  52 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30]
  53 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30
  54
  55 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
  56 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0
  57
  58 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
  59 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0
  60
  61 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01]
  62 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01
  63
  64 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
  65 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03
  66
  67 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
  68 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f
  69
  70 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
  71 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f
  72
  73 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
  74 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00
  75
  76 # CHECK: v_dot2c_f32_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
  77 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00
  78
  79 # CHECK: v_dot2c_f32_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
  80 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00
  81
  82 # CHECK: v_dot2c_f32_f16_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00]
  83 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00
  84
  85 # CHECK: v_dot2c_f32_f16_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00]
  86 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00
  87
  88 # CHECK: v_dot4c_i32_i8_e32 v5, v1, v2   ; encoding: [0x01,0x05,0x0a,0x1a]
  89 0x01,0x05,0x0a,0x1a
  90
  91 # CHECK: v_dot4c_i32_i8_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x1b]
  92 0x01,0x05,0xfe,0x1b
  93
  94 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00]
  95 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00
  96
  97 # CHECK: v_dot4c_i32_i8_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00]
  98 0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00
  99
 100 # CHECK: v_dot4c_i32_i8_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00]
 101 0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00
 102
 103 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00]
 104 0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00
 105
 106 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00]
 107 0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00
 108
 109 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00]
 110 0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00
 111
 112 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00]
 113 0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00
 114
 115 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00]
 116 0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00
 117
 118 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00]
 119 0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00
 120
 121 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00]
 122 0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00
 123
 124 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00]
 125 0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00
 126
 127 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00]
 128 0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00
 129
 130 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00]
 131 0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00
 132
 133 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10]
 134 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10
 135
 136 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30]
 137 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30
 138
 139 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
 140 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0
 141
 142 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
 143 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0
 144
 145 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01]
 146 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01
 147
 148 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
 149 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03
 150
 151 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 152 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f
 153
 154 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 155 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f
 156
 157 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
 158 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00