1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -instsimplify -S | FileCheck %s
4 define i8 @and0(i8 %x) {
12 define <2 x i8> @and0_vec_undef_elt(<2 x i8> %x) {
13 ; CHECK-LABEL: @and0_vec_undef_elt(
14 ; CHECK-NEXT: ret <2 x i8> zeroinitializer
16 %r = and <2 x i8> %x, <i8 undef, i8 0>
20 ; add nsw (xor X, signbit), signbit --> X
22 define <2 x i32> @add_nsw_signbit(<2 x i32> %x) {
23 ; CHECK-LABEL: @add_nsw_signbit(
24 ; CHECK-NEXT: ret <2 x i32> [[X:%.*]]
26 %y = xor <2 x i32> %x, <i32 -2147483648, i32 -2147483648>
27 %z = add nsw <2 x i32> %y, <i32 -2147483648, i32 -2147483648>
31 ; Undef elements in either constant vector are ok.
33 define <2 x i32> @add_nsw_signbit_undef(<2 x i32> %x) {
34 ; CHECK-LABEL: @add_nsw_signbit_undef(
35 ; CHECK-NEXT: ret <2 x i32> [[X:%.*]]
37 %y = xor <2 x i32> %x, <i32 undef, i32 -2147483648>
38 %z = add nsw <2 x i32> %y, <i32 -2147483648, i32 undef>
42 ; add nuw (xor X, signbit), signbit --> X
44 define <2 x i5> @add_nuw_signbit(<2 x i5> %x) {
45 ; CHECK-LABEL: @add_nuw_signbit(
46 ; CHECK-NEXT: ret <2 x i5> [[X:%.*]]
48 %y = xor <2 x i5> %x, <i5 -16, i5 -16>
49 %z = add nuw <2 x i5> %y, <i5 -16, i5 -16>
53 ; Undef elements in either constant vector are ok.
55 define <2 x i5> @add_nuw_signbit_undef(<2 x i5> %x) {
56 ; CHECK-LABEL: @add_nuw_signbit_undef(
57 ; CHECK-NEXT: ret <2 x i5> [[X:%.*]]
59 %y = xor <2 x i5> %x, <i5 -16, i5 undef>
60 %z = add nuw <2 x i5> %y, <i5 undef, i5 -16>
64 define i64 @pow2(i32 %x) {
66 ; CHECK-NEXT: [[NEGX:%.*]] = sub i32 0, [[X:%.*]]
67 ; CHECK-NEXT: [[X2:%.*]] = and i32 [[X]], [[NEGX]]
68 ; CHECK-NEXT: [[E:%.*]] = zext i32 [[X2]] to i64
69 ; CHECK-NEXT: ret i64 [[E]]
72 %x2 = and i32 %x, %negx
73 %e = zext i32 %x2 to i64
75 %e2 = and i64 %e, %nege
79 define i64 @pow2b(i32 %x) {
80 ; CHECK-LABEL: @pow2b(
81 ; CHECK-NEXT: [[SH:%.*]] = shl i32 2, [[X:%.*]]
82 ; CHECK-NEXT: [[E:%.*]] = zext i32 [[SH]] to i64
83 ; CHECK-NEXT: ret i64 [[E]]
86 %e = zext i32 %sh to i64
88 %e2 = and i64 %e, %nege
92 ; Power-of-2-or-zero value has no bits in common with its decrement.
94 define i32 @pow2_decrement(i32 %p) {
95 ; CHECK-LABEL: @pow2_decrement(
96 ; CHECK-NEXT: ret i32 0
104 define <2 x i32> @pow2_decrement_commute_vec(<2 x i32> %p) {
105 ; CHECK-LABEL: @pow2_decrement_commute_vec(
106 ; CHECK-NEXT: ret <2 x i32> zeroinitializer
108 %x = and <2 x i32> %p, <i32 2048, i32 2048>
109 %a = add <2 x i32> %x, <i32 -1, i32 -1>
110 %r = and <2 x i32> %x, %a
114 define i1 @and_of_icmps0(i32 %b) {
115 ; CHECK-LABEL: @and_of_icmps0(
116 ; CHECK-NEXT: ret i1 false
119 %2 = icmp ult i32 %1, 4
120 %cmp3 = icmp sgt i32 %b, 2
121 %cmp = and i1 %2, %cmp3
125 define <2 x i1> @and_of_icmps0_vec(<2 x i32> %b) {
126 ; CHECK-LABEL: @and_of_icmps0_vec(
127 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
129 %1 = add <2 x i32> %b, <i32 2, i32 2>
130 %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
131 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
132 %cmp = and <2 x i1> %2, %cmp3
136 define i1 @and_of_icmps1(i32 %b) {
137 ; CHECK-LABEL: @and_of_icmps1(
138 ; CHECK-NEXT: ret i1 false
140 %1 = add nsw i32 %b, 2
141 %2 = icmp slt i32 %1, 4
142 %cmp3 = icmp sgt i32 %b, 2
143 %cmp = and i1 %2, %cmp3
147 define <2 x i1> @and_of_icmps1_vec(<2 x i32> %b) {
148 ; CHECK-LABEL: @and_of_icmps1_vec(
149 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
151 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
152 %2 = icmp slt <2 x i32> %1, <i32 4, i32 4>
153 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
154 %cmp = and <2 x i1> %2, %cmp3
158 define i1 @and_of_icmps2(i32 %b) {
159 ; CHECK-LABEL: @and_of_icmps2(
160 ; CHECK-NEXT: ret i1 false
163 %2 = icmp ule i32 %1, 3
164 %cmp3 = icmp sgt i32 %b, 2
165 %cmp = and i1 %2, %cmp3
169 define <2 x i1> @and_of_icmps2_vec(<2 x i32> %b) {
170 ; CHECK-LABEL: @and_of_icmps2_vec(
171 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
173 %1 = add <2 x i32> %b, <i32 2, i32 2>
174 %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
175 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
176 %cmp = and <2 x i1> %2, %cmp3
180 define i1 @and_of_icmps3(i32 %b) {
181 ; CHECK-LABEL: @and_of_icmps3(
182 ; CHECK-NEXT: ret i1 false
184 %1 = add nsw i32 %b, 2
185 %2 = icmp sle i32 %1, 3
186 %cmp3 = icmp sgt i32 %b, 2
187 %cmp = and i1 %2, %cmp3
191 define <2 x i1> @and_of_icmps3_vec(<2 x i32> %b) {
192 ; CHECK-LABEL: @and_of_icmps3_vec(
193 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
195 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
196 %2 = icmp sle <2 x i32> %1, <i32 3, i32 3>
197 %cmp3 = icmp sgt <2 x i32> %b, <i32 2, i32 2>
198 %cmp = and <2 x i1> %2, %cmp3
202 define i1 @and_of_icmps4(i32 %b) {
203 ; CHECK-LABEL: @and_of_icmps4(
204 ; CHECK-NEXT: ret i1 false
206 %1 = add nuw i32 %b, 2
207 %2 = icmp ult i32 %1, 4
208 %cmp3 = icmp ugt i32 %b, 2
209 %cmp = and i1 %2, %cmp3
213 define <2 x i1> @and_of_icmps4_vec(<2 x i32> %b) {
214 ; CHECK-LABEL: @and_of_icmps4_vec(
215 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
217 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
218 %2 = icmp ult <2 x i32> %1, <i32 4, i32 4>
219 %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
220 %cmp = and <2 x i1> %2, %cmp3
224 define i1 @and_of_icmps5(i32 %b) {
225 ; CHECK-LABEL: @and_of_icmps5(
226 ; CHECK-NEXT: ret i1 false
228 %1 = add nuw i32 %b, 2
229 %2 = icmp ule i32 %1, 3
230 %cmp3 = icmp ugt i32 %b, 2
231 %cmp = and i1 %2, %cmp3
235 define <2 x i1> @and_of_icmps5_vec(<2 x i32> %b) {
236 ; CHECK-LABEL: @and_of_icmps5_vec(
237 ; CHECK-NEXT: ret <2 x i1> zeroinitializer
239 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
240 %2 = icmp ule <2 x i32> %1, <i32 3, i32 3>
241 %cmp3 = icmp ugt <2 x i32> %b, <i32 2, i32 2>
242 %cmp = and <2 x i1> %2, %cmp3
246 define i1 @or_of_icmps0(i32 %b) {
247 ; CHECK-LABEL: @or_of_icmps0(
248 ; CHECK-NEXT: ret i1 true
251 %2 = icmp uge i32 %1, 4
252 %cmp3 = icmp sle i32 %b, 2
253 %cmp = or i1 %2, %cmp3
257 define <2 x i1> @or_of_icmps0_vec(<2 x i32> %b) {
258 ; CHECK-LABEL: @or_of_icmps0_vec(
259 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
261 %1 = add <2 x i32> %b, <i32 2, i32 2>
262 %2 = icmp uge <2 x i32> %1, <i32 4, i32 4>
263 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
264 %cmp = or <2 x i1> %2, %cmp3
268 define i1 @or_of_icmps1(i32 %b) {
269 ; CHECK-LABEL: @or_of_icmps1(
270 ; CHECK-NEXT: ret i1 true
272 %1 = add nsw i32 %b, 2
273 %2 = icmp sge i32 %1, 4
274 %cmp3 = icmp sle i32 %b, 2
275 %cmp = or i1 %2, %cmp3
279 define <2 x i1> @or_of_icmps1_vec(<2 x i32> %b) {
280 ; CHECK-LABEL: @or_of_icmps1_vec(
281 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
283 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
284 %2 = icmp sge <2 x i32> %1, <i32 4, i32 4>
285 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
286 %cmp = or <2 x i1> %2, %cmp3
290 define i1 @or_of_icmps2(i32 %b) {
291 ; CHECK-LABEL: @or_of_icmps2(
292 ; CHECK-NEXT: ret i1 true
295 %2 = icmp ugt i32 %1, 3
296 %cmp3 = icmp sle i32 %b, 2
297 %cmp = or i1 %2, %cmp3
301 define <2 x i1> @or_of_icmps2_vec(<2 x i32> %b) {
302 ; CHECK-LABEL: @or_of_icmps2_vec(
303 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
305 %1 = add <2 x i32> %b, <i32 2, i32 2>
306 %2 = icmp ugt <2 x i32> %1, <i32 3, i32 3>
307 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
308 %cmp = or <2 x i1> %2, %cmp3
312 define i1 @or_of_icmps3(i32 %b) {
313 ; CHECK-LABEL: @or_of_icmps3(
314 ; CHECK-NEXT: ret i1 true
316 %1 = add nsw i32 %b, 2
317 %2 = icmp sgt i32 %1, 3
318 %cmp3 = icmp sle i32 %b, 2
319 %cmp = or i1 %2, %cmp3
323 define <2 x i1> @or_of_icmps3_vec(<2 x i32> %b) {
324 ; CHECK-LABEL: @or_of_icmps3_vec(
325 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
327 %1 = add nsw <2 x i32> %b, <i32 2, i32 2>
328 %2 = icmp sgt <2 x i32> %1, <i32 3, i32 3>
329 %cmp3 = icmp sle <2 x i32> %b, <i32 2, i32 2>
330 %cmp = or <2 x i1> %2, %cmp3
334 define i1 @or_of_icmps4(i32 %b) {
335 ; CHECK-LABEL: @or_of_icmps4(
336 ; CHECK-NEXT: ret i1 true
338 %1 = add nuw i32 %b, 2
339 %2 = icmp uge i32 %1, 4
340 %cmp3 = icmp ule i32 %b, 2
341 %cmp = or i1 %2, %cmp3
345 define <2 x i1> @or_of_icmps4_vec(<2 x i32> %b) {
346 ; CHECK-LABEL: @or_of_icmps4_vec(
347 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
349 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
350 %2 = icmp uge <2 x i32> %1, <i32 4, i32 4>
351 %cmp3 = icmp ule <2 x i32> %b, <i32 2, i32 2>
352 %cmp = or <2 x i1> %2, %cmp3
356 define i1 @or_of_icmps5(i32 %b) {
357 ; CHECK-LABEL: @or_of_icmps5(
358 ; CHECK-NEXT: ret i1 true
360 %1 = add nuw i32 %b, 2
361 %2 = icmp ugt i32 %1, 3
362 %cmp3 = icmp ule i32 %b, 2
363 %cmp = or i1 %2, %cmp3
367 define <2 x i1> @or_of_icmps5_vec(<2 x i32> %b) {
368 ; CHECK-LABEL: @or_of_icmps5_vec(
369 ; CHECK-NEXT: ret <2 x i1> <i1 true, i1 true>
371 %1 = add nuw <2 x i32> %b, <i32 2, i32 2>
372 %2 = icmp ugt <2 x i32> %1, <i32 3, i32 3>
373 %cmp3 = icmp ule <2 x i32> %b, <i32 2, i32 2>
374 %cmp = or <2 x i1> %2, %cmp3
378 define i32 @neg_nuw(i32 %x) {
379 ; CHECK-LABEL: @neg_nuw(
380 ; CHECK-NEXT: ret i32 0
382 %neg = sub nuw i32 0, %x
386 define i1 @and_icmp1(i32 %x, i32 %y) {
387 ; CHECK-LABEL: @and_icmp1(
388 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]]
389 ; CHECK-NEXT: ret i1 [[TMP1]]
391 %1 = icmp ult i32 %x, %y
392 %2 = icmp ne i32 %y, 0
397 define i1 @and_icmp2(i32 %x, i32 %y) {
398 ; CHECK-LABEL: @and_icmp2(
399 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X:%.*]], [[Y:%.*]]
400 ; CHECK-NEXT: ret i1 [[TMP1]]
402 %1 = icmp ugt i32 %x, %y
403 %2 = icmp ne i32 %x, 0
408 define i1 @and_icmp3(i32 %x, i32 %y) {
409 ; CHECK-LABEL: @and_icmp3(
410 ; CHECK-NEXT: ret i1 false
412 %1 = icmp ult i32 %x, %y
413 %2 = icmp eq i32 %y, 0
418 define i1 @and_icmp4(i32 %x, i32 %y) {
419 ; CHECK-LABEL: @and_icmp4(
420 ; CHECK-NEXT: ret i1 false
422 %1 = icmp ugt i32 %x, %y
423 %2 = icmp eq i32 %x, 0
428 define i1 @or_icmp1(i32 %x, i32 %y) {
429 ; CHECK-LABEL: @or_icmp1(
430 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[Y:%.*]], 0
431 ; CHECK-NEXT: ret i1 [[TMP1]]
433 %1 = icmp ult i32 %x, %y
434 %2 = icmp ne i32 %y, 0
439 define i1 @or_icmp2(i32 %x, i32 %y) {
440 ; CHECK-LABEL: @or_icmp2(
441 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X:%.*]], 0
442 ; CHECK-NEXT: ret i1 [[TMP1]]
444 %1 = icmp ugt i32 %x, %y
445 %2 = icmp ne i32 %x, 0
450 define i1 @or_icmp3(i32 %x, i32 %y) {
451 ; CHECK-LABEL: @or_icmp3(
452 ; CHECK-NEXT: ret i1 true
454 %1 = icmp uge i32 %x, %y
455 %2 = icmp ne i32 %y, 0
460 define i1 @or_icmp4(i32 %x, i32 %y) {
461 ; CHECK-LABEL: @or_icmp4(
462 ; CHECK-NEXT: ret i1 true
464 %1 = icmp ule i32 %x, %y
465 %2 = icmp ne i32 %x, 0
470 define i1 @or_icmp5(i32 %x, i32 %y) {
471 ; CHECK-LABEL: @or_icmp5(
472 ; CHECK-NEXT: [[TMP1:%.*]] = icmp uge i32 [[X:%.*]], [[Y:%.*]]
473 ; CHECK-NEXT: ret i1 [[TMP1]]
475 %1 = icmp uge i32 %x, %y
476 %2 = icmp eq i32 %y, 0
481 define i1 @or_icmp6(i32 %x, i32 %y) {
482 ; CHECK-LABEL: @or_icmp6(
483 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
484 ; CHECK-NEXT: ret i1 [[TMP1]]
486 %1 = icmp ule i32 %x, %y
487 %2 = icmp eq i32 %x, 0
492 ; PR27869 - Look through casts to eliminate cmps and bitwise logic.
494 define i32 @and_of_zexted_icmps(i32 %i) {
495 ; CHECK-LABEL: @and_of_zexted_icmps(
496 ; CHECK-NEXT: ret i32 0
498 %cmp0 = icmp eq i32 %i, 0
499 %conv0 = zext i1 %cmp0 to i32
500 %cmp1 = icmp ugt i32 %i, 4
501 %conv1 = zext i1 %cmp1 to i32
502 %and = and i32 %conv0, %conv1
506 ; Make sure vectors work too.
508 define <4 x i32> @and_of_zexted_icmps_vec(<4 x i32> %i) {
509 ; CHECK-LABEL: @and_of_zexted_icmps_vec(
510 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
512 %cmp0 = icmp eq <4 x i32> %i, zeroinitializer
513 %conv0 = zext <4 x i1> %cmp0 to <4 x i32>
514 %cmp1 = icmp slt <4 x i32> %i, zeroinitializer
515 %conv1 = zext <4 x i1> %cmp1 to <4 x i32>
516 %and = and <4 x i32> %conv0, %conv1
520 ; Try a different cast and weird types.
522 define i5 @and_of_sexted_icmps(i3 %i) {
523 ; CHECK-LABEL: @and_of_sexted_icmps(
524 ; CHECK-NEXT: ret i5 0
526 %cmp0 = icmp eq i3 %i, 0
527 %conv0 = sext i1 %cmp0 to i5
528 %cmp1 = icmp ugt i3 %i, 1
529 %conv1 = sext i1 %cmp1 to i5
530 %and = and i5 %conv0, %conv1
534 ; Try a different cast and weird vector types.
536 define i3 @and_of_bitcast_icmps_vec(<3 x i65> %i) {
537 ; CHECK-LABEL: @and_of_bitcast_icmps_vec(
538 ; CHECK-NEXT: ret i3 0
540 %cmp0 = icmp sgt <3 x i65> %i, zeroinitializer
541 %conv0 = bitcast <3 x i1> %cmp0 to i3
542 %cmp1 = icmp slt <3 x i65> %i, zeroinitializer
543 %conv1 = bitcast <3 x i1> %cmp1 to i3
544 %and = and i3 %conv0, %conv1
548 ; We can't do this if the casts are different.
550 define i16 @and_of_different_cast_icmps(i8 %i) {
551 ; CHECK-LABEL: @and_of_different_cast_icmps(
552 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i8 [[I:%.*]], 0
553 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
554 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[I]], 1
555 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
556 ; CHECK-NEXT: [[AND:%.*]] = and i16 [[CONV0]], [[CONV1]]
557 ; CHECK-NEXT: ret i16 [[AND]]
559 %cmp0 = icmp eq i8 %i, 0
560 %conv0 = zext i1 %cmp0 to i16
561 %cmp1 = icmp eq i8 %i, 1
562 %conv1 = sext i1 %cmp1 to i16
563 %and = and i16 %conv0, %conv1
567 define <2 x i3> @and_of_different_cast_icmps_vec(<2 x i8> %i, <2 x i16> %j) {
568 ; CHECK-LABEL: @and_of_different_cast_icmps_vec(
569 ; CHECK-NEXT: [[CMP0:%.*]] = icmp eq <2 x i8> [[I:%.*]], zeroinitializer
570 ; CHECK-NEXT: [[CONV0:%.*]] = zext <2 x i1> [[CMP0]] to <2 x i3>
571 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <2 x i16> [[J:%.*]], <i16 1, i16 1>
572 ; CHECK-NEXT: [[CONV1:%.*]] = zext <2 x i1> [[CMP1]] to <2 x i3>
573 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i3> [[CONV0]], [[CONV1]]
574 ; CHECK-NEXT: ret <2 x i3> [[AND]]
576 %cmp0 = icmp eq <2 x i8> %i, zeroinitializer
577 %conv0 = zext <2 x i1> %cmp0 to <2 x i3>
578 %cmp1 = icmp ugt <2 x i16> %j, <i16 1, i16 1>
579 %conv1 = zext <2 x i1> %cmp1 to <2 x i3>
580 %and = and <2 x i3> %conv0, %conv1
584 define i32 @or_of_zexted_icmps(i32 %i) {
585 ; CHECK-LABEL: @or_of_zexted_icmps(
586 ; CHECK-NEXT: ret i32 1
588 %cmp0 = icmp ne i32 %i, 0
589 %conv0 = zext i1 %cmp0 to i32
590 %cmp1 = icmp uge i32 4, %i
591 %conv1 = zext i1 %cmp1 to i32
592 %or = or i32 %conv0, %conv1
596 ; Try a different cast and weird vector types.
598 define i3 @or_of_bitcast_icmps_vec(<3 x i65> %i) {
599 ; CHECK-LABEL: @or_of_bitcast_icmps_vec(
600 ; CHECK-NEXT: ret i3 bitcast (<3 x i1> <i1 true, i1 true, i1 true> to i3)
602 %cmp0 = icmp sge <3 x i65> %i, zeroinitializer
603 %conv0 = bitcast <3 x i1> %cmp0 to i3
604 %cmp1 = icmp slt <3 x i65> %i, zeroinitializer
605 %conv1 = bitcast <3 x i1> %cmp1 to i3
606 %or = or i3 %conv0, %conv1
610 ; We can't simplify if the casts are different.
612 define i16 @or_of_different_cast_icmps(i8 %i) {
613 ; CHECK-LABEL: @or_of_different_cast_icmps(
614 ; CHECK-NEXT: [[CMP0:%.*]] = icmp ne i8 [[I:%.*]], 0
615 ; CHECK-NEXT: [[CONV0:%.*]] = zext i1 [[CMP0]] to i16
616 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i8 [[I]], 1
617 ; CHECK-NEXT: [[CONV1:%.*]] = sext i1 [[CMP1]] to i16
618 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[CONV0]], [[CONV1]]
619 ; CHECK-NEXT: ret i16 [[OR]]
621 %cmp0 = icmp ne i8 %i, 0
622 %conv0 = zext i1 %cmp0 to i16
623 %cmp1 = icmp ne i8 %i, 1
624 %conv1 = sext i1 %cmp1 to i16
625 %or = or i16 %conv0, %conv1
629 ; (A & ~B) | (A ^ B) -> A ^ B
631 define i32 @test43(i32 %a, i32 %b) {
632 ; CHECK-LABEL: @test43(
633 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
634 ; CHECK-NEXT: ret i32 [[XOR]]
636 %neg = xor i32 %b, -1
637 %and = and i32 %a, %neg
638 %xor = xor i32 %a, %b
639 %or = or i32 %and, %xor
643 define i32 @test43_commuted_and(i32 %a, i32 %b) {
644 ; CHECK-LABEL: @test43_commuted_and(
645 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
646 ; CHECK-NEXT: ret i32 [[XOR]]
648 %neg = xor i32 %b, -1
649 %and = and i32 %neg, %a
650 %xor = xor i32 %a, %b
651 %or = or i32 %and, %xor
655 ; Commute operands of the 'or'.
656 ; (A ^ B) | (A & ~B) -> A ^ B
658 define i32 @test44(i32 %a, i32 %b) {
659 ; CHECK-LABEL: @test44(
660 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
661 ; CHECK-NEXT: ret i32 [[XOR]]
663 %xor = xor i32 %a, %b
664 %neg = xor i32 %b, -1
665 %and = and i32 %a, %neg
666 %or = or i32 %xor, %and
670 define i32 @test44_commuted_and(i32 %a, i32 %b) {
671 ; CHECK-LABEL: @test44_commuted_and(
672 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
673 ; CHECK-NEXT: ret i32 [[XOR]]
675 %xor = xor i32 %a, %b
676 %neg = xor i32 %b, -1
677 %and = and i32 %neg, %a
678 %or = or i32 %xor, %and
682 ; (~A & ~B) | (~A ^ B) -> ~A ^ B
684 define i32 @test45(i32 %a, i32 %b) {
685 ; CHECK-LABEL: @test45(
686 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
687 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
688 ; CHECK-NEXT: ret i32 [[XOR]]
690 %nega = xor i32 %a, -1
691 %negb = xor i32 %b, -1
692 %and = and i32 %nega, %negb
693 %xor = xor i32 %a, %negb
694 %or = or i32 %and, %xor
698 define i32 @test45_commuted_and(i32 %a, i32 %b) {
699 ; CHECK-LABEL: @test45_commuted_and(
700 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
701 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
702 ; CHECK-NEXT: ret i32 [[XOR]]
704 %nega = xor i32 %a, -1
705 %negb = xor i32 %b, -1
706 %and = and i32 %negb, %nega
707 %xor = xor i32 %a, %negb
708 %or = or i32 %and, %xor
712 ; Commute operands of the 'or'.
713 ; (~A ^ B) | (~A & ~B) -> ~A ^ B
715 define i32 @test46(i32 %a, i32 %b) {
716 ; CHECK-LABEL: @test46(
717 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
718 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
719 ; CHECK-NEXT: ret i32 [[XOR]]
721 %nega = xor i32 %a, -1
722 %negb = xor i32 %b, -1
723 %and = and i32 %nega, %negb
724 %xor = xor i32 %a, %negb
725 %or = or i32 %xor, %and
729 ; (~A & ~B) | (~A ^ B) -> ~A ^ B
731 define i32 @test46_commuted_and(i32 %a, i32 %b) {
732 ; CHECK-LABEL: @test46_commuted_and(
733 ; CHECK-NEXT: [[NEGB:%.*]] = xor i32 [[B:%.*]], -1
734 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
735 ; CHECK-NEXT: ret i32 [[XOR]]
737 %nega = xor i32 %a, -1
738 %negb = xor i32 %b, -1
739 %and = and i32 %negb, %nega
740 %xor = xor i32 %a, %negb
741 %or = or i32 %xor, %and
745 ; (~A ^ B) | (A & B) -> ~A ^ B
747 define i32 @test47(i32 %a, i32 %b) {
748 ; CHECK-LABEL: @test47(
749 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
750 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
751 ; CHECK-NEXT: ret i32 [[XOR]]
753 %nega = xor i32 %a, -1
754 %and = and i32 %a, %b
755 %xor = xor i32 %nega, %b
756 %or = or i32 %xor, %and
760 define i32 @test48(i32 %a, i32 %b) {
761 ; CHECK-LABEL: @test48(
762 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
763 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
764 ; CHECK-NEXT: ret i32 [[XOR]]
766 %nega = xor i32 %a, -1
767 %and = and i32 %a, %b
768 %xor = xor i32 %b, %nega
769 %or = or i32 %xor, %and
773 define i32 @test49(i32 %a, i32 %b) {
774 ; CHECK-LABEL: @test49(
775 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
776 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
777 ; CHECK-NEXT: ret i32 [[XOR]]
779 %nega = xor i32 %a, -1
780 %and = and i32 %b, %a
781 %xor = xor i32 %b, %nega
782 %or = or i32 %xor, %and
786 define i32 @test50(i32 %a, i32 %b) {
787 ; CHECK-LABEL: @test50(
788 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
789 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
790 ; CHECK-NEXT: ret i32 [[XOR]]
792 %nega = xor i32 %a, -1
793 %and = and i32 %b, %a
794 %xor = xor i32 %nega, %b
795 %or = or i32 %xor, %and
799 define i32 @test51(i32 %a, i32 %b) {
800 ; CHECK-LABEL: @test51(
801 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
802 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
803 ; CHECK-NEXT: ret i32 [[XOR]]
805 %nega = xor i32 %a, -1
806 %and = and i32 %a, %b
807 %xor = xor i32 %nega, %b
808 %or = or i32 %and, %xor
812 define i32 @test52(i32 %a, i32 %b) {
813 ; CHECK-LABEL: @test52(
814 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
815 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
816 ; CHECK-NEXT: ret i32 [[XOR]]
818 %nega = xor i32 %a, -1
819 %and = and i32 %a, %b
820 %xor = xor i32 %b, %nega
821 %or = or i32 %and, %xor
825 define i32 @test53(i32 %a, i32 %b) {
826 ; CHECK-LABEL: @test53(
827 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
828 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[NEGA]]
829 ; CHECK-NEXT: ret i32 [[XOR]]
831 %nega = xor i32 %a, -1
832 %and = and i32 %b, %a
833 %xor = xor i32 %b, %nega
834 %or = or i32 %and, %xor
838 define i32 @test54(i32 %a, i32 %b) {
839 ; CHECK-LABEL: @test54(
840 ; CHECK-NEXT: [[NEGA:%.*]] = xor i32 [[A:%.*]], -1
841 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[NEGA]], [[B:%.*]]
842 ; CHECK-NEXT: ret i32 [[XOR]]
844 %nega = xor i32 %a, -1
845 %and = and i32 %b, %a
846 %xor = xor i32 %nega, %b
847 %or = or i32 %and, %xor
851 ; (A & B) | ~(A ^ B) -> ~(A ^ B)
853 define i32 @test55(i32 %a, i32 %b) {
854 ; CHECK-LABEL: @test55(
855 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
856 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
857 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
858 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[XNOR]]
859 ; CHECK-NEXT: ret i32 [[OR]]
861 %and = and i32 %a, %b
862 %xor = xor i32 %a, %b
863 %xnor = xor i32 %xor, -1
864 %or = or i32 %and, %xnor
868 ; ~(A ^ B) | (A & B) -> ~(A ^ B)
870 define i32 @test56(i32 %a, i32 %b) {
871 ; CHECK-LABEL: @test56(
872 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
873 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
874 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
875 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[XNOR]], [[AND]]
876 ; CHECK-NEXT: ret i32 [[OR]]
878 %and = and i32 %a, %b
879 %xor = xor i32 %a, %b
880 %xnor = xor i32 %xor, -1
881 %or = or i32 %xnor, %and
885 ; (B & A) | ~(A ^ B) -> ~(A ^ B)
887 define i32 @test57(i32 %a, i32 %b) {
888 ; CHECK-LABEL: @test57(
889 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[B:%.*]], [[A:%.*]]
890 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
891 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
892 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], [[XNOR]]
893 ; CHECK-NEXT: ret i32 [[OR]]
895 %and = and i32 %b, %a
896 %xor = xor i32 %a, %b
897 %xnor = xor i32 %xor, -1
898 %or = or i32 %and, %xnor
902 ; ~(A ^ B) | (A & B) -> ~(A ^ B)
904 define i32 @test58(i32 %a, i32 %b) {
905 ; CHECK-LABEL: @test58(
906 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[B:%.*]], [[A:%.*]]
907 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
908 ; CHECK-NEXT: [[XNOR:%.*]] = xor i32 [[XOR]], -1
909 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[XNOR]], [[AND]]
910 ; CHECK-NEXT: ret i32 [[OR]]
912 %and = and i32 %b, %a
913 %xor = xor i32 %a, %b
914 %xnor = xor i32 %xor, -1
915 %or = or i32 %xnor, %and
919 define i8 @lshr_perfect_mask(i8 %x) {
920 ; CHECK-LABEL: @lshr_perfect_mask(
921 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
922 ; CHECK-NEXT: ret i8 [[SH]]
925 %mask = and i8 %sh, 7 ; 0x07
929 define <2 x i8> @lshr_oversized_mask_splat(<2 x i8> %x) {
930 ; CHECK-LABEL: @lshr_oversized_mask_splat(
931 ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 5, i8 5>
932 ; CHECK-NEXT: ret <2 x i8> [[SH]]
934 %sh = lshr <2 x i8> %x, <i8 5, i8 5>
935 %mask = and <2 x i8> %sh, <i8 135, i8 135> ; 0x87
939 define i8 @lshr_undersized_mask(i8 %x) {
940 ; CHECK-LABEL: @lshr_undersized_mask(
941 ; CHECK-NEXT: [[SH:%.*]] = lshr i8 [[X:%.*]], 5
942 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SH]], -2
943 ; CHECK-NEXT: ret i8 [[MASK]]
946 %mask = and i8 %sh, -2 ; 0xFE
950 define <2 x i8> @shl_perfect_mask_splat(<2 x i8> %x) {
951 ; CHECK-LABEL: @shl_perfect_mask_splat(
952 ; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], <i8 6, i8 6>
953 ; CHECK-NEXT: ret <2 x i8> [[SH]]
955 %sh = shl <2 x i8> %x, <i8 6, i8 6>
956 %mask = and <2 x i8> %sh, <i8 192, i8 192> ; 0xC0
960 define i8 @shl_oversized_mask(i8 %x) {
961 ; CHECK-LABEL: @shl_oversized_mask(
962 ; CHECK-NEXT: [[SH:%.*]] = shl i8 [[X:%.*]], 6
963 ; CHECK-NEXT: ret i8 [[SH]]
966 %mask = and i8 %sh, 195 ; 0xC3
970 define <2 x i8> @shl_undersized_mask_splat(<2 x i8> %x) {
971 ; CHECK-LABEL: @shl_undersized_mask_splat(
972 ; CHECK-NEXT: [[SH:%.*]] = shl <2 x i8> [[X:%.*]], <i8 6, i8 6>
973 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i8> [[SH]], <i8 -120, i8 -120>
974 ; CHECK-NEXT: ret <2 x i8> [[MASK]]
976 %sh = shl <2 x i8> %x, <i8 6, i8 6>
977 %mask = and <2 x i8> %sh, <i8 136, i8 136> ; 0x88
981 define i32 @reversed_not(i32 %a) {
982 ; CHECK-LABEL: @reversed_not(
983 ; CHECK-NEXT: ret i32 -1
985 %nega = xor i32 -1, %a
986 %or = or i32 %a, %nega
990 define i64 @shl_or_and1(i32 %a, i1 %b) {
991 ; CHECK-LABEL: @shl_or_and1(
992 ; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i64
993 ; CHECK-NEXT: ret i64 [[TMP2]]
995 %tmp1 = zext i32 %a to i64
996 %tmp2 = zext i1 %b to i64
997 %tmp3 = shl nuw i64 %tmp1, 32
998 %tmp4 = or i64 %tmp2, %tmp3
999 %tmp5 = and i64 %tmp4, 1
1003 define i64 @shl_or_and2(i32 %a, i1 %b) {
1004 ; CHECK-LABEL: @shl_or_and2(
1005 ; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[B:%.*]] to i64
1006 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
1007 ; CHECK-NEXT: ret i64 [[TMP3]]
1009 %tmp1 = zext i1 %b to i64
1010 %tmp2 = zext i32 %a to i64
1011 %tmp3 = shl nuw i64 %tmp1, 32
1012 %tmp4 = or i64 %tmp2, %tmp3
1013 %tmp5 = and i64 %tmp4, 4294967296
1017 ; concatenate two 32-bit integers and extract lower 32-bit
1018 define i64 @shl_or_and3(i32 %a, i32 %b) {
1019 ; CHECK-LABEL: @shl_or_and3(
1020 ; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
1021 ; CHECK-NEXT: ret i64 [[TMP2]]
1023 %tmp1 = zext i32 %a to i64
1024 %tmp2 = zext i32 %b to i64
1025 %tmp3 = shl nuw i64 %tmp1, 32
1026 %tmp4 = or i64 %tmp2, %tmp3
1027 %tmp5 = and i64 %tmp4, 4294967295
1031 ; concatenate two 16-bit integers and extract higher 16-bit
1032 define i32 @shl_or_and4(i16 %a, i16 %b) {
1033 ; CHECK-LABEL: @shl_or_and4(
1034 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1035 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1036 ; CHECK-NEXT: ret i32 [[TMP3]]
1038 %tmp1 = zext i16 %a to i32
1039 %tmp2 = zext i16 %b to i32
1040 %tmp3 = shl nuw i32 %tmp1, 16
1041 %tmp4 = or i32 %tmp2, %tmp3
1042 %tmp5 = and i32 %tmp4, 4294901760 ; mask with 0xFFFF0000
1046 define i128 @shl_or_and5(i64 %a, i1 %b) {
1047 ; CHECK-LABEL: @shl_or_and5(
1048 ; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128
1049 ; CHECK-NEXT: ret i128 [[TMP2]]
1051 %tmp1 = zext i64 %a to i128
1052 %tmp2 = zext i1 %b to i128
1053 %tmp3 = shl nuw i128 %tmp1, 64
1054 %tmp4 = or i128 %tmp2, %tmp3
1055 %tmp5 = and i128 %tmp4, 1
1059 ; A variation of above test cases; it fails due to the mask value
1060 define i32 @shl_or_and6(i16 %a, i16 %b) {
1061 ; CHECK-LABEL: @shl_or_and6(
1062 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1063 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1064 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1065 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
1066 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65535
1067 ; CHECK-NEXT: ret i32 [[TMP5]]
1069 %tmp1 = zext i16 %a to i32
1070 %tmp2 = zext i16 %b to i32
1071 %tmp3 = shl nuw i32 %tmp1, 16
1072 %tmp4 = or i32 %tmp2, %tmp3
1073 %tmp5 = and i32 %tmp4, 4294901761 ; mask with 0xFFFF0001
1077 ; A variation of above test cases; it fails due to the mask value
1078 define i32 @shl_or_and7(i16 %a, i16 %b) {
1079 ; CHECK-LABEL: @shl_or_and7(
1080 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1081 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1082 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1083 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
1084 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -131072
1085 ; CHECK-NEXT: ret i32 [[TMP5]]
1087 %tmp1 = zext i16 %a to i32
1088 %tmp2 = zext i16 %b to i32
1089 %tmp3 = shl nuw i32 %tmp1, 16
1090 %tmp4 = or i32 %tmp2, %tmp3
1091 %tmp5 = and i32 %tmp4, 4294836224 ; mask with 0xFFFE0000
1095 ; A variation of above test cases; it fails due to the mask value
1096 define i32 @shl_or_and8(i16 %a, i16 %b) {
1097 ; CHECK-LABEL: @shl_or_and8(
1098 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
1099 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
1100 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
1101 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
1102 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 131071
1103 ; CHECK-NEXT: ret i32 [[TMP5]]
1105 %tmp1 = zext i16 %a to i32
1106 %tmp2 = zext i16 %b to i32
1107 %tmp3 = shl nuw i32 %tmp1, 16
1108 %tmp4 = or i32 %tmp2, %tmp3
1109 %tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF
1113 define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) {
1114 ; CHECK-LABEL: @shl_or_and1v(
1115 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
1116 ; CHECK-NEXT: ret <2 x i64> [[TMP2]]
1118 %tmp1 = zext <2 x i32> %a to <2 x i64>
1119 %tmp2 = zext <2 x i1> %b to <2 x i64>
1120 %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
1121 %tmp4 = or <2 x i64> %tmp3, %tmp2
1122 %tmp5 = and <2 x i64> %tmp4, <i64 1, i64 1>
1126 define <2 x i64> @shl_or_and2v(<2 x i32> %a, <2 x i1> %b) {
1127 ; CHECK-LABEL: @shl_or_and2v(
1128 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
1129 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32>
1130 ; CHECK-NEXT: ret <2 x i64> [[TMP3]]
1132 %tmp1 = zext <2 x i1> %b to <2 x i64>
1133 %tmp2 = zext <2 x i32> %a to <2 x i64>
1134 %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
1135 %tmp4 = or <2 x i64> %tmp2, %tmp3
1136 %tmp5 = and <2 x i64> %tmp4, <i64 4294967296, i64 4294967296>
1140 define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) {
1141 ; A variation of above test case, but fails due to the mask value
1142 ; CHECK-LABEL: @shl_or_and3v(
1143 ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32>
1144 ; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32>
1145 ; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i32> [[TMP1]], <i32 16, i32 16>
1146 ; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP2]], [[TMP3]]
1147 ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i32> [[TMP4]], <i32 -65535, i32 -65535>
1148 ; CHECK-NEXT: ret <2 x i32> [[TMP5]]
1150 %tmp1 = zext <2 x i16> %a to <2 x i32>
1151 %tmp2 = zext <2 x i16> %b to <2 x i32>
1152 %tmp3 = shl nuw <2 x i32> %tmp1, <i32 16, i32 16>
1153 %tmp4 = or <2 x i32> %tmp2, %tmp3
1154 %tmp5 = and <2 x i32> %tmp4, <i32 4294901761, i32 4294901761> ; mask with 0xFFFF0001