utils/TableGen/CodeGenInstruction.h

   1 //===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines a wrapper class for the 'Instruction' TableGen class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
  14 #define LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
  15
  16 #include "llvm/ADT/StringRef.h"
  17 #include "llvm/Support/MachineValueType.h"
  18 #include "llvm/Support/SMLoc.h"
  19 #include <string>
  20 #include <utility>
  21 #include <vector>
  22
  23 namespace llvm {
  24 template <typename T> class ArrayRef;
  25   class Record;
  26   class DagInit;
  27   class CodeGenTarget;
  28
  29   class CGIOperandList {
  30   public:
  31     class ConstraintInfo {
  32       enum { None, EarlyClobber, Tied } Kind;
  33       unsigned OtherTiedOperand;
  34     public:
  35       ConstraintInfo() : Kind(None) {}
  36
  37       static ConstraintInfo getEarlyClobber() {
  38         ConstraintInfo I;
  39         I.Kind = EarlyClobber;
  40         I.OtherTiedOperand = 0;
  41         return I;
  42       }
  43
  44       static ConstraintInfo getTied(unsigned Op) {
  45         ConstraintInfo I;
  46         I.Kind = Tied;
  47         I.OtherTiedOperand = Op;
  48         return I;
  49       }
  50
  51       bool isNone() const { return Kind == None; }
  52       bool isEarlyClobber() const { return Kind == EarlyClobber; }
  53       bool isTied() const { return Kind == Tied; }
  54
  55       unsigned getTiedOperand() const {
  56         assert(isTied());
  57         return OtherTiedOperand;
  58       }
  59
  60       bool operator==(const ConstraintInfo &RHS) const {
  61         if (Kind != RHS.Kind)
  62           return false;
  63         if (Kind == Tied && OtherTiedOperand != RHS.OtherTiedOperand)
  64           return false;
  65         return true;
  66       }
  67       bool operator!=(const ConstraintInfo &RHS) const {
  68         return !(*this == RHS);
  69       }
  70     };
  71
  72     /// OperandInfo - The information we keep track of for each operand in the
  73     /// operand list for a tablegen instruction.
  74     struct OperandInfo {
  75       /// Rec - The definition this operand is declared as.
  76       ///
  77       Record *Rec;
  78
  79       /// Name - If this operand was assigned a symbolic name, this is it,
  80       /// otherwise, it's empty.
  81       std::string Name;
  82
  83       /// PrinterMethodName - The method used to print operands of this type in
  84       /// the asmprinter.
  85       std::string PrinterMethodName;
  86
  87       /// EncoderMethodName - The method used to get the machine operand value
  88       /// for binary encoding. "getMachineOpValue" by default.
  89       std::string EncoderMethodName;
  90
  91       /// OperandType - A value from MCOI::OperandType representing the type of
  92       /// the operand.
  93       std::string OperandType;
  94
  95       /// MIOperandNo - Currently (this is meant to be phased out), some logical
  96       /// operands correspond to multiple MachineInstr operands.  In the X86
  97       /// target for example, one address operand is represented as 4
  98       /// MachineOperands.  Because of this, the operand number in the
  99       /// OperandList may not match the MachineInstr operand num.  Until it
 100       /// does, this contains the MI operand index of this operand.
 101       unsigned MIOperandNo;
 102       unsigned MINumOperands;   // The number of operands.
 103
 104       /// DoNotEncode - Bools are set to true in this vector for each operand in
 105       /// the DisableEncoding list.  These should not be emitted by the code
 106       /// emitter.
 107       std::vector<bool> DoNotEncode;
 108
 109       /// MIOperandInfo - Default MI operand type. Note an operand may be made
 110       /// up of multiple MI operands.
 111       DagInit *MIOperandInfo;
 112
 113       /// Constraint info for this operand.  This operand can have pieces, so we
 114       /// track constraint info for each.
 115       std::vector<ConstraintInfo> Constraints;
 116
 117       OperandInfo(Record *R, const std::string &N, const std::string &PMN,
 118                   const std::string &EMN, const std::string &OT, unsigned MION,
 119                   unsigned MINO, DagInit *MIOI)
 120       : Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN),
 121         OperandType(OT), MIOperandNo(MION), MINumOperands(MINO),
 122         MIOperandInfo(MIOI) {}
 123
 124
 125       /// getTiedOperand - If this operand is tied to another one, return the
 126       /// other operand number.  Otherwise, return -1.
 127       int getTiedRegister() const {
 128         for (unsigned j = 0, e = Constraints.size(); j != e; ++j) {
 129           const CGIOperandList::ConstraintInfo &CI = Constraints[j];
 130           if (CI.isTied()) return CI.getTiedOperand();
 131         }
 132         return -1;
 133       }
 134     };
 135
 136     CGIOperandList(Record *D);
 137
 138     Record *TheDef;            // The actual record containing this OperandList.
 139
 140     /// NumDefs - Number of def operands declared, this is the number of
 141     /// elements in the instruction's (outs) list.
 142     ///
 143     unsigned NumDefs;
 144
 145     /// OperandList - The list of declared operands, along with their declared
 146     /// type (which is a record).
 147     std::vector<OperandInfo> OperandList;
 148
 149     // Information gleaned from the operand list.
 150     bool isPredicable;
 151     bool hasOptionalDef;
 152     bool isVariadic;
 153
 154     // Provide transparent accessors to the operand list.
 155     bool empty() const { return OperandList.empty(); }
 156     unsigned size() const { return OperandList.size(); }
 157     const OperandInfo &operator[](unsigned i) const { return OperandList[i]; }
 158     OperandInfo &operator[](unsigned i) { return OperandList[i]; }
 159     OperandInfo &back() { return OperandList.back(); }
 160     const OperandInfo &back() const { return OperandList.back(); }
 161
 162     typedef std::vector<OperandInfo>::iterator iterator;
 163     typedef std::vector<OperandInfo>::const_iterator const_iterator;
 164     iterator begin() { return OperandList.begin(); }
 165     const_iterator begin() const { return OperandList.begin(); }
 166     iterator end() { return OperandList.end(); }
 167     const_iterator end() const { return OperandList.end(); }
 168
 169     /// getOperandNamed - Return the index of the operand with the specified
 170     /// non-empty name.  If the instruction does not have an operand with the
 171     /// specified name, abort.
 172     unsigned getOperandNamed(StringRef Name) const;
 173
 174     /// hasOperandNamed - Query whether the instruction has an operand of the
 175     /// given name. If so, return true and set OpIdx to the index of the
 176     /// operand. Otherwise, return false.
 177     bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
 178
 179     /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
 180     /// where $foo is a whole operand and $foo.bar refers to a suboperand.
 181     /// This aborts if the name is invalid.  If AllowWholeOp is true, references
 182     /// to operands with suboperands are allowed, otherwise not.
 183     std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
 184                                                   bool AllowWholeOp = true);
 185
 186     /// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
 187     /// flat machineinstr operand #.
 188     unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
 189       return OperandList[Op.first].MIOperandNo + Op.second;
 190     }
 191
 192     /// getSubOperandNumber - Unflatten a operand number into an
 193     /// operand/suboperand pair.
 194     std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
 195       for (unsigned i = 0; ; ++i) {
 196         assert(i < OperandList.size() && "Invalid flat operand #");
 197         if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
 198           return std::make_pair(i, Op-OperandList[i].MIOperandNo);
 199       }
 200     }
 201
 202
 203     /// isFlatOperandNotEmitted - Return true if the specified flat operand #
 204     /// should not be emitted with the code emitter.
 205     bool isFlatOperandNotEmitted(unsigned FlatOpNo) const {
 206       std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo);
 207       if (OperandList[Op.first].DoNotEncode.size() > Op.second)
 208         return OperandList[Op.first].DoNotEncode[Op.second];
 209       return false;
 210     }
 211
 212     void ProcessDisableEncoding(std::string Value);
 213   };
 214
 215
 216   class CodeGenInstruction {
 217   public:
 218     Record *TheDef;            // The actual record defining this instruction.
 219     StringRef Namespace;       // The namespace the instruction is in.
 220
 221     /// AsmString - The format string used to emit a .s file for the
 222     /// instruction.
 223     std::string AsmString;
 224
 225     /// Operands - This is information about the (ins) and (outs) list specified
 226     /// to the instruction.
 227     CGIOperandList Operands;
 228
 229     /// ImplicitDefs/ImplicitUses - These are lists of registers that are
 230     /// implicitly defined and used by the instruction.
 231     std::vector<Record*> ImplicitDefs, ImplicitUses;
 232
 233     // Various boolean values we track for the instruction.
 234     bool isPreISelOpcode : 1;
 235     bool isReturn : 1;
 236     bool isEHScopeReturn : 1;
 237     bool isBranch : 1;
 238     bool isIndirectBranch : 1;
 239     bool isCompare : 1;
 240     bool isMoveImm : 1;
 241     bool isMoveReg : 1;
 242     bool isBitcast : 1;
 243     bool isSelect : 1;
 244     bool isBarrier : 1;
 245     bool isCall : 1;
 246     bool isAdd : 1;
 247     bool isTrap : 1;
 248     bool canFoldAsLoad : 1;
 249     bool mayLoad : 1;
 250     bool mayLoad_Unset : 1;
 251     bool mayStore : 1;
 252     bool mayStore_Unset : 1;
 253     bool mayRaiseFPException : 1;
 254     bool isPredicable : 1;
 255     bool isConvertibleToThreeAddress : 1;
 256     bool isCommutable : 1;
 257     bool isTerminator : 1;
 258     bool isReMaterializable : 1;
 259     bool hasDelaySlot : 1;
 260     bool usesCustomInserter : 1;
 261     bool hasPostISelHook : 1;
 262     bool hasCtrlDep : 1;
 263     bool isNotDuplicable : 1;
 264     bool hasSideEffects : 1;
 265     bool hasSideEffects_Unset : 1;
 266     bool isAsCheapAsAMove : 1;
 267     bool hasExtraSrcRegAllocReq : 1;
 268     bool hasExtraDefRegAllocReq : 1;
 269     bool isCodeGenOnly : 1;
 270     bool isPseudo : 1;
 271     bool isRegSequence : 1;
 272     bool isExtractSubreg : 1;
 273     bool isInsertSubreg : 1;
 274     bool isConvergent : 1;
 275     bool hasNoSchedulingInfo : 1;
 276     bool FastISelShouldIgnore : 1;
 277     bool hasChain : 1;
 278     bool hasChain_Inferred : 1;
 279     bool variadicOpsAreDefs : 1;
 280
 281     std::string DeprecatedReason;
 282     bool HasComplexDeprecationPredicate;
 283
 284     /// Are there any undefined flags?
 285     bool hasUndefFlags() const {
 286       return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
 287     }
 288
 289     // The record used to infer instruction flags, or NULL if no flag values
 290     // have been inferred.
 291     Record *InferredFrom;
 292
 293     CodeGenInstruction(Record *R);
 294
 295     /// HasOneImplicitDefWithKnownVT - If the instruction has at least one
 296     /// implicit def and it has a known VT, return the VT, otherwise return
 297     /// MVT::Other.
 298     MVT::SimpleValueType
 299       HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const;
 300
 301
 302     /// FlattenAsmStringVariants - Flatten the specified AsmString to only
 303     /// include text from the specified variant, returning the new string.
 304     static std::string FlattenAsmStringVariants(StringRef AsmString,
 305                                                 unsigned Variant);
 306
 307     // Is the specified operand in a generic instruction implicitly a pointer.
 308     // This can be used on intructions that use typeN or ptypeN to identify
 309     // operands that should be considered as pointers even though SelectionDAG
 310     // didn't make a distinction between integer and pointers.
 311     bool isOperandAPointer(unsigned i) const;
 312   };
 313
 314
 315   /// CodeGenInstAlias - This represents an InstAlias definition.
 316   class CodeGenInstAlias {
 317   public:
 318     Record *TheDef;            // The actual record defining this InstAlias.
 319
 320     /// AsmString - The format string used to emit a .s file for the
 321     /// instruction.
 322     std::string AsmString;
 323
 324     /// Result - The result instruction.
 325     DagInit *Result;
 326
 327     /// ResultInst - The instruction generated by the alias (decoded from
 328     /// Result).
 329     CodeGenInstruction *ResultInst;
 330
 331
 332     struct ResultOperand {
 333     private:
 334       std::string Name;
 335       Record *R;
 336
 337       int64_t Imm;
 338     public:
 339       enum {
 340         K_Record,
 341         K_Imm,
 342         K_Reg
 343       } Kind;
 344
 345       ResultOperand(std::string N, Record *r)
 346           : Name(std::move(N)), R(r), Kind(K_Record) {}
 347       ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
 348       ResultOperand(Record *r) : R(r), Kind(K_Reg) {}
 349
 350       bool isRecord() const { return Kind == K_Record; }
 351       bool isImm() const { return Kind == K_Imm; }
 352       bool isReg() const { return Kind == K_Reg; }
 353
 354       StringRef getName() const { assert(isRecord()); return Name; }
 355       Record *getRecord() const { assert(isRecord()); return R; }
 356       int64_t getImm() const { assert(isImm()); return Imm; }
 357       Record *getRegister() const { assert(isReg()); return R; }
 358
 359       unsigned getMINumOperands() const;
 360     };
 361
 362     /// ResultOperands - The decoded operands for the result instruction.
 363     std::vector<ResultOperand> ResultOperands;
 364
 365     /// ResultInstOperandIndex - For each operand, this vector holds a pair of
 366     /// indices to identify the corresponding operand in the result
 367     /// instruction.  The first index specifies the operand and the second
 368     /// index specifies the suboperand.  If there are no suboperands or if all
 369     /// of them are matched by the operand, the second value should be -1.
 370     std::vector<std::pair<unsigned, int> > ResultInstOperandIndex;
 371
 372     CodeGenInstAlias(Record *R, CodeGenTarget &T);
 373
 374     bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
 375                          Record *InstOpRec, bool hasSubOps, ArrayRef<SMLoc> Loc,
 376                          CodeGenTarget &T, ResultOperand &ResOp);
 377   };
 378 }
 379
 380 #endif